Fix IPU handler - remove Latch

diff --git a/special/handler_data.vhd b/special/handler_data.vhd
index 63b838bb830a26da31592f60e2d3b32a9f58a937..13a9b21e8a14dc08d769dfaa8f750583bdbc7954 100644 (file)
--- a/special/handler_data.vhd
+++ b/special/handler_data.vhd
@@ -379,7 +379,7 @@ begin
                                  <= not (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full)
                                                                          or header_buffer_almost_full);
           elsif or_all(got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)) = '1' and
-                (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' then
+                (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' and LVL1_TRG_DATA_VALID_IN = '1' then
             got_busy_release(DATA_INTERFACE_NUMBER) <= '1';
           end if;
         end if;

diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd
index b48697a4181514a0e052135f4533b0d3df0222e1..62ddf6e04346333ba4063526839d7c5777bc006b 100644 (file)
--- a/special/handler_ipu.vhd
+++ b/special/handler_ipu.vhd
@@ -130,6 +130,7 @@ begin
       next_first_fifo_read       <= '0';
       next_dat_fifo_number       <= dat_fifo_number;
       next_suppress_output       <= suppress_output;
+      next_hdr_data_waiting      <= hdr_data_waiting;
 
       case current_state is
         when IDLE =>
@@ -427,8 +428,9 @@ assert    (
   STATUS_OUT(13)                  <= error_missing;
   STATUS_OUT(14)                  <= error_sync;
   STATUS_OUT(15)                  <= error_not_configured;
-  STATUS_OUT(23 downto 16)        <= DAT_DATA_IN(7 downto 0);
-  STATUS_OUT(31 downto 24)        <= (others => '0');
+  STATUS_OUT(23 downto 16)        <= DAT_HDR_DATA_IN(7 downto 0);
+  STATUS_OUT(24)                  <= hdr_data_waiting;
+  STATUS_OUT(31 downto 25)        <= (others => '0');
 
 
 end architecture;

diff --git a/special/tb_handler_lvl1.vhd b/special/tb_handler_lvl1.vhd
index 7060d1d0d9c7dbdb5532a452479211de8276a625..158affb61ce31bbe4eb338103c4f69ebae8c7653 100755 (executable)
--- a/special/tb_handler_lvl1.vhd
+++ b/special/tb_handler_lvl1.vhd
@@ -17,6 +17,8 @@ ARCHITECTURE behavior OF testbench IS
        );\r
        PORT(\r
                RESET : IN std_logic;\r
+    RESET_FLAGS_IN               : in  std_logic;\r
+    RESET_STATS_IN               : in  std_logic;\r
                CLOCK : IN std_logic;\r
                LVL1_TIMING_TRG_IN : IN std_logic;\r
                LVL1_PSEUDO_TMG_TRG_IN : IN std_logic;\r
@@ -25,7 +27,7 @@ ARCHITECTURE behavior OF testbench IS
                LVL1_TRG_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
                LVL1_TRG_CODE_IN : IN std_logic_vector(7 downto 0);\r
                LVL1_TRG_INFORMATION_IN : IN std_logic_vector(23 downto 0);\r
-               LVL1_INT_TRG_RESET_IN : IN std_logic;\r
+--             LVL1_INT_TRG_RESET_IN : IN std_logic;\r
                LVL1_INT_TRG_LOAD_IN : IN std_logic;\r
                LVL1_INT_TRG_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
                LVL1_ERROR_PATTERN_IN : IN std_logic_vector(31 downto 0);\r
@@ -39,7 +41,7 @@ ARCHITECTURE behavior OF testbench IS
                LVL1_VALID_TIMING_TRG_OUT : OUT std_logic;\r
                LVL1_VALID_NOTIMING_TRG_OUT : OUT std_logic;\r
                LVL1_INVALID_TRG_OUT : OUT std_logic;\r
-               STATUS_OUT : OUT std_logic_vector(31 downto 0);\r
+               STATUS_OUT : OUT std_logic_vector(63 downto 0);\r
                DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
                );\r
        END COMPONENT;\r
@@ -56,7 +58,7 @@ ARCHITECTURE behavior OF testbench IS
        SIGNAL LVL1_ERROR_PATTERN_OUT :  std_logic_vector(31 downto 0);\r
        SIGNAL LVL1_TRG_RELEASE_OUT :  std_logic;\r
        SIGNAL LVL1_INT_TRG_NUMBER_OUT :  std_logic_vector(15 downto 0);\r
-       SIGNAL LVL1_INT_TRG_RESET_IN :  std_logic;\r
+--     SIGNAL LVL1_INT_TRG_RESET_IN :  std_logic;\r
        SIGNAL LVL1_INT_TRG_LOAD_IN :  std_logic;\r
        SIGNAL LVL1_INT_TRG_COUNTER_IN :  std_logic_vector(15 downto 0);\r
        SIGNAL LVL1_TRG_DATA_VALID_OUT :  std_logic;\r
@@ -65,7 +67,7 @@ ARCHITECTURE behavior OF testbench IS
        SIGNAL LVL1_INVALID_TRG_OUT :  std_logic;\r
        SIGNAL LVL1_ERROR_PATTERN_IN :  std_logic_vector(31 downto 0);\r
        SIGNAL LVL1_TRG_RELEASE_IN :  std_logic;\r
-       SIGNAL STATUS_OUT :  std_logic_vector(31 downto 0);\r
+       SIGNAL STATUS_OUT :  std_logic_vector(63 downto 0);\r
        SIGNAL TRG_ENABLE_IN :  std_logic;\r
        SIGNAL TRG_INVERT_IN :  std_logic;\r
        SIGNAL DEBUG_OUT :  std_logic_vector(15 downto 0);\r
@@ -74,11 +76,13 @@ BEGIN
 \r
 -- Please check and add your generic clause manually\r
        uut: handler_lvl1 \r
-       GENERIC MAP(\r
+       generic map(\r
                TIMING_TRIGGER_RAW => 1\r
        )\r
-       PORT MAP(\r
+       port map(\r
                RESET => RESET,\r
+    RESET_FLAGS_IN => '0',\r
+    RESET_STATS_IN => '0',\r
                CLOCK => CLOCK,\r
                LVL1_TIMING_TRG_IN => LVL1_TIMING_TRG_IN,\r
                LVL1_PSEUDO_TMG_TRG_IN => LVL1_PSEUDO_TMG_TRG_IN,\r
@@ -90,7 +94,7 @@ BEGIN
                LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,\r
                LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT,\r
                LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT,\r
-               LVL1_INT_TRG_RESET_IN => LVL1_INT_TRG_RESET_IN,\r
+--             LVL1_INT_TRG_RESET_IN => LVL1_INT_TRG_RESET_IN,\r
                LVL1_INT_TRG_LOAD_IN => LVL1_INT_TRG_LOAD_IN,\r
                LVL1_INT_TRG_COUNTER_IN => LVL1_INT_TRG_COUNTER_IN,\r
                LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_DATA_VALID_OUT,\r
@@ -124,7 +128,7 @@ begin
        lvl1_trg_number_in <= x"0000";\r
        lvl1_trg_code_in <= x"00";\r
        lvl1_trg_information_in <= x"000000";\r
-       lvl1_int_trg_reset_in <= '0';\r
+--     lvl1_int_trg_reset_in <= '0';\r
        lvl1_int_trg_load_in <= '0';\r
        lvl1_int_trg_counter_in <= x"0000";\r
        lvl1_error_pattern_in <= x"0000_0000";\r
@@ -158,8 +162,13 @@ begin
        -- receive one normal timing trigger\r
        wait for 3 ns;\r
        lvl1_timing_trg_in <= '1';\r
-       wait for 111 ns;\r
+       wait for 100 ns;\r
        lvl1_timing_trg_in <= '0';      \r
+       wait for 10 ns;\r
+       lvl1_timing_trg_in <= '1';      \r
+       wait for 200 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+\r
        wait for 1000 ns;\r
 \r
        -- LVL1 packet is there\r
@@ -194,8 +203,13 @@ begin
        -- receive one normal timing trigger\r
        wait for 3 ns;\r
        lvl1_timing_trg_in <= '1';\r
-       wait for 111 ns;\r
+       wait for 100 ns;\r
        lvl1_timing_trg_in <= '0';      \r
+       wait for 10 ns;\r
+       lvl1_timing_trg_in <= '1';      \r
+       wait for 200 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       \r
        wait for 1000 ns;\r
 \r
        -- LVL1 packet is there\r