signal int2med : int2med_array_t(0 to INTERFACE_NUM-1);
signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx,
- bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx : CTRLBUS_RX;
+ bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx,
+ bustdc_rx, busddmtd_rx : CTRLBUS_RX;
signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx,
- bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx : CTRLBUS_TX;
+ bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,
+ busddmtd_tx : CTRLBUS_TX;
signal sed_error_i : std_logic;
signal bus_master_active : std_logic;
signal tristate_pings_i : std_logic;
signal cal_pulse_i : std_logic;
signal cal_pulse_q : std_logic_vector(1 downto 0);
-
+ signal fsm_active_int : std_logic;
+ signal fsm_ce_int : std_logic;
+ signal fsm_rst_int : std_logic;
+ signal fsm_clr_done_int : std_logic;
+ signal delay_value_int : std_logic_vector(9 downto 0);
+ signal delay_valid_int : std_logic;
+ signal ack_delay : std_logic_vector(2 downto 0);
+ signal ack_delay_x : std_logic;
+ signal phaser_start : std_logic;
+
begin
THE_TIME_COUNTER_PROC: process( clk_full_osc )
-- just for testing
tx_dlm_i <= dlm_send_qq;
send_dlm_word_i <= std_logic_vector(dlm_tag_ctr);
- enable_dlm_i <= test_reg(31);
- send_rst_i <= test_reg(30);
- tristate_pings_i <= test_reg(25);
+ enable_dlm_i <= test_reg(31); -- ONLY FOR TESTING
+ send_rst_i <= test_reg(30); -- ONLY FOR TESTING
+ tristate_pings_i <= test_reg(25); -- ONLY FOR TESTING
destroy_link_i <= test_reg(24); -- ONLY FOR TESTING
+ phaser_start <= test_reg(16); -- ONLY FOR TESTING
send_rst_word_i <= test_reg(15 downto 8); -- ONLY FOR TESTING
wap_requested_i <= test_reg(3 downto 0); -- ONLY FOR TESTING
THE_DDMTD: entity ddmtd
port map(
- AUXCLK => clk_sample,
- RESET => reset_i,
- PING_IN => HDR_IO(1),
- PONG_IN => HDR_IO(3),
- PING_OUT => ping_stretched_i,
- PONG_OUT => pong_stretched_i,
- START_PING_OUT => start_ping_i,
- START_PONG_OUT => start_pong_i,
- DELAY_VALUE_OUT => phaser_data(15 downto 0),
- DELAY_VALID_OUT => open,
- TOGGLE_OUT => toggle_i
+ AUXCLK => clk_sample,
+ RESET => reset_i,
+ PING_IN => HDR_IO(1),
+ PONG_IN => HDR_IO(3),
+ PING_OUT => ping_stretched_i,
+ PONG_OUT => pong_stretched_i,
+ START_PING_OUT => start_ping_i,
+ START_PONG_OUT => start_pong_i,
+ TOGGLE_OUT => toggle_i,
+ DELAY_VALUE_OUT => delay_value_int,
+ DELAY_VALID_OUT => delay_valid_int,
+ FSM_ACTIVE_IN => fsm_active_int,
+ FSM_CE_IN => fsm_ce_int,
+ FSM_RST_IN => fsm_rst_int,
+ FSM_CLR_DONE_OUT => fsm_clr_done_int
);
- phaser_data(31 downto 16) <= (others => '0');
+ THE_STATISTICS: entity statistics
+ port map(
+ AUXCLK => clk_sample,
+ RESET => reset_i,
+ DELAY_VALUE_IN => delay_value_int,
+ DELAY_VALID_IN => delay_valid_int,
+ FSM_START_IN => phaser_start,
+ FSM_CLR_DONE_IN => fsm_clr_done_int,
+ FSM_ACTIVE_OUT => fsm_active_int,
+ FSM_CE_OUT => fsm_ce_int,
+ FSM_RST_OUT => fsm_rst_int,
+ FSM_DONE_OUT => phaser_data(31),
+ RD_CLK => clk_sys,
+ RD_ADDRESS_IN => busddmtd_rx.addr(9 downto 0),
+ RD_DATA_OUT => phaser_data(17 downto 0)
+ );
+
+ phaser_data(30 downto 18) <= (others => '0');
+
+ -- simple readout
+ THE_ACK_DELAY_PROC: process( clk_sys )
+ begin
+ if( rising_edge(clk_sys) ) then
+ ack_delay <= ack_delay(1 downto 0) & ack_delay_x;
+ end if;
+ end process THE_ACK_DELAY_PROC;
+ ack_delay_x <= busddmtd_rx.read or busddmtd_rx.write;
+
+ busddmtd_tx.data <= phaser_data;
+ busddmtd_tx.ack <= ack_delay(2);
+ busddmtd_tx.nack <= '0';
+ busddmtd_tx.unknown <= '0';
+
THE_CAL_CLOCK_PROC: process( master_clk_i, reset_i )
begin
if ( reset_i = '1' ) then
---------------------------------------------------------------------------
-- PCSC: not used
---------------------------------------------------------------------------
--- bussci3_tx.data <= (others => '0');
--- bussci3_tx.ack <= '0';
--- bussci3_tx.nack <= '0';
--- bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+ bussci3_tx.data <= (others => '0');
+ bussci3_tx.ack <= '0';
+ bussci3_tx.nack <= '0';
+ bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
-- can be used for simple readback on debugging
- bussci3_tx.data <= phaser_data;
- bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
- bussci3_tx.nack <= '0';
- bussci3_tx.unknown <= '0';
+-- bussci3_tx.data <= phaser_data;
+-- bussci3_tx.ack <= ack_delay(2); --bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+-- bussci3_tx.nack <= '0';
+-- bussci3_tx.unknown <= '0';
---------------------------------------------------------------------------
-- PCSD: GbE
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 9,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, others => 0),
+ PORT_NUMBER => 10,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"f000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 10, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(6) => busgbereg_rx,
BUS_RX(7) => buscts_rx,
BUS_RX(8) => bustdc_rx,
+ BUS_RX(9) => busddmtd_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bustc_tx,
BUS_TX(2) => bussci1_tx,
BUS_TX(6) => busgbereg_tx,
BUS_TX(7) => buscts_tx,
BUS_TX(8) => bustdc_tx,
+ BUS_TX(9) => busddmtd_tx,
STAT_DEBUG => open
);
jspc29 / trb3sc.git / commitdiff