%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{Trigger Control Registers}
+\subsubsection{Trigger Control Registers, Trigger Logic}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
For all registers described in this subsection refer to the Fig.\ref{cts_logic}
+To enable trigger box logic which is described in this subsection (Fig.\ref{cts_logic})
+it is necessary to set register A0C5 to 40000000.
\begin{description}
\item [0xA089: Debug] Trigger logic debug out
\item [0xA09B -- 0xA0BA: Scaler] Scalers out
\item[Bit 6] Force update Shower pedestals trigger (write ..1..0)
\item[Bit 7] Disable Shower pedestals update (generated once during each spill off)
\item[Bit 11 -- 8] Select frequency for internally generated trigger - $781.25kHz/(2^{value})$
+ \item[Bit 12] Enable Shower calibration trigger
+ \item[Bit 13] Enable trigger from internal generator
\end{description}
+ \item [0xA099] Trigger logic debug
+ \item[Bit 3 -- 0] State machine debug: 0x1 - Idle; 0x2 - Waiting for readout start; 3 - sending latches; 4 - sending scalers; 5 - readout finished
+ \item[Bit 4] Beam inhibit in
\end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{CTS Control and Status Registers}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+When Trigger Logic is not used (A0C5 bit 30 = 0 ) the configuration of the used logic is simple (just accepting the input triggers see address A0C5).
+In this case when calibration trigger is set (0xA0C7;A0C5 bit 30 = 0) still the reference time/hold signal is send. When Trigger Logic is enabled and register 0xA0DC is used to overwrite trigger code. In this case if calibration trigger is send there is no reference time/hold signal.
+It is recommended to start system ether with simple or trigger logic and do not switch between them when it is running.
\begin{description}
\item[0xA091: LVL1 information] Busy flags and current trigger number and type on LVL1 channel
\begin{description}