Channel_200_DEBUG : out std_logic_vector(31 downto 0));
end component;
--- component Channel is
--- generic (
--- CHANNEL_ID : integer range 0 to 64);
--- port (
--- RESET_200 : in std_logic;
--- RESET_100 : in std_logic;
--- RESET_COUNTERS : in std_logic;
--- CLK_200 : in std_logic;
--- CLK_100 : in std_logic;
--- HIT_IN : in std_logic;
----- TRIGGER_IN : in std_logic; -- not used after version 1.3
--- TRIGGER_WIN_END_IN : in std_logic;
--- READ_EN_IN : in std_logic;
--- FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
--- FIFO_WCNT_OUT : out unsigned(7 downto 0);
--- FIFO_EMPTY_OUT : out std_logic;
--- FIFO_FULL_OUT : out std_logic;
--- FIFO_ALMOST_FULL_OUT : out std_logic;
--- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
--- EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
--- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
--- HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
--- ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
--- ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0);
--- Channel_DEBUG : out std_logic_vector(31 downto 0));
--- end component Channel;
-
--- component Channel_200 is
--- generic (
--- CHANNEL_ID : integer range 0 to 64);
--- port (
--- CLK_200 : in std_logic;
--- RESET_200 : in std_logic;
--- CLK_100 : in std_logic;
--- RESET_100 : in std_logic;
--- HIT_IN : in std_logic;
----- TRIGGER_IN : in std_logic; -- not used after version 1.3
--- TRIGGER_WIN_END_IN : in std_logic;
--- EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
--- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
--- READ_EN_IN : in std_logic;
--- FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
--- FIFO_WCNT_OUT : out unsigned(7 downto 0);
--- FIFO_EMPTY_OUT : out std_logic;
--- FIFO_FULL_OUT : out std_logic;
--- FIFO_ALMOST_FULL_OUT : out std_logic;
--- ENCODER_START_OUT : out std_logic;
--- ENCODER_FINISHED_OUT : out std_logic);
--- end component Channel_200;
-
-
component Readout is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end component;
-
+
+
component input_to_trigger_logic is
generic(
INPUTS : integer range 1 to 32 := 24;
);
end component;
+
+component serdes_full_ctc is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_full_ctc.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ ctc_urun_ch0_s : out std_logic;
+ ctc_orun_ch0_s : out std_logic;
+ ctc_ins_ch0_s : out std_logic;
+ ctc_del_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ ctc_urun_ch1_s : out std_logic;
+ ctc_orun_ch1_s : out std_logic;
+ ctc_ins_ch1_s : out std_logic;
+ ctc_del_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (15 downto 0);
+ tx_k_ch2 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ rxdata_ch2 : out std_logic_vector (15 downto 0);
+ rx_k_ch2 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch2 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch2 : out std_logic_vector (1 downto 0);
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ ctc_urun_ch2_s : out std_logic;
+ ctc_orun_ch2_s : out std_logic;
+ ctc_ins_ch2_s : out std_logic;
+ ctc_del_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (15 downto 0);
+ tx_k_ch3 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch3 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch3 : in std_logic_vector (1 downto 0);
+ rxdata_ch3 : out std_logic_vector (15 downto 0);
+ rx_k_ch3 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch3 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch3 : out std_logic_vector (1 downto 0);
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ ctc_urun_ch3_s : out std_logic;
+ ctc_orun_ch3_s : out std_logic;
+ ctc_ins_ch3_s : out std_logic;
+ ctc_del_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+component serdes_full_noctc is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_full_noctc.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (15 downto 0);
+ tx_k_ch2 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ rxdata_ch2 : out std_logic_vector (15 downto 0);
+ rx_k_ch2 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch2 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch2 : out std_logic_vector (1 downto 0);
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (15 downto 0);
+ tx_k_ch3 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch3 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch3 : in std_logic_vector (1 downto 0);
+ rxdata_ch3 : out std_logic_vector (15 downto 0);
+ rx_k_ch3 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch3 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch3 : out std_logic_vector (1 downto 0);
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_onboard_full is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (15 downto 0);
+ tx_k_ch2 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ rxdata_ch2 : out std_logic_vector (15 downto 0);
+ rx_k_ch2 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch2 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch2 : out std_logic_vector (1 downto 0);
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (15 downto 0);
+ tx_k_ch3 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch3 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch3 : in std_logic_vector (1 downto 0);
+ rxdata_ch3 : out std_logic_vector (15 downto 0);
+ rx_k_ch3 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch3 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch3 : out std_logic_vector (1 downto 0);
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_onboard_full_125 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_125.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (15 downto 0);
+ tx_k_ch2 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ rxdata_ch2 : out std_logic_vector (15 downto 0);
+ rx_k_ch2 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch2 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch2 : out std_logic_vector (1 downto 0);
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (15 downto 0);
+ tx_k_ch3 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch3 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch3 : in std_logic_vector (1 downto 0);
+ rxdata_ch3 : out std_logic_vector (15 downto 0);
+ rx_k_ch3 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch3 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch3 : out std_logic_vector (1 downto 0);
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_onboard_full_ctc is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_onboard_full_ctc.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ ctc_urun_ch0_s : out std_logic;
+ ctc_orun_ch0_s : out std_logic;
+ ctc_ins_ch0_s : out std_logic;
+ ctc_del_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ ctc_urun_ch1_s : out std_logic;
+ ctc_orun_ch1_s : out std_logic;
+ ctc_ins_ch1_s : out std_logic;
+ ctc_del_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (15 downto 0);
+ tx_k_ch2 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ rxdata_ch2 : out std_logic_vector (15 downto 0);
+ rx_k_ch2 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch2 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch2 : out std_logic_vector (1 downto 0);
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ ctc_urun_ch2_s : out std_logic;
+ ctc_orun_ch2_s : out std_logic;
+ ctc_ins_ch2_s : out std_logic;
+ ctc_del_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (15 downto 0);
+ tx_k_ch3 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch3 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch3 : in std_logic_vector (1 downto 0);
+ rxdata_ch3 : out std_logic_vector (15 downto 0);
+ rx_k_ch3 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch3 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch3 : out std_logic_vector (1 downto 0);
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ ctc_urun_ch3_s : out std_logic;
+ ctc_orun_ch3_s : out std_logic;
+ ctc_ins_ch3_s : out std_logic;
+ ctc_del_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_sync_0 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_0.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ tx_force_disp_ch0 : in std_logic;
+ tx_disp_sel_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_sync_125_0 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_125_0.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ tx_force_disp_ch0 : in std_logic;
+ tx_disp_sel_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component sfp_0_200_ctc is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_0_200_ctc.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ ctc_urun_ch0_s : out std_logic;
+ ctc_orun_ch0_s : out std_logic;
+ ctc_ins_ch0_s : out std_logic;
+ ctc_del_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component sfp_0_200_int is
+ generic (USER_CONFIG_FILE : String := "sfp_0_200_int.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component sfp_1_125_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component sfp_1_200_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component sfp_ctc_0_200_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_ctc_0_200_int.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (15 downto 0);
+ tx_k_ch0 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (15 downto 0);
+ rx_k_ch0 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ ctc_urun_ch0_s : out std_logic;
+ ctc_orun_ch0_s : out std_logic;
+ ctc_ins_ch0_s : out std_logic;
+ ctc_del_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
end package;
jspc29 / trb3.git / commitdiff