+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.version.all;
-use work.config.all;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.med_sync_define_RS.all;
-
-entity tomcat_gbe is
- port(
- -- clock oscillators
- CLK_200 : in std_logic;
- CLK_125 : in std_logic;
- -- SFP signals
- SFP_TX_DIS : out std_logic;
- SFP_LOS : in std_logic;
- SFP_RATESEL : out std_logic;
- SFP_MOD_0 : in std_logic; -- detect
- SFP_MOD_1 : inout std_logic; -- SCL
- SFP_MOD_2 : inout std_logic; -- SDA
- -- Flash, Reload
- FLASH_SCLK : out std_logic;
- FLASH_NCS : out std_logic;
- FLASH_MOSI : out std_logic;
- FLASH_MISO : in std_logic;
- FLASH_HOLD : out std_logic;
- FLASH_WP : out std_logic;
- FLASH_SELECT : in std_logic;
- FLASH_OVERRIDE : out std_logic;
- PROGRAMN : out std_logic;
- -- I2C (temperature, UID)
- I2C_SDA : inout std_logic;
- I2C_SCL : inout std_logic;
- -- LEDs
- LED : out std_logic_vector(3 downto 0);
- LED_SFP_YELLOW : out std_logic;
- LED_SFP_GREEN : out std_logic;
- LED_SFP_RED : out std_logic;
- -- LVDS intercom
--- INTCOM : inout std_logic_vector(9 downto 0); -- LVDS
- INTCOM : inout std_logic_vector(19 downto 0); -- LVCMOS
- -- timing measurements
- TIMING_TEST : inout std_logic;
- -- GPIO
- GPIO : out std_logic_vector(15 downto 0)
- );
-
- attribute syn_useioff : boolean;
- attribute syn_useioff of FLASH_NCS : signal is true;
- attribute syn_useioff of FLASH_SCLK : signal is true;
- attribute syn_useioff of FLASH_MOSI : signal is true;
- attribute syn_useioff of FLASH_MISO : signal is true;
-
-end entity;
-
-architecture arch of tomcat_gbe is
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- signal clk_sys : std_logic;
- signal GSR_N : std_logic;
- signal reset_i : std_logic;
- signal reset_n_i : std_logic;
- signal clear_i : std_logic;
- signal clear_n_i : std_logic;
-
- signal sd_led_green : std_logic;
- signal sd_led_yellow : std_logic;
- signal sd_led_red : std_logic;
-
- signal led_i : std_logic_vector(3 downto 0);
-
- signal uuid_i : std_logic_vector(63 downto 0);
-
- signal gsc_init_data : std_logic_vector(15 downto 0);
- signal gsc_reply_data : std_logic_vector(15 downto 0);
- signal gsc_init_read : std_logic;
- signal gsc_reply_read : std_logic;
- signal gsc_init_dataready : std_logic;
- signal gsc_reply_dataready : std_logic;
- signal gsc_init_packet_num : std_logic_vector(2 downto 0);
- signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
- signal gsc_busy : std_logic;
-
- signal reboot_from_gbe : std_logic;
- signal reset_via_gbe : std_logic;
-
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
-
- signal debug : std_logic_vector(127 downto 0);
- signal status : std_logic_vector(15 downto 0);
-
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-
- signal ctrlbus_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
- signal ctrlbus_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
- signal bus_master_active : std_logic;
-
- signal timer : TIMERS;
- signal additional_reg : std_logic_vector(31 downto 0);
- signal led_off : std_logic;
-
- signal flash_ncs_i : std_logic;
- signal flash_sclk_i : std_logic;
- signal flash_miso_i : std_logic;
- signal flash_mosi_i : std_logic;
-
- signal link_active : std_logic;
-
- -- the new FIFO interface
-
- -- 10: frame_start
- -- 9 : fifo_wr
- -- 8 : fifo_eof
- -- 7..0: data
- signal ul_rx_data : std_logic_vector(10 downto 0);
- signal ul_rx_frame_avail : std_logic;
- signal ul_rx_frame_req : std_logic;
- signal ul_rx_frame_ack : std_logic;
- signal ul_rx_fifofull : std_logic;
- signal ul_tx_data : std_logic_vector(10 downto 0);
- signal ul_tx_fifofull : std_logic;
-
- -- 10: frame_start
- -- 9 : fifo_wr
- -- 8 : fifo_eof
- -- 7..0: fifo_data
- type dl_rx_data_t is array(0 to 1) of std_logic_vector(10 downto 0);
- signal dl_rx_data : dl_rx_data_t;
- signal dl_rx_data_q : dl_rx_data_t;
- signal dl_rx_frame_req : std_logic_vector(1 downto 0);
- signal dl_rx_frame_ack : std_logic_vector(1 downto 0);
- signal dl_rx_frame_avail : std_logic_vector(1 downto 0);
- signal dl_rx_fifofull : std_logic_vector(1 downto 0);
- signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
- signal dl_tx_fifofull : std_logic_vector(1 downto 0);
-
- -- 10: frame_start
- -- 9 : fifo_wr
- -- 8 : fifo_eof
- -- 7..0: data
- signal local_rx_data : std_logic_vector(10 downto 0); -- CPU (RX) to 1:2 MUXes
- signal local_rx_frame_avail : std_logic;
- signal local_rx_frame_req : std_logic;
- signal local_rx_frame_ack : std_logic;
- signal local_rx_fifofull : std_logic;
- signal local_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to CPU (TX)
- signal local_tx_fifofull : std_logic;
- -- these signals go from multiplexer to UL (TX)
-
- signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
-
- signal dl_rx_port_mux : std_logic_vector(3 downto 0);
- signal ul_tx_port_sel : std_logic;
- signal dl_tx_port_sel : std_logic;
- signal local_tx_port_sel : std_logic;
-
- signal sniffer_data : std_logic_vector(7 downto 0);
- signal sniffer_wr : std_logic;
- signal sniffer_eof : std_logic;
- signal sniffer_error : std_logic;
-
- signal fwd_mac_int : std_logic_vector(47 downto 0);
- signal fwd_ip_int : std_logic_vector(31 downto 0);
- signal fwd_port_int : std_logic_vector(15 downto 0);
- signal fwd_data_int : std_logic_vector(7 downto 0);
- signal fwd_ready_int : std_logic;
- signal fwd_full_int : std_logic;
- signal fwd_data_valid_int : std_logic;
- signal fwd_sop_int : std_logic;
- signal fwd_eop_int : std_logic;
- signal fwd_busy_int : std_logic;
-
- signal control_reg : std_logic_vector(31 downto 0);
- signal aux_reg : std_logic_vector(31 downto 0);
-
- signal tick_ms_int : std_logic;
- signal tick_us_int : std_logic;
-
- signal reboot_int : std_logic;
-
- signal sgl_debug : std_logic_vector(15 downto 0);
-
- signal blink_counter : unsigned(9 downto 0);
-
- signal oob_reg_0_int : std_logic_vector(31 downto 0);
- signal oob_reg_1_int : std_logic_vector(31 downto 0);
- signal oob_reg_2_int : std_logic_vector(31 downto 0);
- signal oob_reg_3_int : std_logic_vector(31 downto 0);
-
- signal dlm_found_int : std_logic;
- signal dlm_inject_int : std_logic;
- signal dlm_tx_data_int : std_logic_vector(7 downto 0);
- signal dlm_rx_data_int : std_logic_vector(7 downto 0);
-
- signal dlm_ctr : unsigned(23 downto 0);
- signal rst_dlm_ctr_x : std_logic;
- signal rst_dlm_ctr : std_logic;
-
-begin
-
----------------------------------------------------------------------------
--- Important pins
----------------------------------------------------------------------------
--- PROGRAMN <= '1';
--- FLASH_OVERRIDE <= '1';
--- FLASH_SCLK <= 'Z';
--- FLASH_NCS <= '1';
--- FLASH_MOSI <= '0';
--- FLASH_HOLD <= '1';
--- FLASH_WP <= '1';
-
----------------------------------------------------------------------------
--- Clock & Reset Handling
----------------------------------------------------------------------------
- THE_CLOCK_RESET_HANDLER: entity clock_reset_handler
- port map(
- CLK_IN => CLK_125,
- GLOBAL_RESET_IN => '0', -- for sync operation
- RESET_FROM_NET_IN => '0', -- unused
- --
- CLK_OUT => clk_sys,
- RESET_OUT => reset_i,
- RESET_N_OUT => reset_n_i,
- CLEAR_OUT => clear_i,
- CLEAR_N_OUT => clear_n_i,
- --
- TICK_MS_OUT => tick_ms_int,
- TICK_US_OUT => tick_us_int,
- --
- LED_RED_OUT => open,
- LED_GREEN_OUT => open
- );
-
-
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-THE_BLINK_COUNTER_PROC: process( clk_sys )
-begin
- if( rising_edge(clk_sys) ) then
- if( tick_ms_int = '1' ) then
- blink_counter <= blink_counter + 1;
- end if;
- end if;
-end process THE_BLINK_COUNTER_PROC;
-
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--- DLM timing generator
-THE_DLM_SEND_PROC: process( clk_sys )
-begin
- if( rising_edge(clk_sys) ) then
- rst_dlm_ctr <= rst_dlm_ctr_x;
- if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
- dlm_ctr <= (others => '0');
- elsif( aux_reg(31) = '1' ) then
- dlm_ctr <= dlm_ctr + 1;
- end if;
- end if;
-end process THE_DLM_SEND_PROC;
-
-rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
-
----------------------------------------------------------------------------
--- GbE interface (SFP)
----------------------------------------------------------------------------
- GBE_SFP_INTERFACE: entity gbe_med_fifo
- generic map(
- SERDES_NUM => 0
- )
- port map(
- RESET => reset_i,
- RESET_N => reset_n_i,
- CLEAR => clear_i,
- CLEAR_N => clear_n_i,
- CLK_125 => clk_sys,
- -- FIFO interface RX
- FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
- FIFO_WR_OUT => ul_rx_data(9),
- FIFO_DATA_OUT => ul_rx_data(8 downto 0),
- FRAME_START_OUT => ul_rx_data(10),
- FRAME_REQ_IN => ul_rx_frame_req,
- FRAME_ACK_OUT => ul_rx_frame_ack,
- FRAME_AVAIL_OUT => ul_rx_frame_avail,
- -- FIFO interface TX
- FIFO_WR_IN => ul_tx_data(9),
- FIFO_DATA_IN => ul_tx_data(8 downto 0),
- FRAME_START_IN => ul_tx_data(10),
- FIFO_FULL_OUT => ul_tx_fifofull,
- --SFP Connection
- SD_PRSNT_N_IN => SFP_MOD_0,
- SD_LOS_IN => SFP_LOS,
- SD_TXDIS_OUT => SFP_TX_DIS,
- -- internal sniffer port
- MAC_RX_DATA_OUT => sniffer_data,
- MAC_RX_WRITE_OUT => sniffer_wr,
- MAC_RX_EOF_OUT => sniffer_eof,
- MAC_RX_ERROR_OUT => sniffer_error,
- -- Status
- PCS_AN_READY_OUT => open,
- LINK_ACTIVE_OUT => link_active, -- only needed on UL port for SCTRL
- TICK_MS_IN => tick_ms_int,
- -- DLM
- DLM_INJECT_IN => '0',
- DLM_DATA_IN => x"00",
- DLM_FOUND_OUT => open,
- DLM_DATA_OUT => open,
- -- Debug
- STATUS_OUT => status(7 downto 0),
- DEBUG_OUT => open
- );
-
- debug(127 downto 64) <= (others => '0');
-
----------------------------------------------------------------------------
--- GbE interface (copper)
----------------------------------------------------------------------------
- GBE_COPPER_INTERFACE: entity gbe_med_fifo
- generic map(
- SERDES_NUM => 3
- )
- port map(
- RESET => reset_i,
- RESET_N => reset_n_i,
- CLEAR => clear_i,
- CLEAR_N => clear_n_i,
- CLK_125 => clk_sys,
- -- FIFO interface RX
- FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
- FIFO_WR_OUT => dl_rx_data(1)(9),
- FIFO_DATA_OUT => dl_rx_data(1)(8 downto 0),
- FRAME_START_OUT => dl_rx_data(1)(10),
- FRAME_REQ_IN => dl_rx_frame_req(1),
- FRAME_ACK_OUT => dl_rx_frame_ack(1),
- FRAME_AVAIL_OUT => dl_rx_frame_avail(1),
- -- FIFO interface TX
- FIFO_WR_IN => dl_tx_data(9),
- FIFO_DATA_IN => dl_tx_data(8 downto 0),
- FRAME_START_IN => dl_tx_data(10),
- FIFO_FULL_OUT => dl_tx_fifofull(1),
- --SFP Connection
- SD_PRSNT_N_IN => '0',
- SD_LOS_IN => '0',
- SD_TXDIS_OUT => open,
- -- internal sniffer port
- -- Status
- PCS_AN_READY_OUT => open,
- LINK_ACTIVE_OUT => open,
- TICK_MS_IN => tick_ms_int,
- -- DLM
- DLM_INJECT_IN => dlm_inject_int,
- DLM_DATA_IN => dlm_tx_data_int,
- DLM_FOUND_OUT => dlm_found_int,
- DLM_DATA_OUT => dlm_rx_data_int,
- -- Debug
- STATUS_OUT => open,
- DEBUG_OUT => debug(63 downto 0) --open
- );
-
- dlm_inject_int <= rst_dlm_ctr;
- dlm_tx_data_int <= control_reg(7 downto 0);
-
----------------------------------------------------------------------------
----------------------------------------------------------------------------
- THE_SGL_CTRL: entity sgl_ctrl
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- -- UL port
- UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full
- UL_FRAME_AVAIL_IN => ul_rx_frame_avail, -- UL RX has frames for DL/LOCAL
- UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
- UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
- -- DL ports (includes SCTRL)
- DL_FIFOFULL_IN(1 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
- DL_FRAME_AVAIL_IN(1 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
- DL_FRAME_REQ_OUT(1 downto 0) => dl_rx_frame_req, -- DL RXn request to send
- DL_FRAME_ACK_IN(1 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
- -- CPU port -- not needed
- -- MUX control
- DL_RX_PORT_SEL_OUT(1 downto 0) => open,
- DL_RX_PORT_MUX_OUT => dl_rx_port_mux,
- DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
- LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
- UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
- --
- DEBUG => sgl_debug --open
- );
-
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
-
--- debug(7 downto 0) <= ul_rx_data(7 downto 0);
--- debug(15 downto 8) <= ul_tx_data(7 downto 0);
--- debug(16) <= ul_rx_data(9);
--- debug(17) <= ul_tx_data(9);
--- debug(18) <= ul_rx_data(10);
--- debug(19) <= ul_tx_data(10);
--- debug(20) <= ul_rx_data(8);
--- debug(21) <= ul_tx_data(8);
--- debug(22) <= ul_rx_frame_req;
--- debug(23) <= ul_rx_frame_ack;
--- debug(24) <= ul_rx_frame_avail;
--- debug(25) <= dl_rx_frame_req(0);
--- debug(26) <= dl_rx_frame_ack(0);
--- debug(27) <= dl_rx_frame_avail(0);
--- debug(31 downto 28) <= sgl_debug(3 downto 0);
--- debug(32) <= dl_rx_port_mux(1);
--- debug(33) <= clk_sys;
-
----------------------------------------------------------------------------
--- Multiplexers for data streams
----------------------------------------------------------------------------
- THE_PIPELINING: for I in 0 to 1 generate
- dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys);
- end generate THE_PIPELINING;
-
- local_rx_data <= (others => '0'); -- no local CPU port
-
- THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q )
- begin
- case dl_rx_port_mux is
- when x"0" => switch_rx_data <= dl_rx_data_q(0);
- when x"1" => switch_rx_data <= dl_rx_data_q(1);
- when others => switch_rx_data <= (others => '0');
- end case;
- end process THE_DL_RX_MUX;
-
- ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data; -- not needed
-
- local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data; -- not needed
-
- dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; -- not needed
-
----------------------------------------------------------------------------
--- GbE wrapper without med interface
----------------------------------------------------------------------------
- GBE: entity work.gbe_wrapper_fifo
- generic map(
- LINK_HAS_SLOWCTRL => '1',
- LINK_HAS_DHCP => '1',
- LINK_HAS_ARP => '1',
- LINK_HAS_PING => '1',
- LINK_HAS_FWD => '1'
- )
- port map(
- CLK_125_IN => clk_sys,
- RESET => reset_i,
- GSR_N => reset_n_i,
- -- we connect to FIFO interface directly
- -- FIFO interface TX (send frames)
- FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
- FIFO_FULL_IN => ul_tx_fifofull,
- FIFO_WR_OUT => dl_rx_data(0)(9),
- FRAME_REQ_IN => dl_rx_frame_req(0),
- FRAME_ACK_OUT => dl_rx_frame_ack(0),
- FRAME_AVAIL_OUT => dl_rx_frame_avail(0),
- FRAME_START_OUT => dl_rx_data(0)(10),
- -- FIFO interface RX (receive frames)
- MAC_RX_DATA_IN => sniffer_data,
- MAC_RX_WRITE_IN => sniffer_wr,
- MAC_RX_EOF_IN => sniffer_eof,
- MAC_RX_ERROR_IN => sniffer_error,
- --
- PCS_AN_READY_IN => link_active,
- LINK_ACTIVE_IN => link_active,
- -- unique adresses
- MC_UNIQUE_ID_IN => timer.uid,
- MY_TRBNET_ADDRESS_IN => timer.network_address,
- ISSUE_REBOOT_OUT => reboot_from_gbe,
- -- slow control by GbE
- GSC_CLK_IN => clk_sys,
- GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
- GSC_INIT_DATA_OUT => gsc_init_data,
- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
- GSC_INIT_READ_IN => gsc_init_read,
- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
- GSC_REPLY_DATA_IN => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
- GSC_REPLY_READ_OUT => gsc_reply_read,
- GSC_BUSY_IN => gsc_busy,
- -- Forwarder
- FWD_DST_MAC_IN => fwd_mac_int,
- FWD_DST_IP_IN => fwd_ip_int,
- FWD_DST_UDP_IN => fwd_port_int,
- FWD_DATA_IN => fwd_data_int,
- FWD_DATA_VALID_IN => fwd_data_valid_int,
- FWD_SOP_IN => fwd_sop_int,
- FWD_EOP_IN => fwd_eop_int,
- FWD_READY_OUT => fwd_ready_int,
- FWD_FULL_OUT => fwd_full_int,
- --
- OOB_REGISTER_0_OUT => oob_reg_0_int,
- OOB_REGISTER_1_OUT => oob_reg_1_int,
- OOB_REGISTER_2_OUT => oob_reg_2_int,
- OOB_REGISTER_3_OUT => oob_reg_3_int,
- -- reset
- MAKE_RESET_OUT => reset_via_gbe,
- -- debug
- STATUS_OUT => status(15 downto 8),
- DEBUG_OUT => open
- );
-
- THE_FWD_TEST: entity fwd_test_random
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- --
- FWD_ENABLE_IN => additional_reg(31),
- FWD_DELAY_IN => control_reg(31 downto 16),
--- FWD_SIZE_IN => control_reg(15 downto 0),
- FWD_START_IN => tick_us_int,
- FWD_BUSY_OUT => fwd_busy_int, --open
- --
- FWD_READY_IN => fwd_ready_int,
- FWD_FULL_IN => fwd_full_int,
- FWD_DATA_OUT => fwd_data_int,
- FWD_DATA_VALID_OUT => fwd_data_valid_int,
- FWD_SOP_OUT => fwd_sop_int,
- FWD_EOP_OUT => fwd_eop_int,
- --
- DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SCTRL endpoint for GbE standalone
----------------------------------------------------------------------------
- THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
- generic map(
- FIFO_TO_INT_DEPTH => 6,
- FIFO_TO_APL_DEPTH => 6,
- APL_WRITE_ALL_WORDS => c_NO,
- INIT_ADDRESS => INIT_ADDRESS,
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- REGIO_INIT_ENDPOINT_ID => x"0001",
- REGIO_USE_VAR_ENDPOINT_ID => c_NO,
- REGIO_USE_1WIRE_INTERFACE => c_I2C_TC
- )
- port map(
- -- Misc
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
- --Port to GbE
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
- GBE_MAKE_RESET_IN => reset_via_gbe,
- --Slow Control Port
- --common registers 0x00-0x2F
- REGIO_COMMON_STAT_REG_IN => common_stat_reg,
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
- REGIO_COMMON_STAT_STROBE_OUT => open,
- REGIO_COMMON_CTRL_STROBE_OUT => open,
- --internal data port
- BUS_RX => ctrlbus_rx,
- BUS_TX => ctrlbus_tx,
- --Data port - external master (e.g. Flash or Debug)
- BUS_MASTER_IN => bus_master_in,
- BUS_MASTER_OUT => bus_master_out,
- BUS_MASTER_ACTIVE => bus_master_active,
- --Sensors & ID
- ONEWIRE_INOUT => open,
- I2C_SCL => I2C_SCL,
- I2C_SDA => I2C_SDA,
- -- Generic stuff
- TIMERS_OUT => timer,
- MY_ADDRESS_OUT => open
- );
-
- common_stat_reg(159 downto 128) <= oob_reg_3_int;
- common_stat_reg(127 downto 96) <= oob_reg_2_int;
- common_stat_reg(95 downto 64) <= oob_reg_1_int;
- common_stat_reg(63 downto 32) <= oob_reg_0_int;
-
--- common_stat_reg <= (others => '0');
-
--------------------------------------------------------------------------------
--- Bus Handler
--------------------------------------------------------------------------------
- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
- generic map(
- PORT_NUMBER => 1,
- PORT_ADDRESSES => (0 => x"d000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, others => 0),
- PORT_MASK_ENABLE => 1
- )
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- REGIO_RX => ctrlbus_rx,
- REGIO_TX => ctrlbus_tx,
- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_TX(0) => bustools_tx,
- STAT_DEBUG => open
- );
-
--------------------------------------------------------------------------------
--- Control Tools
--------------------------------------------------------------------------------
- THE_TOOLS : entity work.tomcat_tools
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- --Flash & Reload
- FLASH_CS => flash_ncs_i,
- FLASH_CLK => flash_sclk_i,
- FLASH_IN => flash_miso_i,
- FLASH_OUT => flash_mosi_i,
- PROGRAMN => PROGRAMN,
- REBOOT_IN => reboot_int,
- -- I2C
- SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
- SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
- -- Additional register
- ADDITIONAL_REG => additional_reg,
- CTRL_REG => control_reg,
- AUX_REG => aux_reg,
- -- Ethernet registers
- FWD_MAC_OUT => fwd_mac_int,
- FWD_IP_OUT => fwd_ip_int,
- FWD_PORT_OUT => fwd_port_int,
- -- Trigger
- TRIGGER_OUT => open,
- --Slowcontrol
- BUS_RX => bustools_rx,
- BUS_TX => bustools_tx,
- --Control master for default settings
- BUS_MASTER_IN => bus_master_in,
- BUS_MASTER_OUT => bus_master_out,
- BUS_MASTER_ACTIVE => bus_master_active,
- DEBUG_OUT => open
- );
-
- reboot_int <= common_ctrl_reg(15) or reboot_from_gbe;
-
--- led_off <= additional_reg(0);
-
- -- FlashROM external connections
- FLASH_OVERRIDE <= not additional_reg(1);
- FLASH_HOLD <= '1';
- FLASH_WP <= '1';
- FLASH_NCS <= flash_ncs_i;
- FLASH_SCLK <= flash_sclk_i;
- FLASH_MOSI <= flash_mosi_i;
- flash_miso_i <= FLASH_MISO;
-
- -- Jan's proposal
- -- led_off <= additional_reg(0);
- -- FLASH_OVERRIDE <= not additional_reg(1);
-
--------------------------------------------------------------------------------
--- Outputs
--------------------------------------------------------------------------------
--- INTCOM(19 downto 0) <= (others => '0');
- INTCOM <= debug(19 downto 0);
--- INTCOM(19 downto 0) <= (others => 'Z');
-
--- GPIO <= (others => '0');
- GPIO(15 downto 14) <= (others => '0');
- GPIO(13 downto 0) <= debug(33 downto 20);
--- GPIO(8 downto 0) <= debug(28 downto 20);
--- GPIO(12 downto 9) <= debug(71 downto 68);
--- GPIO(13 downto 13) <= debug(33 downto 33);
--- GPIO <= (others => 'Z');
-
- TIMING_TEST <= dlm_found_int; --'0';
-
--------------------------------------------------------------------------------
--- LED
--------------------------------------------------------------------------------
- LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
- LED_SFP_YELLOW <= not status(5); --'0';
- LED_SFP_RED <= not status(6); --'0';
- LED(3) <= not std_logic(blink_counter(5)); --additional_reg(7); --'0';
- LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
- LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
- LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
-
- -- 0 red
- -- 1 orange
- -- 2 green
- -- 3 green
-
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
---
--- debug(7 downto 0) <= ul_rx_data(7 downto 0);
--- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
--- debug(16) <= ul_rx_data(9);
--- debug(17) <= ul_tx_data_q(9);
--- debug(18) <= ul_rx_data(10);
--- debug(19) <= ul_tx_data_q(10);
--- debug(20) <= ul_rx_data(8);
--- debug(21) <= ul_tx_data_q(8);
--- debug(22) <= ul_rx_frame_req;
--- debug(23) <= ul_rx_frame_ack;
--- debug(24) <= ul_rx_frame_avail;
--- debug(25) <= dl_rx_frame_req(0);
--- debug(26) <= dl_rx_frame_ack(0);
--- debug(27) <= dl_rx_frame_avail(0);
--- debug(28) <= port_sel(0);
--- debug(29) <= ul_rx_fifofull;
--- debug(30) <= ul_tx_fifofull;
--- debug(31) <= '0';
--- debug(32) <= tick_int;
--- debug(33) <= clk_sys;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-
-end architecture;
--- /dev/null
+tomcat_gbe_d0ch0_d1ch1.vhd
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define_RS.all;
+
+entity tomcat_gbe is
+ port(
+ -- clock oscillators
+ CLK_200 : in std_logic;
+ CLK_125 : in std_logic;
+ -- SFP signals
+ SFP_TX_DIS : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_RATESEL : out std_logic;
+ SFP_MOD_0 : in std_logic; -- detect
+ SFP_MOD_1 : inout std_logic; -- SCL
+ SFP_MOD_2 : inout std_logic; -- SDA
+ -- Flash, Reload
+ FLASH_SCLK : out std_logic;
+ FLASH_NCS : out std_logic;
+ FLASH_MOSI : out std_logic;
+ FLASH_MISO : in std_logic;
+ FLASH_HOLD : out std_logic;
+ FLASH_WP : out std_logic;
+ FLASH_SELECT : in std_logic;
+ FLASH_OVERRIDE : out std_logic;
+ PROGRAMN : out std_logic;
+ -- I2C (temperature, UID)
+ I2C_SDA : inout std_logic;
+ I2C_SCL : inout std_logic;
+ -- LEDs
+ LED : out std_logic_vector(3 downto 0);
+ LED_SFP_YELLOW : out std_logic;
+ LED_SFP_GREEN : out std_logic;
+ LED_SFP_RED : out std_logic;
+ -- LVDS intercom
+-- INTCOM : inout std_logic_vector(9 downto 0); -- LVDS
+ INTCOM : inout std_logic_vector(19 downto 0); -- LVCMOS
+ -- timing measurements
+ TIMING_TEST : inout std_logic;
+ -- GPIO
+ GPIO : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_NCS : signal is true;
+ attribute syn_useioff of FLASH_SCLK : signal is true;
+ attribute syn_useioff of FLASH_MOSI : signal is true;
+ attribute syn_useioff of FLASH_MISO : signal is true;
+
+end entity;
+
+architecture arch of tomcat_gbe is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal reset_n_i : std_logic;
+ signal clear_i : std_logic;
+ signal clear_n_i : std_logic;
+
+ signal sd_led_green : std_logic;
+ signal sd_led_yellow : std_logic;
+ signal sd_led_red : std_logic;
+
+ signal led_i : std_logic_vector(3 downto 0);
+
+ signal uuid_i : std_logic_vector(63 downto 0);
+
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_read : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+
+ signal reboot_from_gbe : std_logic;
+ signal reset_via_gbe : std_logic;
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ signal debug : std_logic_vector(127 downto 0);
+ signal status : std_logic_vector(15 downto 0);
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal ctrlbus_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
+ signal bus_master_active : std_logic;
+
+ signal timer : TIMERS;
+ signal additional_reg : std_logic_vector(31 downto 0);
+ signal led_off : std_logic;
+
+ signal flash_ncs_i : std_logic;
+ signal flash_sclk_i : std_logic;
+ signal flash_miso_i : std_logic;
+ signal flash_mosi_i : std_logic;
+
+ signal link_active : std_logic;
+
+ -- the new FIFO interface
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal ul_rx_data : std_logic_vector(10 downto 0);
+ signal ul_rx_frame_avail : std_logic;
+ signal ul_rx_frame_req : std_logic;
+ signal ul_rx_frame_ack : std_logic;
+ signal ul_rx_fifofull : std_logic;
+ signal ul_tx_data : std_logic_vector(10 downto 0);
+ signal ul_tx_fifofull : std_logic;
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: fifo_data
+ type dl_rx_data_t is array(0 to 1) of std_logic_vector(10 downto 0);
+ signal dl_rx_data : dl_rx_data_t;
+ signal dl_rx_data_q : dl_rx_data_t;
+ signal dl_rx_frame_req : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_ack : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_avail : std_logic_vector(1 downto 0);
+ signal dl_rx_fifofull : std_logic_vector(1 downto 0);
+ signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
+ signal dl_tx_fifofull : std_logic_vector(1 downto 0);
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal local_rx_data : std_logic_vector(10 downto 0); -- CPU (RX) to 1:2 MUXes
+ signal local_rx_frame_avail : std_logic;
+ signal local_rx_frame_req : std_logic;
+ signal local_rx_frame_ack : std_logic;
+ signal local_rx_fifofull : std_logic;
+ signal local_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to CPU (TX)
+ signal local_tx_fifofull : std_logic;
+ -- these signals go from multiplexer to UL (TX)
+
+ signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
+
+ signal dl_rx_port_mux : std_logic_vector(3 downto 0);
+ signal ul_tx_port_sel : std_logic;
+ signal dl_tx_port_sel : std_logic;
+ signal local_tx_port_sel : std_logic;
+
+ signal sniffer_data : std_logic_vector(7 downto 0);
+ signal sniffer_wr : std_logic;
+ signal sniffer_eof : std_logic;
+ signal sniffer_error : std_logic;
+
+ signal fwd_mac_int : std_logic_vector(47 downto 0);
+ signal fwd_ip_int : std_logic_vector(31 downto 0);
+ signal fwd_port_int : std_logic_vector(15 downto 0);
+ signal fwd_data_int : std_logic_vector(7 downto 0);
+ signal fwd_ready_int : std_logic;
+ signal fwd_full_int : std_logic;
+ signal fwd_data_valid_int : std_logic;
+ signal fwd_sop_int : std_logic;
+ signal fwd_eop_int : std_logic;
+ signal fwd_busy_int : std_logic;
+
+ signal control_reg : std_logic_vector(31 downto 0);
+ signal aux_reg : std_logic_vector(31 downto 0);
+
+ signal tick_ms_int : std_logic;
+ signal tick_us_int : std_logic;
+
+ signal reboot_int : std_logic;
+
+ signal sgl_debug : std_logic_vector(15 downto 0);
+
+ signal blink_counter : unsigned(9 downto 0);
+
+ signal oob_reg_0_int : std_logic_vector(31 downto 0);
+ signal oob_reg_1_int : std_logic_vector(31 downto 0);
+ signal oob_reg_2_int : std_logic_vector(31 downto 0);
+ signal oob_reg_3_int : std_logic_vector(31 downto 0);
+
+ signal dlm_found_int : std_logic;
+ signal dlm_inject_int : std_logic;
+ signal dlm_tx_data_int : std_logic_vector(7 downto 0);
+ signal dlm_rx_data_int : std_logic_vector(7 downto 0);
+
+ signal dlm_ctr : unsigned(23 downto 0);
+ signal rst_dlm_ctr_x : std_logic;
+ signal rst_dlm_ctr : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Important pins
+---------------------------------------------------------------------------
+-- PROGRAMN <= '1';
+-- FLASH_OVERRIDE <= '1';
+-- FLASH_SCLK <= 'Z';
+-- FLASH_NCS <= '1';
+-- FLASH_MOSI <= '0';
+-- FLASH_HOLD <= '1';
+-- FLASH_WP <= '1';
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET_HANDLER: entity clock_reset_handler
+ port map(
+ CLK_IN => CLK_125,
+ GLOBAL_RESET_IN => '0', -- for sync operation
+ RESET_FROM_NET_IN => '0', -- unused
+ --
+ CLK_OUT => clk_sys,
+ RESET_OUT => reset_i,
+ RESET_N_OUT => reset_n_i,
+ CLEAR_OUT => clear_i,
+ CLEAR_N_OUT => clear_n_i,
+ --
+ TICK_MS_OUT => tick_ms_int,
+ TICK_US_OUT => tick_us_int,
+ --
+ LED_RED_OUT => open,
+ LED_GREEN_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+THE_BLINK_COUNTER_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ if( tick_ms_int = '1' ) then
+ blink_counter <= blink_counter + 1;
+ end if;
+ end if;
+end process THE_BLINK_COUNTER_PROC;
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- DLM timing generator
+THE_DLM_SEND_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ rst_dlm_ctr <= rst_dlm_ctr_x;
+ if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
+ dlm_ctr <= (others => '0');
+ elsif( aux_reg(31) = '1' ) then
+ dlm_ctr <= dlm_ctr + 1;
+ end if;
+ end if;
+end process THE_DLM_SEND_PROC;
+
+rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+
+---------------------------------------------------------------------------
+-- GbE interface (SFP)
+---------------------------------------------------------------------------
+ GBE_SFP_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 0
+ )
+ port map(
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- FIFO interface RX
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
+ FIFO_WR_OUT => ul_rx_data(9),
+ FIFO_DATA_OUT => ul_rx_data(8 downto 0),
+ FRAME_START_OUT => ul_rx_data(10),
+ FRAME_REQ_IN => ul_rx_frame_req,
+ FRAME_ACK_OUT => ul_rx_frame_ack,
+ FRAME_AVAIL_OUT => ul_rx_frame_avail,
+ -- FIFO interface TX
+ FIFO_WR_IN => ul_tx_data(9),
+ FIFO_DATA_IN => ul_tx_data(8 downto 0),
+ FRAME_START_IN => ul_tx_data(10),
+ FIFO_FULL_OUT => ul_tx_fifofull,
+ --SFP Connection
+ SD_PRSNT_N_IN => SFP_MOD_0,
+ SD_LOS_IN => SFP_LOS,
+ SD_TXDIS_OUT => SFP_TX_DIS,
+ -- internal sniffer port
+ MAC_RX_DATA_OUT => sniffer_data,
+ MAC_RX_WRITE_OUT => sniffer_wr,
+ MAC_RX_EOF_OUT => sniffer_eof,
+ MAC_RX_ERROR_OUT => sniffer_error,
+ -- Status
+ PCS_AN_READY_OUT => open,
+ LINK_ACTIVE_OUT => link_active, -- only needed on UL port for SCTRL
+ TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => '0',
+ DLM_DATA_IN => x"00",
+ DLM_FOUND_OUT => open,
+ DLM_DATA_OUT => open,
+ -- Debug
+ STATUS_OUT => status(7 downto 0),
+ DEBUG_OUT => open
+ );
+
+ debug(127 downto 64) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- GbE interface (copper)
+---------------------------------------------------------------------------
+ GBE_COPPER_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 3
+ )
+ port map(
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- FIFO interface RX
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
+ FIFO_WR_OUT => dl_rx_data(1)(9),
+ FIFO_DATA_OUT => dl_rx_data(1)(8 downto 0),
+ FRAME_START_OUT => dl_rx_data(1)(10),
+ FRAME_REQ_IN => dl_rx_frame_req(1),
+ FRAME_ACK_OUT => dl_rx_frame_ack(1),
+ FRAME_AVAIL_OUT => dl_rx_frame_avail(1),
+ -- FIFO interface TX
+ FIFO_WR_IN => dl_tx_data(9),
+ FIFO_DATA_IN => dl_tx_data(8 downto 0),
+ FRAME_START_IN => dl_tx_data(10),
+ FIFO_FULL_OUT => dl_tx_fifofull(1),
+ --SFP Connection
+ SD_PRSNT_N_IN => '0',
+ SD_LOS_IN => '0',
+ SD_TXDIS_OUT => open,
+ -- internal sniffer port
+ -- Status
+ PCS_AN_READY_OUT => open,
+ LINK_ACTIVE_OUT => open,
+ TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => dlm_inject_int,
+ DLM_DATA_IN => dlm_tx_data_int,
+ DLM_FOUND_OUT => dlm_found_int,
+ DLM_DATA_OUT => dlm_rx_data_int,
+ -- Debug
+ STATUS_OUT => open,
+ DEBUG_OUT => debug(63 downto 0) --open
+ );
+
+ dlm_inject_int <= rst_dlm_ctr;
+ dlm_tx_data_int <= control_reg(7 downto 0);
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+ THE_SGL_CTRL: entity sgl_ctrl
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ -- UL port
+ UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full
+ UL_FRAME_AVAIL_IN => ul_rx_frame_avail, -- UL RX has frames for DL/LOCAL
+ UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
+ UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
+ -- DL ports (includes SCTRL)
+ DL_FIFOFULL_IN(1 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
+ DL_FRAME_AVAIL_IN(1 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
+ DL_FRAME_REQ_OUT(1 downto 0) => dl_rx_frame_req, -- DL RXn request to send
+ DL_FRAME_ACK_IN(1 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
+ -- CPU port -- not needed
+ -- MUX control
+ DL_RX_PORT_SEL_OUT(1 downto 0) => open,
+ DL_RX_PORT_MUX_OUT => dl_rx_port_mux,
+ DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
+ LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
+ UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
+ --
+ DEBUG => sgl_debug --open
+ );
+
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(31 downto 28) <= sgl_debug(3 downto 0);
+-- debug(32) <= dl_rx_port_mux(1);
+-- debug(33) <= clk_sys;
+
+---------------------------------------------------------------------------
+-- Multiplexers for data streams
+---------------------------------------------------------------------------
+ THE_PIPELINING: for I in 0 to 1 generate
+ dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys);
+ end generate THE_PIPELINING;
+
+ local_rx_data <= (others => '0'); -- no local CPU port
+
+ THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q )
+ begin
+ case dl_rx_port_mux is
+ when x"0" => switch_rx_data <= dl_rx_data_q(0);
+ when x"1" => switch_rx_data <= dl_rx_data_q(1);
+ when others => switch_rx_data <= (others => '0');
+ end case;
+ end process THE_DL_RX_MUX;
+
+ ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data; -- not needed
+
+ local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data; -- not needed
+
+ dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; -- not needed
+
+---------------------------------------------------------------------------
+-- GbE wrapper without med interface
+---------------------------------------------------------------------------
+ GBE: entity work.gbe_wrapper_fifo
+ generic map(
+ LINK_HAS_SLOWCTRL => '1',
+ LINK_HAS_DHCP => '1',
+ LINK_HAS_ARP => '1',
+ LINK_HAS_PING => '1',
+ LINK_HAS_FWD => '1'
+ )
+ port map(
+ CLK_125_IN => clk_sys,
+ RESET => reset_i,
+ GSR_N => reset_n_i,
+ -- we connect to FIFO interface directly
+ -- FIFO interface TX (send frames)
+ FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
+ FIFO_FULL_IN => ul_tx_fifofull,
+ FIFO_WR_OUT => dl_rx_data(0)(9),
+ FRAME_REQ_IN => dl_rx_frame_req(0),
+ FRAME_ACK_OUT => dl_rx_frame_ack(0),
+ FRAME_AVAIL_OUT => dl_rx_frame_avail(0),
+ FRAME_START_OUT => dl_rx_data(0)(10),
+ -- FIFO interface RX (receive frames)
+ MAC_RX_DATA_IN => sniffer_data,
+ MAC_RX_WRITE_IN => sniffer_wr,
+ MAC_RX_EOF_IN => sniffer_eof,
+ MAC_RX_ERROR_IN => sniffer_error,
+ --
+ PCS_AN_READY_IN => link_active,
+ LINK_ACTIVE_IN => link_active,
+ -- unique adresses
+ MC_UNIQUE_ID_IN => timer.uid,
+ MY_TRBNET_ADDRESS_IN => timer.network_address,
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+ -- slow control by GbE
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+ -- Forwarder
+ FWD_DST_MAC_IN => fwd_mac_int,
+ FWD_DST_IP_IN => fwd_ip_int,
+ FWD_DST_UDP_IN => fwd_port_int,
+ FWD_DATA_IN => fwd_data_int,
+ FWD_DATA_VALID_IN => fwd_data_valid_int,
+ FWD_SOP_IN => fwd_sop_int,
+ FWD_EOP_IN => fwd_eop_int,
+ FWD_READY_OUT => fwd_ready_int,
+ FWD_FULL_OUT => fwd_full_int,
+ --
+ OOB_REGISTER_0_OUT => oob_reg_0_int,
+ OOB_REGISTER_1_OUT => oob_reg_1_int,
+ OOB_REGISTER_2_OUT => oob_reg_2_int,
+ OOB_REGISTER_3_OUT => oob_reg_3_int,
+ -- reset
+ MAKE_RESET_OUT => reset_via_gbe,
+ -- debug
+ STATUS_OUT => status(15 downto 8),
+ DEBUG_OUT => open
+ );
+
+ THE_FWD_TEST: entity fwd_test_random
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ FWD_ENABLE_IN => additional_reg(31),
+ FWD_DELAY_IN => control_reg(31 downto 16),
+-- FWD_SIZE_IN => control_reg(15 downto 0),
+ FWD_START_IN => tick_us_int,
+ FWD_BUSY_OUT => fwd_busy_int, --open
+ --
+ FWD_READY_IN => fwd_ready_int,
+ FWD_FULL_IN => fwd_full_int,
+ FWD_DATA_OUT => fwd_data_int,
+ FWD_DATA_VALID_OUT => fwd_data_valid_int,
+ FWD_SOP_OUT => fwd_sop_int,
+ FWD_EOP_OUT => fwd_eop_int,
+ --
+ DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SCTRL endpoint for GbE standalone
+---------------------------------------------------------------------------
+ THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
+ generic map(
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ APL_WRITE_ALL_WORDS => c_NO,
+ INIT_ADDRESS => INIT_ADDRESS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
+ REGIO_USE_1WIRE_INTERFACE => c_I2C_TC
+ )
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+ --Port to GbE
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+ GBE_MAKE_RESET_IN => reset_via_gbe,
+ --Slow Control Port
+ --common registers 0x00-0x2F
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_COMMON_STAT_STROBE_OUT => open,
+ REGIO_COMMON_CTRL_STROBE_OUT => open,
+ --internal data port
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ --Data port - external master (e.g. Flash or Debug)
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ --Sensors & ID
+ ONEWIRE_INOUT => open,
+ I2C_SCL => I2C_SCL,
+ I2C_SDA => I2C_SDA,
+ -- Generic stuff
+ TIMERS_OUT => timer,
+ MY_ADDRESS_OUT => open
+ );
+
+ common_stat_reg(159 downto 128) <= oob_reg_3_int;
+ common_stat_reg(127 downto 96) <= oob_reg_2_int;
+ common_stat_reg(95 downto 64) <= oob_reg_1_int;
+ common_stat_reg(63 downto 32) <= oob_reg_0_int;
+
+-- common_stat_reg <= (others => '0');
+
+-------------------------------------------------------------------------------
+-- Bus Handler
+-------------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 1,
+ PORT_ADDRESSES => (0 => x"d000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_TX(0) => bustools_tx,
+ STAT_DEBUG => open
+ );
+
+-------------------------------------------------------------------------------
+-- Control Tools
+-------------------------------------------------------------------------------
+ THE_TOOLS : entity work.tomcat_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --Flash & Reload
+ FLASH_CS => flash_ncs_i,
+ FLASH_CLK => flash_sclk_i,
+ FLASH_IN => flash_miso_i,
+ FLASH_OUT => flash_mosi_i,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => reboot_int,
+ -- I2C
+ SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
+ SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
+ -- Additional register
+ ADDITIONAL_REG => additional_reg,
+ CTRL_REG => control_reg,
+ AUX_REG => aux_reg,
+ -- Ethernet registers
+ FWD_MAC_OUT => fwd_mac_int,
+ FWD_IP_OUT => fwd_ip_int,
+ FWD_PORT_OUT => fwd_port_int,
+ -- Trigger
+ TRIGGER_OUT => open,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+ reboot_int <= common_ctrl_reg(15) or reboot_from_gbe;
+
+-- led_off <= additional_reg(0);
+
+ -- FlashROM external connections
+ FLASH_OVERRIDE <= not additional_reg(1);
+ FLASH_HOLD <= '1';
+ FLASH_WP <= '1';
+ FLASH_NCS <= flash_ncs_i;
+ FLASH_SCLK <= flash_sclk_i;
+ FLASH_MOSI <= flash_mosi_i;
+ flash_miso_i <= FLASH_MISO;
+
+ -- Jan's proposal
+ -- led_off <= additional_reg(0);
+ -- FLASH_OVERRIDE <= not additional_reg(1);
+
+-------------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------------
+-- INTCOM(19 downto 0) <= (others => '0');
+ INTCOM <= debug(19 downto 0);
+-- INTCOM(19 downto 0) <= (others => 'Z');
+
+-- GPIO <= (others => '0');
+ GPIO(15 downto 14) <= (others => '0');
+ GPIO(13 downto 0) <= debug(33 downto 20);
+-- GPIO(8 downto 0) <= debug(28 downto 20);
+-- GPIO(12 downto 9) <= debug(71 downto 68);
+-- GPIO(13 downto 13) <= debug(33 downto 33);
+-- GPIO <= (others => 'Z');
+
+ TIMING_TEST <= dlm_found_int; --'0';
+
+-------------------------------------------------------------------------------
+-- LED
+-------------------------------------------------------------------------------
+ LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
+ LED_SFP_YELLOW <= not status(5); --'0';
+ LED_SFP_RED <= not status(6); --'0';
+ LED(3) <= not std_logic(blink_counter(6)); --additional_reg(7); --'0';
+ LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
+ LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
+ LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
+
+ -- 0 red
+ -- 1 orange
+ -- 2 green
+ -- 3 green
+
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+--
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data_q(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data_q(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data_q(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(28) <= port_sel(0);
+-- debug(29) <= ul_rx_fifofull;
+-- debug(30) <= ul_tx_fifofull;
+-- debug(31) <= '0';
+-- debug(32) <= tick_int;
+-- debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
+end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define_RS.all;
+
+entity tomcat_gbe is
+ port(
+ -- clock oscillators
+ CLK_200 : in std_logic;
+ CLK_125 : in std_logic;
+ -- SFP signals
+ SFP_TX_DIS : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_RATESEL : out std_logic;
+ SFP_MOD_0 : in std_logic; -- detect
+ SFP_MOD_1 : inout std_logic; -- SCL
+ SFP_MOD_2 : inout std_logic; -- SDA
+ -- Flash, Reload
+ FLASH_SCLK : out std_logic;
+ FLASH_NCS : out std_logic;
+ FLASH_MOSI : out std_logic;
+ FLASH_MISO : in std_logic;
+ FLASH_HOLD : out std_logic;
+ FLASH_WP : out std_logic;
+ FLASH_SELECT : in std_logic;
+ FLASH_OVERRIDE : out std_logic;
+ PROGRAMN : out std_logic;
+ -- I2C (temperature, UID)
+ I2C_SDA : inout std_logic;
+ I2C_SCL : inout std_logic;
+ -- LEDs
+ LED : out std_logic_vector(3 downto 0);
+ LED_SFP_YELLOW : out std_logic;
+ LED_SFP_GREEN : out std_logic;
+ LED_SFP_RED : out std_logic;
+ -- LVDS intercom
+-- INTCOM : inout std_logic_vector(9 downto 0); -- LVDS
+ INTCOM : inout std_logic_vector(19 downto 0); -- LVCMOS
+ -- timing measurements
+ TIMING_TEST : inout std_logic;
+ -- GPIO
+ GPIO : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_NCS : signal is true;
+ attribute syn_useioff of FLASH_SCLK : signal is true;
+ attribute syn_useioff of FLASH_MOSI : signal is true;
+ attribute syn_useioff of FLASH_MISO : signal is true;
+
+end entity;
+
+architecture arch of tomcat_gbe is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal reset_n_i : std_logic;
+ signal clear_i : std_logic;
+ signal clear_n_i : std_logic;
+
+ signal sd_led_green : std_logic;
+ signal sd_led_yellow : std_logic;
+ signal sd_led_red : std_logic;
+
+ signal led_i : std_logic_vector(3 downto 0);
+
+ signal uuid_i : std_logic_vector(63 downto 0);
+
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_read : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+
+ signal reboot_from_gbe : std_logic;
+ signal reset_via_gbe : std_logic;
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ signal debug : std_logic_vector(127 downto 0);
+ signal status : std_logic_vector(15 downto 0);
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal ctrlbus_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
+ signal bus_master_active : std_logic;
+
+ signal timer : TIMERS;
+ signal additional_reg : std_logic_vector(31 downto 0);
+ signal led_off : std_logic;
+
+ signal flash_ncs_i : std_logic;
+ signal flash_sclk_i : std_logic;
+ signal flash_miso_i : std_logic;
+ signal flash_mosi_i : std_logic;
+
+ signal link_active : std_logic;
+
+ -- the new FIFO interface
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal ul_rx_data : std_logic_vector(10 downto 0);
+ signal ul_rx_frame_avail : std_logic;
+ signal ul_rx_frame_req : std_logic;
+ signal ul_rx_frame_ack : std_logic;
+ signal ul_rx_fifofull : std_logic;
+ signal ul_tx_data : std_logic_vector(10 downto 0);
+ signal ul_tx_fifofull : std_logic;
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: fifo_data
+ type dl_rx_data_t is array(0 to 1) of std_logic_vector(10 downto 0);
+ signal dl_rx_data : dl_rx_data_t;
+ signal dl_rx_data_q : dl_rx_data_t;
+ signal dl_rx_frame_req : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_ack : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_avail : std_logic_vector(1 downto 0);
+ signal dl_rx_fifofull : std_logic_vector(1 downto 0);
+ signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
+ signal dl_tx_fifofull : std_logic_vector(1 downto 0);
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal local_rx_data : std_logic_vector(10 downto 0); -- CPU (RX) to 1:2 MUXes
+ signal local_rx_frame_avail : std_logic;
+ signal local_rx_frame_req : std_logic;
+ signal local_rx_frame_ack : std_logic;
+ signal local_rx_fifofull : std_logic;
+ signal local_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to CPU (TX)
+ signal local_tx_fifofull : std_logic;
+ -- these signals go from multiplexer to UL (TX)
+
+ signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
+
+ signal dl_rx_port_mux : std_logic_vector(3 downto 0);
+ signal ul_tx_port_sel : std_logic;
+ signal dl_tx_port_sel : std_logic;
+ signal local_tx_port_sel : std_logic;
+
+ signal sniffer_data : std_logic_vector(7 downto 0);
+ signal sniffer_wr : std_logic;
+ signal sniffer_eof : std_logic;
+ signal sniffer_error : std_logic;
+
+ signal fwd_mac_int : std_logic_vector(47 downto 0);
+ signal fwd_ip_int : std_logic_vector(31 downto 0);
+ signal fwd_port_int : std_logic_vector(15 downto 0);
+ signal fwd_data_int : std_logic_vector(7 downto 0);
+ signal fwd_ready_int : std_logic;
+ signal fwd_full_int : std_logic;
+ signal fwd_data_valid_int : std_logic;
+ signal fwd_sop_int : std_logic;
+ signal fwd_eop_int : std_logic;
+ signal fwd_busy_int : std_logic;
+
+ signal control_reg : std_logic_vector(31 downto 0);
+ signal aux_reg : std_logic_vector(31 downto 0);
+
+ signal tick_ms_int : std_logic;
+ signal tick_us_int : std_logic;
+
+ signal reboot_int : std_logic;
+
+ signal sgl_debug : std_logic_vector(15 downto 0);
+
+ signal blink_counter : unsigned(9 downto 0);
+
+ signal oob_reg_0_int : std_logic_vector(31 downto 0);
+ signal oob_reg_1_int : std_logic_vector(31 downto 0);
+ signal oob_reg_2_int : std_logic_vector(31 downto 0);
+ signal oob_reg_3_int : std_logic_vector(31 downto 0);
+
+ signal dlm_found_int : std_logic;
+ signal dlm_inject_int : std_logic;
+ signal dlm_tx_data_int : std_logic_vector(7 downto 0);
+ signal dlm_rx_data_int : std_logic_vector(7 downto 0);
+
+ signal dlm_ctr : unsigned(23 downto 0);
+ signal rst_dlm_ctr_x : std_logic;
+ signal rst_dlm_ctr : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Important pins
+---------------------------------------------------------------------------
+-- PROGRAMN <= '1';
+-- FLASH_OVERRIDE <= '1';
+-- FLASH_SCLK <= 'Z';
+-- FLASH_NCS <= '1';
+-- FLASH_MOSI <= '0';
+-- FLASH_HOLD <= '1';
+-- FLASH_WP <= '1';
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET_HANDLER: entity clock_reset_handler
+ port map(
+ CLK_IN => CLK_125,
+ GLOBAL_RESET_IN => '0', -- for sync operation
+ RESET_FROM_NET_IN => '0', -- unused
+ --
+ CLK_OUT => clk_sys,
+ RESET_OUT => reset_i,
+ RESET_N_OUT => reset_n_i,
+ CLEAR_OUT => clear_i,
+ CLEAR_N_OUT => clear_n_i,
+ --
+ TICK_MS_OUT => tick_ms_int,
+ TICK_US_OUT => tick_us_int,
+ --
+ LED_RED_OUT => open,
+ LED_GREEN_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+THE_BLINK_COUNTER_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ if( tick_ms_int = '1' ) then
+ blink_counter <= blink_counter + 1;
+ end if;
+ end if;
+end process THE_BLINK_COUNTER_PROC;
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- DLM timing generator
+THE_DLM_SEND_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ rst_dlm_ctr <= rst_dlm_ctr_x;
+ if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
+ dlm_ctr <= (others => '0');
+ elsif( aux_reg(31) = '1' ) then
+ dlm_ctr <= dlm_ctr + 1;
+ end if;
+ end if;
+end process THE_DLM_SEND_PROC;
+
+rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+
+---------------------------------------------------------------------------
+-- GbE interface (SFP)
+---------------------------------------------------------------------------
+ GBE_SFP_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 3
+ )
+ port map(
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- FIFO interface RX
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
+ FIFO_WR_OUT => ul_rx_data(9),
+ FIFO_DATA_OUT => ul_rx_data(8 downto 0),
+ FRAME_START_OUT => ul_rx_data(10),
+ FRAME_REQ_IN => ul_rx_frame_req,
+ FRAME_ACK_OUT => ul_rx_frame_ack,
+ FRAME_AVAIL_OUT => ul_rx_frame_avail,
+ -- FIFO interface TX
+ FIFO_WR_IN => ul_tx_data(9),
+ FIFO_DATA_IN => ul_tx_data(8 downto 0),
+ FRAME_START_IN => ul_tx_data(10),
+ FIFO_FULL_OUT => ul_tx_fifofull,
+ --SFP Connection
+ SD_PRSNT_N_IN => SFP_MOD_0,
+ SD_LOS_IN => SFP_LOS,
+ SD_TXDIS_OUT => SFP_TX_DIS,
+ -- internal sniffer port
+ MAC_RX_DATA_OUT => sniffer_data,
+ MAC_RX_WRITE_OUT => sniffer_wr,
+ MAC_RX_EOF_OUT => sniffer_eof,
+ MAC_RX_ERROR_OUT => sniffer_error,
+ -- Status
+ PCS_AN_READY_OUT => open,
+ LINK_ACTIVE_OUT => link_active, -- only needed on UL port for SCTRL
+ TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => dlm_inject_int,
+ DLM_DATA_IN => dlm_tx_data_int,
+ DLM_FOUND_OUT => dlm_found_int,
+ DLM_DATA_OUT => dlm_rx_data_int,
+ -- Debug
+ STATUS_OUT => status(7 downto 0),
+ DEBUG_OUT => debug(63 downto 0) --open
+ );
+
+ dlm_inject_int <= rst_dlm_ctr;
+ dlm_tx_data_int <= control_reg(7 downto 0);
+
+ debug(127 downto 64) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- GbE interface (copper)
+---------------------------------------------------------------------------
+ GBE_COPPER_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 0
+ )
+ port map(
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- FIFO interface RX
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
+ FIFO_WR_OUT => dl_rx_data(1)(9),
+ FIFO_DATA_OUT => dl_rx_data(1)(8 downto 0),
+ FRAME_START_OUT => dl_rx_data(1)(10),
+ FRAME_REQ_IN => dl_rx_frame_req(1),
+ FRAME_ACK_OUT => dl_rx_frame_ack(1),
+ FRAME_AVAIL_OUT => dl_rx_frame_avail(1),
+ -- FIFO interface TX
+ FIFO_WR_IN => dl_tx_data(9),
+ FIFO_DATA_IN => dl_tx_data(8 downto 0),
+ FRAME_START_IN => dl_tx_data(10),
+ FIFO_FULL_OUT => dl_tx_fifofull(1),
+ --SFP Connection
+ SD_PRSNT_N_IN => '0',
+ SD_LOS_IN => '0',
+ SD_TXDIS_OUT => open,
+ -- internal sniffer port
+ -- Status
+ PCS_AN_READY_OUT => open,
+ LINK_ACTIVE_OUT => open,
+ TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => '0',
+ DLM_DATA_IN => x"00",
+ DLM_FOUND_OUT => open,
+ DLM_DATA_OUT => open,
+ -- Debug
+ STATUS_OUT => open,
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+ THE_SGL_CTRL: entity sgl_ctrl
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ -- UL port
+ UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full
+ UL_FRAME_AVAIL_IN => ul_rx_frame_avail, -- UL RX has frames for DL/LOCAL
+ UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
+ UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
+ -- DL ports (includes SCTRL)
+ DL_FIFOFULL_IN(1 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
+ DL_FRAME_AVAIL_IN(1 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
+ DL_FRAME_REQ_OUT(1 downto 0) => dl_rx_frame_req, -- DL RXn request to send
+ DL_FRAME_ACK_IN(1 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
+ -- CPU port -- not needed
+ -- MUX control
+ DL_RX_PORT_SEL_OUT(1 downto 0) => open,
+ DL_RX_PORT_MUX_OUT => dl_rx_port_mux,
+ DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
+ LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
+ UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
+ --
+ DEBUG => sgl_debug --open
+ );
+
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(31 downto 28) <= sgl_debug(3 downto 0);
+-- debug(32) <= dl_rx_port_mux(1);
+-- debug(33) <= clk_sys;
+
+---------------------------------------------------------------------------
+-- Multiplexers for data streams
+---------------------------------------------------------------------------
+ THE_PIPELINING: for I in 0 to 1 generate
+ dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys);
+ end generate THE_PIPELINING;
+
+ local_rx_data <= (others => '0'); -- no local CPU port
+
+ THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q )
+ begin
+ case dl_rx_port_mux is
+ when x"0" => switch_rx_data <= dl_rx_data_q(0);
+ when x"1" => switch_rx_data <= dl_rx_data_q(1);
+ when others => switch_rx_data <= (others => '0');
+ end case;
+ end process THE_DL_RX_MUX;
+
+ ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data; -- not needed
+
+ local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data; -- not needed
+
+ dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; -- not needed
+
+---------------------------------------------------------------------------
+-- GbE wrapper without med interface
+---------------------------------------------------------------------------
+ GBE: entity work.gbe_wrapper_fifo
+ generic map(
+ LINK_HAS_SLOWCTRL => '1',
+ LINK_HAS_DHCP => '1',
+ LINK_HAS_ARP => '1',
+ LINK_HAS_PING => '1',
+ LINK_HAS_FWD => '1'
+ )
+ port map(
+ CLK_125_IN => clk_sys,
+ RESET => reset_i,
+ GSR_N => reset_n_i,
+ -- we connect to FIFO interface directly
+ -- FIFO interface TX (send frames)
+ FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
+ FIFO_FULL_IN => ul_tx_fifofull,
+ FIFO_WR_OUT => dl_rx_data(0)(9),
+ FRAME_REQ_IN => dl_rx_frame_req(0),
+ FRAME_ACK_OUT => dl_rx_frame_ack(0),
+ FRAME_AVAIL_OUT => dl_rx_frame_avail(0),
+ FRAME_START_OUT => dl_rx_data(0)(10),
+ -- FIFO interface RX (receive frames)
+ MAC_RX_DATA_IN => sniffer_data,
+ MAC_RX_WRITE_IN => sniffer_wr,
+ MAC_RX_EOF_IN => sniffer_eof,
+ MAC_RX_ERROR_IN => sniffer_error,
+ --
+ PCS_AN_READY_IN => link_active,
+ LINK_ACTIVE_IN => link_active,
+ -- unique adresses
+ MC_UNIQUE_ID_IN => timer.uid,
+ MY_TRBNET_ADDRESS_IN => timer.network_address,
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+ -- slow control by GbE
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+ -- Forwarder
+ FWD_DST_MAC_IN => fwd_mac_int,
+ FWD_DST_IP_IN => fwd_ip_int,
+ FWD_DST_UDP_IN => fwd_port_int,
+ FWD_DATA_IN => fwd_data_int,
+ FWD_DATA_VALID_IN => fwd_data_valid_int,
+ FWD_SOP_IN => fwd_sop_int,
+ FWD_EOP_IN => fwd_eop_int,
+ FWD_READY_OUT => fwd_ready_int,
+ FWD_FULL_OUT => fwd_full_int,
+ --
+ OOB_REGISTER_0_OUT => oob_reg_0_int,
+ OOB_REGISTER_1_OUT => oob_reg_1_int,
+ OOB_REGISTER_2_OUT => oob_reg_2_int,
+ OOB_REGISTER_3_OUT => oob_reg_3_int,
+ -- reset
+ MAKE_RESET_OUT => reset_via_gbe,
+ -- debug
+ STATUS_OUT => status(15 downto 8),
+ DEBUG_OUT => open
+ );
+
+ THE_FWD_TEST: entity fwd_test_random
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ FWD_ENABLE_IN => additional_reg(31),
+ FWD_DELAY_IN => control_reg(31 downto 16),
+-- FWD_SIZE_IN => control_reg(15 downto 0),
+ FWD_START_IN => tick_us_int,
+ FWD_BUSY_OUT => fwd_busy_int, --open
+ --
+ FWD_READY_IN => fwd_ready_int,
+ FWD_FULL_IN => fwd_full_int,
+ FWD_DATA_OUT => fwd_data_int,
+ FWD_DATA_VALID_OUT => fwd_data_valid_int,
+ FWD_SOP_OUT => fwd_sop_int,
+ FWD_EOP_OUT => fwd_eop_int,
+ --
+ DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SCTRL endpoint for GbE standalone
+---------------------------------------------------------------------------
+ THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
+ generic map(
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ APL_WRITE_ALL_WORDS => c_NO,
+ INIT_ADDRESS => INIT_ADDRESS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
+ REGIO_USE_1WIRE_INTERFACE => c_I2C_TC
+ )
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+ --Port to GbE
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+ GBE_MAKE_RESET_IN => reset_via_gbe,
+ --Slow Control Port
+ --common registers 0x00-0x2F
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_COMMON_STAT_STROBE_OUT => open,
+ REGIO_COMMON_CTRL_STROBE_OUT => open,
+ --internal data port
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ --Data port - external master (e.g. Flash or Debug)
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ --Sensors & ID
+ ONEWIRE_INOUT => open,
+ I2C_SCL => I2C_SCL,
+ I2C_SDA => I2C_SDA,
+ -- Generic stuff
+ TIMERS_OUT => timer,
+ MY_ADDRESS_OUT => open
+ );
+
+ common_stat_reg(159 downto 128) <= oob_reg_3_int;
+ common_stat_reg(127 downto 96) <= oob_reg_2_int;
+ common_stat_reg(95 downto 64) <= oob_reg_1_int;
+ common_stat_reg(63 downto 32) <= oob_reg_0_int;
+
+-- common_stat_reg <= (others => '0');
+
+-------------------------------------------------------------------------------
+-- Bus Handler
+-------------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 1,
+ PORT_ADDRESSES => (0 => x"d000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_TX(0) => bustools_tx,
+ STAT_DEBUG => open
+ );
+
+-------------------------------------------------------------------------------
+-- Control Tools
+-------------------------------------------------------------------------------
+ THE_TOOLS : entity work.tomcat_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --Flash & Reload
+ FLASH_CS => flash_ncs_i,
+ FLASH_CLK => flash_sclk_i,
+ FLASH_IN => flash_miso_i,
+ FLASH_OUT => flash_mosi_i,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => reboot_int,
+ -- I2C
+ SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
+ SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
+ -- Additional register
+ ADDITIONAL_REG => additional_reg,
+ CTRL_REG => control_reg,
+ AUX_REG => aux_reg,
+ -- Ethernet registers
+ FWD_MAC_OUT => fwd_mac_int,
+ FWD_IP_OUT => fwd_ip_int,
+ FWD_PORT_OUT => fwd_port_int,
+ -- Trigger
+ TRIGGER_OUT => open,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+ reboot_int <= common_ctrl_reg(15) or reboot_from_gbe;
+
+-- led_off <= additional_reg(0);
+
+ -- FlashROM external connections
+ FLASH_OVERRIDE <= not additional_reg(1);
+ FLASH_HOLD <= '1';
+ FLASH_WP <= '1';
+ FLASH_NCS <= flash_ncs_i;
+ FLASH_SCLK <= flash_sclk_i;
+ FLASH_MOSI <= flash_mosi_i;
+ flash_miso_i <= FLASH_MISO;
+
+ -- Jan's proposal
+ -- led_off <= additional_reg(0);
+ -- FLASH_OVERRIDE <= not additional_reg(1);
+
+-------------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------------
+-- INTCOM(19 downto 0) <= (others => '0');
+ INTCOM <= debug(19 downto 0);
+-- INTCOM(19 downto 0) <= (others => 'Z');
+
+-- GPIO <= (others => '0');
+ GPIO(15 downto 14) <= (others => '0');
+ GPIO(13 downto 0) <= debug(33 downto 20);
+-- GPIO(8 downto 0) <= debug(28 downto 20);
+-- GPIO(12 downto 9) <= debug(71 downto 68);
+-- GPIO(13 downto 13) <= debug(33 downto 33);
+-- GPIO <= (others => 'Z');
+
+ TIMING_TEST <= dlm_found_int; --'0';
+
+-------------------------------------------------------------------------------
+-- LED
+-------------------------------------------------------------------------------
+ LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
+ LED_SFP_YELLOW <= not status(5); --'0';
+ LED_SFP_RED <= not status(6); --'0';
+ LED(3) <= not std_logic(blink_counter(9)); --additional_reg(7); --'0';
+ LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
+ LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
+ LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
+
+ -- 0 red
+ -- 1 orange
+ -- 2 green
+ -- 3 green
+
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+--
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data_q(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data_q(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data_q(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(28) <= port_sel(0);
+-- debug(29) <= ul_rx_fifofull;
+-- debug(30) <= ul_tx_fifofull;
+-- debug(31) <= '0';
+-- debug(32) <= tick_int;
+-- debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
+end architecture;