wq

diff --git a/xilinx/virtex4/fifo/fifo_18x512_oreg.xco b/xilinx/virtex4/fifo/fifo_18x512_oreg.xco
index e411eb3ddb82a8a24b03e260e06ed00a7e988884..a2f5b55e6098e43dc32f073720b6e4b6e2b7198c 100644 (file)
--- a/xilinx/virtex4/fifo/fifo_18x512_oreg.xco
+++ b/xilinx/virtex4/fifo/fifo_18x512_oreg.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version J.40
-# Date: Sun Apr 18 18:45:39 2010
+# Xilinx Core Generator version K.39
+# Date: Mon Apr 19 12:38:50 2010
 #
 ##############################################################
 #
@@ -24,22 +24,23 @@ SET flowvendor = Other
 SET formalverification = False
 SET foundationsym = False
 SET implementationfiletype = Ngc
-SET package = ff668
+SET package = ff1148
 SET removerpms = False
 SET simulationfiles = Behavioral
-SET speedgrade = -11
+SET speedgrade = -10
 SET verilogsim = False
 SET vhdlsim = True
 # END Project Options
 # BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
 # END Select
 # BEGIN Parameters
 CSET almost_empty_flag=false
 CSET almost_full_flag=false
 CSET component_name=fifo_18x512_oreg
 CSET data_count=true
-CSET data_count_width=9
+CSET data_count_width=10
+CSET disable_timing_violations=false
 CSET dout_reset_value=0
 CSET empty_threshold_assert_value=2
 CSET empty_threshold_negate_value=3
@@ -47,12 +48,12 @@ CSET enable_ecc=false
 CSET enable_int_clk=false
 CSET fifo_implementation=Common_Clock_Block_RAM
 CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=510
-CSET full_threshold_negate_value=509
+CSET full_threshold_assert_value=1022
+CSET full_threshold_negate_value=1021
 CSET input_data_width=18
-CSET input_depth=512
+CSET input_depth=1024
 CSET output_data_width=18
-CSET output_depth=512
+CSET output_depth=1024
 CSET overflow_flag=false
 CSET overflow_sense=Active_High
 CSET performance_options=Standard_FIFO
@@ -60,13 +61,13 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold
 CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port
 CSET read_clock_frequency=1
 CSET read_data_count=false
-CSET read_data_count_width=9
+CSET read_data_count_width=10
 CSET reset_pin=true
 CSET reset_type=Asynchronous_Reset
 CSET underflow_flag=false
 CSET underflow_sense=Active_High
-CSET use_dout_reset=false
-CSET use_embedded_registers=true
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
 CSET use_extra_logic=false
 CSET valid_flag=false
 CSET valid_sense=Active_High
@@ -74,8 +75,8 @@ CSET write_acknowledge_flag=false
 CSET write_acknowledge_sense=Active_High
 CSET write_clock_frequency=1
 CSET write_data_count=false
-CSET write_data_count_width=9
+CSET write_data_count_width=10
 # END Parameters
 GENERATE
-# CRC: 5d90b917
+# CRC: 98b1a0cf
 

diff --git a/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco b/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco
index 8de1da47fe723e1b17b8ff1831fbc255fabf8f71..d96b915800b6a707db219170ac5f3017d8c6d7f7 100644 (file)
--- a/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco
+++ b/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version J.40
-# Date: Fri Apr 16 21:01:46 2010
+# Xilinx Core Generator version K.39
+# Date: Mon Apr 19 12:37:12 2010
 #
 ##############################################################
 #
@@ -24,22 +24,23 @@ SET flowvendor = Other
 SET formalverification = False
 SET foundationsym = False
 SET implementationfiletype = Ngc
-SET package = ff668
+SET package = ff1148
 SET removerpms = False
 SET simulationfiles = Behavioral
-SET speedgrade = -11
+SET speedgrade = -10
 SET verilogsim = False
 SET vhdlsim = True
 # END Project Options
 # BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
 # END Select
 # BEGIN Parameters
 CSET almost_empty_flag=false
-CSET almost_full_flag=true
+CSET almost_full_flag=false
 CSET component_name=fifo_36x16k_oreg
 CSET data_count=true
 CSET data_count_width=14
+CSET disable_timing_violations=false
 CSET dout_reset_value=0
 CSET empty_threshold_assert_value=2
 CSET empty_threshold_negate_value=3
@@ -65,8 +66,8 @@ CSET reset_pin=true
 CSET reset_type=Asynchronous_Reset
 CSET underflow_flag=false
 CSET underflow_sense=Active_High
-CSET use_dout_reset=false
-CSET use_embedded_registers=true
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
 CSET use_extra_logic=false
 CSET valid_flag=false
 CSET valid_sense=Active_High
@@ -77,5 +78,5 @@ CSET write_data_count=false
 CSET write_data_count_width=14
 # END Parameters
 GENERATE
-# CRC: 4fce8c61
+# CRC: e09a62f9
 

diff --git a/xilinx/virtex4/fifo/fifo_var_oreg.vhd b/xilinx/virtex4/fifo/fifo_var_oreg.vhd
index 205615bc66708f5271b4940620524bfb361b8ce4..d563da2c09a32c1090cf9d321884f8f9f9a956b9 100644 (file)
--- a/xilinx/virtex4/fifo/fifo_var_oreg.vhd
+++ b/xilinx/virtex4/fifo/fifo_var_oreg.vhd
@@ -44,6 +44,23 @@ component fifo_18x512_oreg
     );
 end component;
 
+component fifo_36x512_oreg
+  port (
+    clk               : in std_logic;
+    din               : in std_logic_vector(17 downto 0);
+    prog_full_thresh  : in std_logic_vector(8 downto 0);
+    rd_en             : in std_logic;
+    rst               : in std_logic;
+    wr_en             : in std_logic;
+    data_count        : out std_logic_vector(8 downto 0);
+    dout              : out std_logic_vector(17 downto 0);
+    empty             : out std_logic;
+    full              : out std_logic;
+    prog_full         : out std_logic
+    );
+end component;
+
+
 component fifo_36x16k_oreg
   port (
     clk               : in std_logic;
@@ -78,9 +95,10 @@ end component;
 
 begin
 
-  assert    (FIFO_DEPTH >= 13 and FIFO_DEPTH <= 14 and FIFO_WIDTH = 36)
-         or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 18)
-         report "Selected data buffer size not implemented" severity error;
+--REPORT_EN: if ( ( (FIFO_DEPTH < 14 or FIFO_DEPTH >15) and FIFO_WIDTH = 36) or ( (FIFO_DEPTH < 9 or FIFO_DEPTH >9) and FIFO_WIDTH = 18) ) generate
+--  assert (FALSE) report "Selected data buffer type not implemented : depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error;  
+--end generate REPORT_EN;
+
 
 
 
@@ -139,4 +157,4 @@ begin
 
 
 
-end architecture;
\ No newline at end of file
+end architecture;