*** empty log message ***

diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
index 0da4d258ca7e007860c76f86980b1cdd45359d66..6df49cddaa03120268a77ea43b555e7fb2a371c0 100644 (file)
--- a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
@@ -863,9 +863,9 @@ begin
   end generate;
 
 
-  PROC_LED_COUNTER : process(CLK)
+  PROC_LED_COUNTER : process(SYSCLK)
     begin
-      if rising_edge(CLK) then
+      if rising_edge(SYSCLK) then
           led_counter <= led_counter + 1;
       end if;
     end process;

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index 24ee93b9f626098daf8319561445cd3c50dc93e0..2a46bff7506260e05f33936d7906f1c7e2fc9026 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -7,6 +7,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 
 library work;
 use work.trb_net_std.all;
+use work.trb_net_components.all;
 
 
 entity trb_net16_endpoint_hades_full is
@@ -140,404 +141,6 @@ end entity;
 
 architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full is
 
-  component trb_net_onewire_listener is
-    port(
-      CLK    : in std_logic;
-      CLK_EN : in std_logic;
-      RESET  : in std_logic;
-      MONITOR_IN : in std_logic;
-      DATA_OUT : out std_logic_vector(15 downto 0);
-      ADDR_OUT : out std_logic_vector(2 downto 0);
-      WRITE_OUT: out std_logic;
-      TEMP_OUT : out std_logic_vector(11 downto 0);
-      STAT     : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component trb_net_onewire is
-    generic(
-      USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
-      CLK_PERIOD : integer := 10  --clk period in ns
-      );
-    port(
-      CLK      : in std_logic;
-      RESET    : in std_logic;
-      --connection to 1-wire interface
-      ONEWIRE  : inout std_logic;
-      MONITOR_OUT : out std_logic;
-      --connection to id ram, according to memory map in TrbNetRegIO
-      DATA_OUT : out std_logic_vector(15 downto 0);
-      ADDR_OUT : out std_logic_vector(2 downto 0);
-      WRITE_OUT: out std_logic;
-      TEMP_OUT : out std_logic_vector(11 downto 0);
-      STAT     : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component trb_net16_regIO is
-    generic (
-      NUM_STAT_REGS      : integer range 0 to 6 := 3; --log2 of number of status registers
-      NUM_CTRL_REGS      : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-      --standard values for output registers
-      INIT_CTRL_REGS     : std_logic_vector(2**(3)*32-1 downto 0) :=
-              (others => '0');
-      --set to 0 for unused ctrl registers to save resources
-      USED_CTRL_REGS     : std_logic_vector(2**(3)-1 downto 0)   := "00000001";
-      --set to 0 for each unused bit in a register
-      USED_CTRL_BITMASK  : std_logic_vector(2**(3)*32-1 downto 0) :=
-              (others => '1');
-      USE_DAT_PORT        : integer range 0 to 1 := c_YES;  --internal data port
-      INIT_ADDRESS     : std_logic_vector(15 downto 0) := x"FFFF";
-      INIT_UNIQUE_ID   : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-      INIT_BOARD_INFO  : std_logic_vector(31 downto 0) := x"1111_2222";
-      INIT_ENDPOINT_ID : std_logic_vector(15 downto 0)  := x"0001";
-      COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
-      COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
-      HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
-      CLOCK_FREQ         : integer range 1 to 200 := 100 --MHz
-      );
-    port(
-    --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-    -- Port to API
-      API_DATA_OUT           : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_OUT     : out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_DATAREADY_OUT      : out std_logic;
-      API_READ_IN            : in  std_logic;
-      API_SHORT_TRANSFER_OUT : out std_logic;
-      API_DTYPE_OUT          : out std_logic_vector (3 downto 0);
-      API_ERROR_PATTERN_OUT  : out std_logic_vector (31 downto 0);
-      API_SEND_OUT           : out std_logic;
-      -- Receiver port
-      API_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_TYP_IN          : in  std_logic_vector (2 downto 0);
-      API_DATAREADY_IN    : in  std_logic;
-      API_READ_OUT        : out std_logic;
-      -- APL Control port
-      API_RUN_IN          : in  std_logic;
-      API_SEQNR_IN        : in  std_logic_vector (7 downto 0);
-
-      --Port to write Unique ID
-      IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0);
-      IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-      IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0);
-      IDRAM_WR_IN         : in  std_logic;
-      MY_ADDRESS_OUT      : out std_logic_vector(15 downto 0);
-      TRIGGER_MONITOR           : in  std_logic;  --strobe when timing trigger received
-      GLOBAL_TIME               : out std_logic_vector(31 downto 0); --global time, microseconds
-      LOCAL_TIME                : out std_logic_vector(7 downto 0);  --local time running with chip frequency
-      TIME_SINCE_LAST_TRG       : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
-      TIMER_US_TICK             : out std_logic;  --1 tick every microsecond
-
-    --Common Register in / out
-      COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
-      COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);
-    --Custom Register in / out
-      REGISTERS_IN        : in  std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
-      REGISTERS_OUT       : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
-    --Internal Data Port
-      DAT_ADDR_OUT        : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
-      DAT_READ_ENABLE_OUT : out std_logic;
-      DAT_WRITE_ENABLE_OUT: out std_logic;
-      DAT_DATA_OUT        : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
-      DAT_DATA_IN         : in  std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
-      DAT_DATAREADY_IN    : in  std_logic;
-      DAT_NO_MORE_DATA_IN : in  std_logic;
-      DAT_WRITE_ACK_IN    : in  std_logic;
-      DAT_UNKNOWN_ADDR_IN : in  std_logic;
-      DAT_TIMEOUT_OUT     : out std_logic;
-
-      STAT                : out std_logic_vector(31 downto 0);
-      STAT_ADDR_DEBUG     : out std_logic_vector(15 downto 0)
-      );
-  end component;
-
-  component trb_net16_iobuf is
-    generic (
-      IBUF_DEPTH            : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
-      IBUF_SECURE_MODE      : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
-      SBUF_VERSION          : integer range 0 to 1 := std_SBUF_VERSION;
-      OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
-      USE_ACKNOWLEDGE       : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
-      USE_CHECKSUM          : integer range 0 to 1 := c_YES;
-      USE_VENDOR_CORES      : integer range 0 to 1 := c_YES;
-      INIT_CAN_SEND_DATA    : integer range 0 to 1 := c_YES;
-      REPLY_CAN_SEND_DATA   : integer range 0 to 1 := c_YES;
-      REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
-      );
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-      --  Media direction port
-      MED_INIT_DATAREADY_OUT: out std_logic;
-      MED_INIT_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_INIT_READ_IN:       in  std_logic;
-
-      MED_REPLY_DATAREADY_OUT: out std_logic;
-      MED_REPLY_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_REPLY_READ_IN:       in  std_logic;
-
-      MED_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media(the IOBUF MUST read)
-      MED_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_READ_OUT:      out std_logic;
-      MED_ERROR_IN:      in  std_logic_vector (2 downto 0);
-
-      -- Internal direction port
-      INT_INIT_DATAREADY_OUT: out std_logic;
-      INT_INIT_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      INT_INIT_READ_IN:       in  std_logic;
-
-      INT_INIT_DATAREADY_IN:  in  std_logic;
-      INT_INIT_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_INIT_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      INT_INIT_READ_OUT:      out std_logic;
-
-      INT_REPLY_DATAREADY_OUT: out std_logic;
-      INT_REPLY_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      INT_REPLY_READ_IN:       in  std_logic;
-
-      INT_REPLY_DATAREADY_IN:  in  std_logic;
-      INT_REPLY_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_REPLY_PACKET_NUM_IN :in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      INT_REPLY_READ_OUT:      out std_logic;
-
-      -- Status and control port
-      STAT_GEN                  : out std_logic_vector (31 downto 0);
-      STAT_IBUF_BUFFER          : out std_logic_vector (31 downto 0);
-      CTRL_GEN                  : in  std_logic_vector (31 downto 0);
-      STAT_INIT_OBUF_DEBUG      : out std_logic_vector (31 downto 0);
-      STAT_REPLY_OBUF_DEBUG     : out std_logic_vector (31 downto 0)
-      );
-  end component;
-
-  component trb_net16_api_base is
-    generic (
-      API_TYPE          : integer range 0 to 1 := c_API_PASSIVE;
-      FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
-      FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
-      FORCE_REPLY       : integer range 0 to 1 := std_FORCE_REPLY;
-      SBUF_VERSION      : integer range 0 to 1 := std_SBUF_VERSION;
-      USE_VENDOR_CORES  : integer range 0 to 1 := c_YES;
-      SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
-      SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
-      APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
-      BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
-      );
-
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      -- APL Transmitter port
-      APL_DATA_IN           : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      APL_PACKET_NUM_IN     : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      APL_DATAREADY_IN      : in  std_logic;
-      APL_READ_OUT          : out std_logic;
-      APL_SHORT_TRANSFER_IN : in  std_logic;
-      APL_DTYPE_IN          : in  std_logic_vector (3 downto 0);
-      APL_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0);
-      APL_SEND_IN           : in  std_logic;
-      APL_TARGET_ADDRESS_IN : in  std_logic_vector (15 downto 0);-- the target (only for active APIs)
-
-      -- Receiver port
-      APL_DATA_OUT          : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      APL_PACKET_NUM_OUT    : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      APL_TYP_OUT           : out std_logic_vector (2 downto 0);
-      APL_DATAREADY_OUT     : out std_logic;
-      APL_READ_IN           : in  std_logic;
-
-      -- APL Control port
-      APL_RUN_OUT           : out std_logic;
-      APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);
-      APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);
-      APL_LENGTH_IN         : in  std_logic_vector (15 downto 0);
-
-      -- Internal direction port
-      -- the ports with master or slave in their name are to be mapped by the active api
-      -- to the init respectivly the reply path and vice versa in the passive api.
-      -- lets define: the "master" path is the path that I send data on.
-      -- master_data_out and slave_data_in are only used in active API for termination
-      INT_MASTER_DATAREADY_OUT  : out std_logic;
-      INT_MASTER_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      INT_MASTER_READ_IN        : in  std_logic;
-
-      INT_MASTER_DATAREADY_IN   : in  std_logic;
-      INT_MASTER_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_MASTER_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      INT_MASTER_READ_OUT       : out std_logic;
-
-      INT_SLAVE_DATAREADY_OUT   : out std_logic;
-      INT_SLAVE_DATA_OUT        : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_SLAVE_PACKET_NUM_OUT  : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      INT_SLAVE_READ_IN         : in  std_logic;
-
-      INT_SLAVE_DATAREADY_IN    : in  std_logic;
-      INT_SLAVE_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_SLAVE_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      INT_SLAVE_READ_OUT        : out std_logic;
-
-      -- Status and control port
-      CTRL_SEQNR_RESET          : in  std_logic;
-      STAT_FIFO_TO_INT          : out std_logic_vector(31 downto 0);
-      STAT_FIFO_TO_APL          : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-
-
-  component trb_net16_io_multiplexer is
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      --  Media direction port
-      MED_DATAREADY_IN:  in  STD_LOGIC;
-      MED_DATA_IN:       in  STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN:  in  STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
-      MED_READ_OUT:      out STD_LOGIC;
-
-      MED_DATAREADY_OUT: out STD_LOGIC;
-      MED_DATA_OUT:      out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
-      MED_READ_IN:       in  STD_LOGIC;
-
-      -- Internal direction port
-      INT_DATA_OUT:      out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
-      INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
-      INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-      INT_READ_IN:       in  STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
-      INT_DATAREADY_IN:  in  STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-      INT_DATA_IN:       in  STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
-      INT_PACKET_NUM_IN:  in  STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
-      INT_READ_OUT:      out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
-      -- Status and control port
-      CTRL:              in  STD_LOGIC_VECTOR (31 downto 0);
-      STAT:              out STD_LOGIC_VECTOR (31 downto 0)
-      );
-  end component;
-
-  component trb_net16_term_buf is
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      MED_INIT_DATAREADY_OUT:     out std_logic;
-      MED_INIT_DATA_OUT:          out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
-      MED_INIT_PACKET_NUM_OUT:    out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_INIT_READ_IN:           in  std_logic;
-
-      MED_REPLY_DATAREADY_OUT:     out std_logic;
-      MED_REPLY_DATA_OUT:          out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
-      MED_REPLY_PACKET_NUM_OUT:    out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_REPLY_READ_IN:           in  std_logic;
-
-      MED_DATAREADY_IN:      in  std_logic;
-      MED_DATA_IN:           in  std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
-      MED_PACKET_NUM_IN:     in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      MED_READ_OUT:          out std_logic
-      );
-  end component;
-
-  component trb_net16_trigger is
-    generic (
-      USE_TRG_PORT : integer range 0 to 1 := c_YES;
-                --even when NO, ERROR_PACKET_IN is used for automatic replys
-      SECURE_MODE  : integer range 0 to 1 := std_TERM_SECURE_MODE
-                --if secure_mode is not used, apl must provide error pattern and dtype until
-                --next trigger comes in. In secure mode these need to be available while relase_trg is high only
-      );
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      INT_DATAREADY_OUT:     out std_logic;
-      INT_DATA_OUT:          out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_PACKET_NUM_OUT:    out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      INT_READ_IN:           in  std_logic;
-
-      INT_DATAREADY_IN:      in  std_logic;
-      INT_DATA_IN:           in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      INT_PACKET_NUM_IN:     in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      INT_READ_OUT:          out std_logic;
-
-      -- Trigger information output
-      TRG_TYPE_OUT          : out std_logic_vector (3 downto 0);
-      TRG_NUMBER_OUT        : out std_logic_vector (15 downto 0);
-      TRG_CODE_OUT          : out std_logic_vector (7 downto 0);
-      TRG_INFORMATION_OUT   : out std_logic_vector (7 downto 0);
-      TRG_RECEIVED_OUT      : out std_logic;
-      TRG_RELEASE_IN        : in  std_logic;
-      TRG_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0)
-      );
-  end component;
-
-  component trb_net16_ipudata is
-    port(
-    --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-    -- Port to API
-      API_DATA_OUT           : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_OUT     : out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_DATAREADY_OUT      : out std_logic;
-      API_READ_IN            : in  std_logic;
-      API_SHORT_TRANSFER_OUT : out std_logic;
-      API_DTYPE_OUT          : out std_logic_vector (3 downto 0);
-      API_ERROR_PATTERN_OUT  : out std_logic_vector (31 downto 0);
-      API_SEND_OUT           : out std_logic;
-      -- Receiver port
-      API_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_TYP_IN          : in  std_logic_vector (2 downto 0);
-      API_DATAREADY_IN    : in  std_logic;
-      API_READ_OUT        : out std_logic;
-      -- APL Control port
-      API_RUN_IN          : in  std_logic;
-      API_SEQNR_IN        : in  std_logic_vector (7 downto 0);
-      API_LENGTH_OUT      : out std_logic_vector (15 downto 0);
-      MY_ADDRESS_IN       : in  std_logic_vector (15 downto 0);
-
-      --Information received with request
-      IPU_NUMBER_OUT   : out std_logic_vector (15 downto 0);
-      IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
-      --start strobe
-      IPU_START_READOUT_OUT: out std_logic;
-      --detector data, equipped with DHDR
-      IPU_DATA_IN          : in  std_logic_vector (31 downto 0);
-      IPU_DATAREADY_IN     : in  std_logic;
-      --no more data, end transfer, send TRM
-      IPU_READOUT_FINISHED_IN : in  std_logic;
-      --will be low every second cycle due to 32bit -> 16bit conversion
-      IPU_READ_OUT         : out std_logic;
-      IPU_LENGTH_IN        : in  std_logic_vector (15 downto 0);
-      IPU_ERROR_PATTERN_IN : in  std_logic_vector (31 downto 0);
-
-      STAT_DEBUG          : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
 
 signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
 signal apl_to_buf_INIT_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
@@ -605,11 +208,11 @@ signal buf_IDRAM_DATA_IN       :  std_logic_vector(15 downto 0);
 signal buf_IDRAM_DATA_OUT      :  std_logic_vector(15 downto 0);
 signal buf_IDRAM_ADDR_IN       :  std_logic_vector(2 downto 0);
 signal buf_IDRAM_WR_IN         :  std_logic;
-signal reset_internal          :  std_logic;
+signal reset_no_link          :  std_logic;
 
 begin
 
-  reset_internal <= MED_STAT_OP_IN(13) or RESET;
+  reset_no_link <= MED_STAT_OP_IN(14) or RESET;
   MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15);
   MED_CTRL_OP_OUT(14 downto 0) <= (others => '0');
   MED_STAT_OP <= MED_STAT_OP_IN;
@@ -633,7 +236,7 @@ begin
           port map (
             --  Misc
             CLK     => CLK ,
-            RESET   => RESET,
+            RESET   => reset_no_link,
             CLK_EN  => CLK_EN,
             --  Media direction port
             MED_INIT_DATAREADY_OUT  => MED_IO_DATAREADY_OUT(i*2),
@@ -1027,7 +630,7 @@ begin
         termbuf: trb_net16_term_buf
           port map(
             CLK    => CLK,
-            RESET  => RESET,
+            RESET  => reset_no_link,
             CLK_EN => CLK_EN,
             MED_DATAREADY_IN       => MED_IO_DATAREADY_IN(i),
             MED_DATA_IN            => MED_IO_DATA_IN,
@@ -1050,7 +653,7 @@ begin
   MPLEX: trb_net16_io_multiplexer
     port map (
       CLK      => CLK,
-      RESET    => RESET,
+      RESET    => reset_no_link,
       CLK_EN   => CLK_EN,
       MED_DATAREADY_IN   => MED_DATAREADY_IN,
       MED_DATA_IN        => MED_DATA_IN,

diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd
index 78ec360d4963b0fbfde2e68d0fb84ac1e4990523..b4cd7ac50d30b2914d035049f840f48a0b13375e 100644 (file)
--- a/trb_net16_hub_ipu_logic.vhd
+++ b/trb_net16_hub_ipu_logic.vhd
@@ -376,10 +376,11 @@ begin
   gen_read_out : for i in 0 to POINT_NUMBER-1 generate
     buf_REPLY_READ_OUT(i) <= reg_current_reply_reading_TRM(i) --current_reply_reading_TRM(i)
                           or reg_current_reply_reading_HDR(i) --current_reply_reading_HDR(i)
-                          or current_reply_auto_reading_DHDR(i) --current_reply_auto_reading_DHDR(i)
+                          or (reg_current_reply_auto_reading_DHDR(i) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1))
+--                          or current_reply_auto_reading_DHDR(i) --current_reply_auto_reading_DHDR(i)
                           or saved_reading_padding(i)
-                          or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2))
-                          or (reply_fsm_state(4) and reply_reading_H0(i));
+                          or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2));
+--                           or (reply_fsm_state(4) and reply_reading_H0(i));
 
 
   end generate;
@@ -461,12 +462,14 @@ begin
 --saving (D)HDR
 -------------------------
   gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate
-    hdrram_write_enable(i) <= (current_reply_reading_HDR(i) and
-                          (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or
-                              (current_reply_reading_DHDR(i) and
-                          (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i)
+    hdrram_write_enable(i) <= (current_reply_reading_HDR(i) or current_reply_reading_DHDR(i)) and not reply_reading_H0(i);
+
+--     (current_reply_reading_HDR(i) and
+--                           (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or
+--                               (current_reply_reading_DHDR(i) and
+--                           (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i)
 --                           (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not                               REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2))
-                          ));
+--                           ));
                                --read normal HDR_F0 to DHDR_F1 and DHDR_F2 without read='1'
     hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH);
     hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0';
@@ -736,9 +739,11 @@ begin
       end process;
   end generate;
 
-  comb_REPLY_muxed_DATAREADY <= or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not current_reply_reading_trm
+  comb_REPLY_muxed_DATAREADY <= or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not reg_current_reply_reading_trm
                                        and not reply_reading_H0 and not saved_reading_padding)
                                   and REPLY_POOL_next_read;
+                                  --reg_current_reply_reading_trm can be used instead of current_reply_reading_trm since
+                                  -- reply_reading_H0 is checked!
 
 --temporary! no real compare is done!
 reply_compare_finished <= reply_compare_start;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 2d54a5f590b720f238fe5b0b9565146c8d9e2275..729033ef08ecdef1f4ba6c59544af9d8823260e3 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -435,6 +435,54 @@ package trb_net_components is
 
 
 
+  component trb_net16_ipudata is
+    port(
+    --  Misc
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+    -- Port to API
+      API_DATA_OUT           : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      API_PACKET_NUM_OUT     : out std_logic_vector (c_NUM_WIDTH-1  downto 0);
+      API_DATAREADY_OUT      : out std_logic;
+      API_READ_IN            : in  std_logic;
+      API_SHORT_TRANSFER_OUT : out std_logic;
+      API_DTYPE_OUT          : out std_logic_vector (3 downto 0);
+      API_ERROR_PATTERN_OUT  : out std_logic_vector (31 downto 0);
+      API_SEND_OUT           : out std_logic;
+      -- Receiver port
+      API_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      API_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
+      API_TYP_IN          : in  std_logic_vector (2 downto 0);
+      API_DATAREADY_IN    : in  std_logic;
+      API_READ_OUT        : out std_logic;
+      -- APL Control port
+      API_RUN_IN          : in  std_logic;
+      API_SEQNR_IN        : in  std_logic_vector (7 downto 0);
+      API_LENGTH_OUT      : out std_logic_vector (15 downto 0);
+      MY_ADDRESS_IN       : in  std_logic_vector (15 downto 0);
+
+      --Information received with request
+      IPU_NUMBER_OUT   : out std_logic_vector (15 downto 0);
+      IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
+      --start strobe
+      IPU_START_READOUT_OUT: out std_logic;
+      --detector data, equipped with DHDR
+      IPU_DATA_IN          : in  std_logic_vector (31 downto 0);
+      IPU_DATAREADY_IN     : in  std_logic;
+      --no more data, end transfer, send TRM
+      IPU_READOUT_FINISHED_IN : in  std_logic;
+      --will be low every second cycle due to 32bit -> 16bit conversion
+      IPU_READ_OUT         : out std_logic;
+      IPU_LENGTH_IN        : in  std_logic_vector (15 downto 0);
+      IPU_ERROR_PATTERN_IN : in  std_logic_vector (31 downto 0);
+
+      STAT_DEBUG          : out std_logic_vector(31 downto 0)
+      );
+  end component;
+
+
+
 
   component trb_net16_med_8_SDR_OS is
     generic(
@@ -1010,6 +1058,44 @@ package trb_net_components is
 
 
 
+  component trb_net16_trigger is
+    generic (
+      USE_TRG_PORT : integer range 0 to 1 := c_YES;
+                --even when NO, ERROR_PACKET_IN is used for automatic replys
+      SECURE_MODE  : integer range 0 to 1 := std_TERM_SECURE_MODE
+                --if secure_mode is not used, apl must provide error pattern and dtype until
+                --next trigger comes in. In secure mode these need to be available while relase_trg is high only
+      );
+    port(
+      --  Misc
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+
+      INT_DATAREADY_OUT:     out std_logic;
+      INT_DATA_OUT:          out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      INT_PACKET_NUM_OUT:    out std_logic_vector (c_NUM_WIDTH-1  downto 0);
+      INT_READ_IN:           in  std_logic;
+
+      INT_DATAREADY_IN:      in  std_logic;
+      INT_DATA_IN:           in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      INT_PACKET_NUM_IN:     in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
+      INT_READ_OUT:          out std_logic;
+
+      -- Trigger information output
+      TRG_TYPE_OUT          : out std_logic_vector (3 downto 0);
+      TRG_NUMBER_OUT        : out std_logic_vector (15 downto 0);
+      TRG_CODE_OUT          : out std_logic_vector (7 downto 0);
+      TRG_INFORMATION_OUT   : out std_logic_vector (7 downto 0);
+      TRG_RECEIVED_OUT      : out std_logic;
+      TRG_RELEASE_IN        : in  std_logic;
+      TRG_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0)
+      );
+  end component;
+
+
+
+
 
 
   component wide_adder_17x16 is