attilio

diff --git a/compile_gsi.pl b/compile_gsi.pl
index a6c322f1cd4e51a04631eb1d1047ea0fc2bac727..d9f46ee5b93d302218f28a9093bf8d296a4c4b5e 100755 (executable)
--- a/compile_gsi.pl
+++ b/compile_gsi.pl
@@ -16,7 +16,7 @@ use strict;
 #my $synplify_path = '/d/sugar/lattice/synplify/synOEM7.2/synplify_linux/';
 
 my $lattice_path = '/storage120/lattice/isplever7.2/isptools/';
-my $synplify_path = '/storage120/syn/syn96L2/synplify_linux';
+my $synplify_path = '/storage120/syn/syn96L3/synplify_linux';
 
 use FileHandle;
 

diff --git a/mdc_oepb.prj b/mdc_oepb.prj
index 91e1db1185aae9f615b27c5aa017d8b81afa32f9..b391f876fbfbf14e66f3e13ac7586421ed5bb717 100644 (file)
--- a/mdc_oepb.prj
+++ b/mdc_oepb.prj
@@ -53,8 +53,10 @@ add_file -vhdl -lib work "design/counter_12bit.vhd"
 add_file -vhdl -lib work "design/counter_4bit.vhd"
 add_file -vhdl -lib work "design/counter_8bit.vhd"
 add_file -vhdl -lib work "design/edge_to_pulse.vhd"
-add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh.vhd"
-add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width.vhd"
+#add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh.vhd"
+#add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width.vhd"
+add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh_reg_out.vhd"
+add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width_reg_out.vhd"
 add_file -vhdl -lib work "design/initialization_RAM.vhd"
 add_file -vhdl -lib work "design/load_mode_line.vhd"
 add_file -vhdl -lib work "design/load_ROC1_tdc_setup.vhd"