Update SODA source and client

diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd
index 4198883e1c3060dc2cf79e9aeda6bb6d65e11d44..361f15947bdf2dcd9f3d9b5c22058c878304eae4 100644 (file)
--- a/source/med_ecp3_sfp_sync_down.vhd
+++ b/source/med_ecp3_sfp_sync_down.vhd
@@ -10,7 +10,7 @@ use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.med_sync_define.all;
 
-entity med_ecp3_sfp_sync is
+entity med_ecp3_sfp_sync_down is
   generic(
     SERDES_NUM : integer range 0 to 3 := 0;
 --     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
@@ -67,14 +67,14 @@ entity med_ecp3_sfp_sync is
 end entity;
 
 
-architecture med_ecp3_sfp_sync_arch of med_ecp3_sfp_sync is
+architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is
 
   -- Placer Directives
   attribute HGROUP : string;
   -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_sync_arch : architecture  is "media_interface_group";
+  attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture  is "media_interface_group";
   attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_sync_arch : architecture is "off";
+  attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";
 
 
 component DCS
@@ -495,5 +495,5 @@ STAT_OP(10) <= rx_allow;
 STAT_OP(9)  <= tx_allow;
 STAT_OP(8 downto 4) <= (others => '0');
 STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_arch;
+end med_ecp3_sfp_sync_down_arch;
 

diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd
index da28b0ec8593967fe16fbf15556b11490f7b47ae..f0052aa2a8ab38ce1af6cf004264583605aca3ad 100644 (file)
--- a/source/med_ecp3_sfp_sync_up.vhd
+++ b/source/med_ecp3_sfp_sync_up.vhd
@@ -10,7 +10,7 @@ use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.med_sync_define.all;
 
-entity med_ecp3_sfp_sync is
+entity med_ecp3_sfp_sync_up is
   generic(
     SERDES_NUM : integer range 0 to 3 := 0;
 --     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
@@ -67,14 +67,14 @@ entity med_ecp3_sfp_sync is
 end entity;
 
 
-architecture med_ecp3_sfp_sync_arch of med_ecp3_sfp_sync is
+architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is
 
   -- Placer Directives
   attribute HGROUP : string;
   -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_sync_arch : architecture  is "media_interface_group";
+  attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture  is "media_interface_group";
   attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_sync_arch : architecture is "off";
+  attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";
 
 
 component DCS
@@ -494,5 +494,5 @@ STAT_OP(10) <= rx_allow;
 STAT_OP(9)  <= tx_allow;
 STAT_OP(8 downto 4) <= (others => '0');
 STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_arch;
+end med_ecp3_sfp_sync_up_arch;
 

diff --git a/source/posedge_to_pulse.vhd b/source/posedge_to_pulse.vhd
new file mode 100644 (file)
index 0000000..1bdc601
--- /dev/null
+++ b/source/posedge_to_pulse.vhd
@@ -0,0 +1,72 @@
+-----------------------------------------------------------------------------------
+-- posedge_to_pulse
+--             Makes pulse with duration 1 clock-cycle from positive edge
+--     
+-- inputs
+--             clock_in : clock input for input signal
+--             clock_out : clock input to synchronize to
+--             en_clk : clock enable
+--             signal_in : rising edge of this signal will result in pulse
+--
+--     output
+--             pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity posedge_to_pulse is
+       port (
+               clock_in     : in  std_logic;
+               clock_out     : in  std_logic;
+               en_clk    : in  std_logic;
+               signal_in : in  std_logic;
+               pulse     : out std_logic
+       );
+end posedge_to_pulse;
+
+architecture behavioral of posedge_to_pulse is
+
+  signal resetff       : std_logic := '0';
+  signal last_signal_in        : std_logic := '0';
+  signal qff   : std_logic := '0'; 
+  signal qff1  : std_logic := '0'; 
+  signal qff2  : std_logic := '0'; 
+  signal qff3  : std_logic := '0'; 
+begin  
+
+process (clock_in)
+begin
+       if rising_edge(clock_in) then
+               if resetff='1' then
+                       qff <= '0';
+               elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then 
+                       qff <= '1';
+               else
+                       qff <= qff;
+               end if;
+               last_signal_in <= signal_in;
+       end if;
+end process;
+resetff <= qff2;
+
+process (clock_out)
+begin
+       if rising_edge(clock_out) then
+               if qff3='0' and qff2='1' then 
+                       pulse <= '1'; 
+               else 
+                       pulse <= '0';
+               end if;
+               qff3 <= qff2;
+               qff2 <= qff1;
+               qff1 <= qff;
+       end if;
+end process; 
+
+
+end behavioral;
+

diff --git a/source/soda_client.vhd b/source/soda_client.vhd
index 6642b41bb2ad8f4a649b294f775c4e4620868851..fcae1d305bc17f636af994b227cbec1019f836a4 100644 (file)
--- a/source/soda_client.vhd
+++ b/source/soda_client.vhd
@@ -208,23 +208,28 @@ end process TRANSFORM;
        end process THE_READ_REG_PROC;
 \r
 --     debug signals\r
-       DEBUG_CLIENT : process(SYSCLK)\r
+       DEBUG_CLIENT : process(SODACLK)\r
        begin\r
-               if( rising_edge(SYSCLK) ) then\r
+               if( rising_edge(SODACLK) ) then\r
                        debug_status_S(0)               <= RESET;
                        debug_status_S(1)               <= CLEAR;
                        debug_status_S(2)               <= CLK_EN;
                        if   ( RESET = '1' ) then\r
                                debug_rx_cnt_S          <= (others => '0');
                                debug_tx_cnt_S          <= (others => '0');
-                       elsif (tx_dlm_out_S = '1') then
-                               debug_tx_cnt_S  <= debug_tx_cnt_S + 1;
-                       elsif (RX_DLM_IN = '1') then
-                               debug_rx_cnt_S  <= debug_rx_cnt_S + 1;
-                       elsif (start_of_superburst_S = '1') then
-                               debug_sos_cnt_S <= debug_sos_cnt_S + 1;
-                       elsif (soda_cmd_valid_S = '1') then
-                               debug_cmd_cnt_S <= debug_cmd_cnt_S + 1;
+                       else
+                               if (tx_dlm_out_S = '1') then
+                                       debug_tx_cnt_S  <= debug_tx_cnt_S + 1;
+                               end if;
+                               if (RX_DLM_IN = '1') then
+                                       debug_rx_cnt_S  <= debug_rx_cnt_S + 1;
+                               end if;
+                               if (start_of_superburst_S = '1') then
+                                       debug_sos_cnt_S <= debug_sos_cnt_S + 1;
+                               end if;
+                               if (soda_cmd_valid_S = '1') then
+                                       debug_cmd_cnt_S <= debug_cmd_cnt_S + 1;
+                               end if;
                        end if;
                end if; \r
        end process;\r

diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 4c5d9b6b694add7e448d3a659f354b9376187ef0..3825aad3d39c6386aa0261fa14987c752df330fc 100644 (file)
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -89,6 +89,7 @@ package soda_components is
        component soda_source   -- box containing soda_source components
                port(
                        SYSCLK                                  : in    std_logic; -- fabric clock
+                       SODACLK                                 : in    std_logic; -- clock for data to serdes
                        RESET                                           : in    std_logic; -- synchronous reset
                        CLEAR                                           : in    std_logic; -- asynchronous reset
                        CLK_EN                                  : in    std_logic; 
@@ -254,5 +255,117 @@ package soda_components is
                        PULSE_OUT               : out std_logic
                );
        end component;
+       
+component med_ecp3_sfp_sync_down is
+  generic(
+    SERDES_NUM : integer range 0 to 3 := 0;
+--     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
+    IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
+    );
+  port(
+    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    --Internal Connection TX
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic := '0';
+    --Internal Connection RX
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+    MED_DATAREADY_OUT  : out std_logic := '0';
+    MED_READ_IN        : in  std_logic;
+    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
+    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+    
+    --Sync operation
+    RX_DLM             : out std_logic := '0';
+    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
+    TX_DLM             : in  std_logic := '0';
+    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+    
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;  --not used
+    SD_REFCLK_N_IN     : in  std_logic;  --not used
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+   );
+end component;
+
+component med_ecp3_sfp_sync_up is
+  generic(
+    SERDES_NUM : integer range 0 to 3 := 0;
+--     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
+    IS_SYNC_SLAVE   : integer := c_YES       --select slave mode
+    );
+  port(
+    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    --Internal Connection TX
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic := '0';
+    --Internal Connection RX
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+    MED_DATAREADY_OUT  : out std_logic := '0';
+    MED_READ_IN        : in  std_logic;
+    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
+    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+    
+    --Sync operation
+    RX_DLM             : out std_logic := '0';
+    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
+    TX_DLM             : in  std_logic := '0';
+    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+    
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;  --not used
+    SD_REFCLK_N_IN     : in  std_logic;  --not used
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+   );
+end component;
 \r
 end package;

diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd
index 48690fe6ae821dab0890ee3806dd62bbdbf49a07..3b61b2273f190f056951f1b0af5a80a8bad134b6 100644 (file)
--- a/source/soda_packet_handler.vhd
+++ b/source/soda_packet_handler.vhd
@@ -141,6 +141,8 @@ begin
                                                soda_pkt_valid_S                                                <= '0';
                                                soda_pkt_word_S                                         <= (others=>'0');
                                        when c_SODA_PKT1        =>
+                                               START_OF_SUPERBURST_OUT                         <= '0';
+                                               SODA_CMD_VALID_OUT                                      <= '0';
                                                soda_pkt_word_S(31 downto 24)           <=      RX_DLM_WORD_IN;
                                        when c_SODA_PKT2        =>
                                                -- do nothing -- disregard K28.7

diff --git a/source/soda_source.vhd b/source/soda_source.vhd
index 37a0d68f17c4bc52d29778f6a4fd23f46d9e4e76..e7aa09b08aba6d2cb16313b3b38f5f8ee7ef2271 100644 (file)
--- a/source/soda_source.vhd
+++ b/source/soda_source.vhd
@@ -11,6 +11,7 @@ use work.soda_components.all;
 entity soda_source is
        port(
                SYSCLK                                  : in    std_logic; -- fabric clock
+               SODACLK                                 : in    std_logic; -- clock for data to serdes
                RESET                                           : in    std_logic; -- synchronous reset
                CLEAR                                           : in    std_logic; -- asynchronous reset
                CLK_EN                                  : in    std_logic; 
@@ -34,10 +35,21 @@ end soda_source;
 
 architecture Behavioral of soda_source is
 
+component posedge_to_pulse is
+       port (
+               clock_in     : in  std_logic;
+               clock_out     : in  std_logic;
+               en_clk    : in  std_logic;
+               signal_in : in  std_logic;
+               pulse     : out std_logic
+       );
+end component;
+
        --SODA
        signal link_phase_S                                     : natural range 0 to 1 := 0;
        signal soda_cmd_word_S                          : std_logic_vector(30 downto 0) := (others => '0');
        signal soda_cmd_strobe_S                        : std_logic := '0';
+       signal soda_cmd_strobe_sodaclk_S        : std_logic := '0';     
        signal start_of_superburst_S            : std_logic := '0';
        signal super_burst_nr_S                         : std_logic_vector(30 downto 0) := (others => '0');             -- from super-burst-nr-generator
        
@@ -73,7 +85,7 @@ begin
        superburst_gen :  soda_superburst_generator
                generic map(BURST_COUNT         => 16)
                port map(
-                       SODACLK                                         =>      SYSCLK,         -- Here sysclk is the same as sodaclk; we are still at the source
+                       SODACLK                                         =>      SODACLK,                
                        RESET                                                   =>      RESET,
                        CLEAR                                                   =>      '0',
                        CLK_EN                                          =>      CLK_EN,
@@ -85,13 +97,13 @@ begin
 
        packet_builder : soda_packet_builder
                port map(
-                       SODACLK                                 =>      SYSCLK,
+                       SODACLK                                 =>      SODACLK,
                        RESET                                           =>      RESET,
                        CLEAR                                           =>      '0',
                        CLK_EN                                  => CLK_EN,
                        --Internal Connection
                        LINK_PHASE                              =>      link_phase_S,
-                       SODA_CMD_STROBE_IN      => soda_cmd_strobe_S,
+                       SODA_CMD_STROBE_IN      => soda_cmd_strobe_sodaclk_S,
                        START_OF_SUPERBURST     => start_of_superburst_S,
                        SUPER_BURST_NR_IN               => super_burst_nr_S,
                        SODA_CMD_WORD_IN                => soda_cmd_word_S,
@@ -103,7 +115,7 @@ begin
 
        src_reply_handler : soda_reply_handler
                port map(
-                       SYSCLK                                          =>      SYSCLK,
+                       SYSCLK                                          =>      SODACLK,
                        RESET                                                   => RESET,
                        CLEAR                                                   =>      '0',
                        CLK_EN                                          =>      '1',
@@ -118,7 +130,7 @@ begin
 
        src_calibration_timer : soda_calibration_timer
                port map(
-                       SYSCLK                                          =>      SYSCLK,
+                       SYSCLK                                          =>      SODACLK,
                        RESET                                                   => RESET,
                        CLEAR                                                   =>      '0',
                        CLK_EN                                          =>      '1',
@@ -142,9 +154,9 @@ begin
 -----------------------------------------------------------
 --     Phase fsm for 16-bit transmissions                                                      --
 -----------------------------------------------------------
-       phase_fsm_proc : process(SYSCLK)
+       phase_fsm_proc : process(SODACLK)
        begin
-               if rising_edge(SYSCLK) then
+               if rising_edge(SODACLK) then
                        if( RESET = '1' ) then
                                link_phase_S    <= 0;
                        elsif (link_phase_S < 1) then
@@ -236,6 +248,13 @@ begin
        end case;
 end process TRANSFORM;
 
+posedge_to_pulse1: posedge_to_pulse port map(
+               clock_in => SYSCLK,
+               clock_out => SODACLK,
+               en_clk => '1',
+               signal_in => soda_cmd_strobe_S,
+               pulse => soda_cmd_strobe_sodaclk_S);
+
 ---------------------------------------------------------
 -- data handling                                       --
 ---------------------------------------------------------
@@ -253,6 +272,7 @@ end process TRANSFORM;
                                soda_cmd_strobe_S       <= '1';
                                soda_cmd_word_S <= SODA_DATA_IN(30 downto 0);
                        elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then
+                               soda_cmd_strobe_S       <= '0';
                                LEDregister_i           <= SODA_DATA_IN;
 --                     elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then
 --                             TEST_LINE_i                     <= SODA_DATA_IN;

diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd
index dfcb2e79df2724ace3022dd0afa1c53f2c31fdcf..d9c7e5860bcb03c278265e9e85a84c4847949208 100644 (file)
--- a/source/trb3_periph_sodaclient.vhd
+++ b/source/trb3_periph_sodaclient.vhd
@@ -16,7 +16,7 @@ entity trb3_periph_sodaclient is
     SYNC_MODE : integer range 0 to 1 := c_YES;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
     USE_125_MHZ : integer := c_NO;
     CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 2
+    NUM_INTERFACES : integer := 1
     );
   port(
     --Clocks 
@@ -123,8 +123,6 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
   attribute syn_preserve of GSR_N : signal is true;
   signal clk_sys_internal         : std_logic;
   signal clk_raw_internal         : std_logic;
-  signal rx_clock_half             : std_logic;
-  signal rx_clock_full             : std_logic;
   signal clk_tdc                  : std_logic;
   signal time_counter, time_counter2 : unsigned(31 downto 0);
   --Media Interface
@@ -181,21 +179,25 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
   signal spimem_unknown_addr_out : std_logic;
   signal spimem_write_ack_out    : std_logic;
 
+  --media interface
   signal sci1_ack      : std_logic;
   signal sci1_write    : std_logic;
   signal sci1_read     : std_logic;
   signal sci1_data_in  : std_logic_vector(7 downto 0);
   signal sci1_data_out : std_logic_vector(7 downto 0);
   signal sci1_addr     : std_logic_vector(8 downto 0);  
-  signal sci2_ack      : std_logic;
-  signal sci2_nack     : std_logic;
-  signal sci2_write    : std_logic;
-  signal sci2_read     : std_logic;
-  signal sci2_data_in  : std_logic_vector(7 downto 0);
-  signal sci2_data_out : std_logic_vector(7 downto 0);
-  signal sci2_addr     : std_logic_vector(8 downto 0);  
+  signal sci1_nack     : std_logic;
 
        --SODA
+  signal soda_rx_clock_half : std_logic;
+  signal soda_rx_clock_full : std_logic;
+  signal tx_dlm_i          : std_logic;
+  signal rx_dlm_i          : std_logic;
+  signal tx_dlm_word       : std_logic_vector(7 downto 0);
+  signal rx_dlm_word       : std_logic_vector(7 downto 0);
+  signal make_reset        : std_logic;
+
+  -- SODA slow controll
        signal soda_ack      : std_logic;
 --     signal soda_nack     : std_logic;
        signal soda_write    : std_logic;
@@ -205,18 +207,11 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
        signal soda_addr     : std_logic_vector(3 downto 0);  
        signal soda_leds     : std_logic_vector(3 downto 0);  
 
-       --TDC
-  signal hit_in_i : std_logic_vector(63 downto 0);
-      
-  signal soda_rx_clock_half : std_logic;
-  signal soda_rx_clock_full : std_logic;
-  signal tx_dlm_i          : std_logic;
-  signal rx_dlm_i          : std_logic;
-  signal tx_dlm_word       : std_logic_vector(7 downto 0);
-  signal rx_dlm_word                   : std_logic_vector(7 downto 0);\r
-  \r
   signal       link_debug_in_S : std_logic_vector(31 downto 0);
-
+  signal general_reset_i    : std_logic := '1';
+  
+  signal       soda_counter_i  : unsigned(3 downto 0);
+  attribute syn_keep of soda_counter_i     : signal is true;
        
 begin
 ---------------------------------------------------------------------------
@@ -235,14 +230,20 @@ begin
       CLK_IN        => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
       SYSCLK_IN     => clk_sys_i,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      RESET_IN      => '0', --general_reset_i, -- '0',              -- general reset signal (SYSCLK) --peter schakel
       TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
       CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
       RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
       DEBUG_OUT     => open
       );  
 
-
+       process(clk_sys_i) 
+       begin
+               if rising_edge(clk_sys_i) then
+                       general_reset_i <= not SFP_LOS(1);
+               end if;
+       end process;
+       
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
@@ -263,8 +264,8 @@ end generate;
 
 gen_sync_clocks : if SYNC_MODE = c_YES generate
        clk_sys_i       <= clk_sys_internal;
-       clk_soda_i      <= rx_clock_full;
---     clk_200_i       <= rx_clock_full;
+       clk_soda_i      <= soda_rx_clock_full;
+--     clk_200_i       <= soda_rx_clock_full;
 end generate;
 
 gen_local_clocks : if SYNC_MODE = c_NO generate
@@ -275,209 +276,189 @@ end generate;
 
 
 ---------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
+-- Endpoint
 ---------------------------------------------------------------------------
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
     generic map(
-      SERDES_NUM  => 1,     --number of serdes in quad
-      EXT_CLOCK   => c_NO,  --use internal clock
-      USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
-      USE_125_MHZ => USE_125_MHZ,
-      USE_CTC     => c_NO,
-      USE_SLAVE   => SYNC_MODE
-      )      
+               USE_CHANNEL               => (c_YES,c_YES,c_NO,c_YES),
+               REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
+               REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
+               ADDRESS_MASK              => x"FFFF",
+               BROADCAST_BITMASK         => x"FF",
+               BROADCAST_SPECIAL_ADDR    => x"45",
+               REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+               REGIO_HARDWARE_VERSION    => x"9100b000",
+               REGIO_INIT_ADDRESS        => x"f356",
+               REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+               CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
+               TIMING_TRIGGER_RAW        => c_YES,
+               --Configure data handler
+               DATA_INTERFACE_NUMBER     => 1,
+               DATA_BUFFER_DEPTH         => 9,  --13
+               DATA_BUFFER_WIDTH         => 32,
+               DATA_BUFFER_FULL_THRESH   => 256,
+               TRG_RELEASE_AFTER_DATA    => c_YES,
+               HEADER_BUFFER_DEPTH       => 9,
+               HEADER_BUFFER_FULL_THRESH => 256
+      )
     port map(
-      CLK                => clk_raw_internal,
-      SYSCLK             => clk_sys_i,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
-      --Internal Connection
-      MED_DATA_IN        => med_data_out(15 downto 0),
-      MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-      MED_DATAREADY_IN   => med_dataready_out(0),
-      MED_READ_OUT       => med_read_in(0),
-      MED_DATA_OUT       => med_data_in(15 downto 0),
-      MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-      MED_DATAREADY_OUT  => med_dataready_in(0),
-      MED_READ_IN        => med_read_out(0),
-      REFCLK2CORE_OUT    => open,
-      CLK_RX_HALF_OUT    => rx_clock_half,
-      CLK_RX_FULL_OUT    => rx_clock_full,
-      
-      --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(2),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(3),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(2),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(3),
-      SD_REFCLK_P_IN     => '0',
-      SD_REFCLK_N_IN     => '0',
-      SD_PRSNT_N_IN      => FPGA5_COMM(0),
-      SD_LOS_IN          => FPGA5_COMM(0),
-      SD_TXDIS_OUT       => FPGA5_COMM(2),
-      
-      SCI_DATA_IN        => sci1_data_in,
-      SCI_DATA_OUT       => sci1_data_out,
-      SCI_ADDR           => sci1_addr,
-      SCI_READ           => sci1_read,
-      SCI_WRITE          => sci1_write,
-      SCI_ACK            => sci1_ack,        
-      -- Status and control port
-      STAT_OP            => med_stat_op(15 downto 0),
-      CTRL_OP            => med_ctrl_op(15 downto 0),
-      STAT_DEBUG         => med_stat_debug(63 downto 0),
-      CTRL_DEBUG         => (others => '0')
-      );
-
-
----------------------------------------------------------------------------
--- Hub 
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
-  generic map (
-    HUB_USED_CHANNELS  => (c_NO,c_NO,c_NO,c_YES),
-    IBUF_SECURE_MODE  => c_YES,
-    MII_NUMBER        => NUM_INTERFACES,
-    MII_IS_UPLINK     => (0 => 1, others => 0),
-    MII_IS_DOWNLINK   => (0 => 0, others => 1),
-    MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
-    INT_NUMBER        => 0,
-    USE_ONEWIRE       => c_YES,
-    COMPILE_TIME      => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
---    COMPILE_TIME      => VERSION_NUMBER_TIME, 
-    HARDWARE_VERSION  => x"91003200",
-    INIT_ENDPOINT_ID  => x"0003",
-    INIT_ADDRESS      => x"F356",
-    USE_VAR_ENDPOINT_ID => c_YES,
-    BROADCAST_SPECIAL_ADDR => x"45",
-    CLOCK_FREQUENCY   => CLOCK_FREQUENCY
-    )
-  port map (
-    CLK    => clk_sys_i,
-    RESET  => reset_i,
-    CLK_EN => '1',
-
-    --Media interfacces
-    MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0)   => med_dataready_out,
-    MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0)       => med_data_out,
-    MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0)  => med_packet_num_out,
-    MED_READ_IN(NUM_INTERFACES*1-1 downto 0)         => med_read_in,
-    MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0)    => med_dataready_in,
-    MED_DATA_IN(NUM_INTERFACES*16-1 downto 0)        => med_data_in,
-    MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0)   => med_packet_num_in,
-    MED_READ_OUT(NUM_INTERFACES*1-1 downto 0)        => med_read_out,
-    MED_STAT_OP(NUM_INTERFACES*16-1 downto 0)        => med_stat_op,
-    MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0)        => med_ctrl_op,
-
-    COMMON_STAT_REGS                => common_stat_reg,
-    COMMON_CTRL_REGS                => common_ctrl_reg,
-    MY_ADDRESS_OUT                  => open,
-    --REGIO INTERFACE
-    REGIO_ADDR_OUT                  => regio_addr_out,
-    REGIO_READ_ENABLE_OUT           => regio_read_enable_out,
-    REGIO_WRITE_ENABLE_OUT          => regio_write_enable_out,
-    REGIO_DATA_OUT                  => regio_data_out,
-    REGIO_DATA_IN                   => regio_data_in,
-    REGIO_DATAREADY_IN              => regio_dataready_in,
-    REGIO_NO_MORE_DATA_IN           => regio_no_more_data_in,
-    REGIO_WRITE_ACK_IN              => regio_write_ack_in,
-    REGIO_UNKNOWN_ADDR_IN           => regio_unknown_addr_in,
-    REGIO_TIMEOUT_OUT               => regio_timeout_out,
-    REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
-    REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-    ONEWIRE                         => TEMPSENS,
-    ONEWIRE_MONITOR_OUT             => open,
-    --Status ports (for debugging)
-    MPLEX_CTRL            => (others => '0'),
-    CTRL_DEBUG            => (others => '0'),
-    STAT_DEBUG            => open
-    );
-
-
+               CLK                => clk_sys_i,
+               RESET              => reset_i,
+               CLK_EN             => '1',
+               MED_DATAREADY_OUT  => med_dataready_out(0),
+               MED_DATA_OUT       => med_data_out,
+               MED_PACKET_NUM_OUT => med_packet_num_out,
+               MED_READ_IN        => med_read_in(0),
+               MED_DATAREADY_IN   => med_dataready_in(0),
+               MED_DATA_IN        => med_data_in,
+               MED_PACKET_NUM_IN  => med_packet_num_in,
+               MED_READ_OUT       => med_read_out(0),
+               MED_STAT_OP_IN     => med_stat_op,
+               MED_CTRL_OP_OUT    => med_ctrl_op,
+
+               --Timing trigger in
+               TRG_TIMING_TRG_RECEIVED_IN  => '0',
+               --LVL1 trigger to FEE
+               LVL1_TRG_DATA_VALID_OUT     => open,
+               LVL1_VALID_TIMING_TRG_OUT   => open,
+               LVL1_VALID_NOTIMING_TRG_OUT => open,
+               LVL1_INVALID_TRG_OUT        => open,
+
+               LVL1_TRG_TYPE_OUT        => open,
+               LVL1_TRG_NUMBER_OUT      => open,
+               LVL1_TRG_CODE_OUT        => open,
+               LVL1_TRG_INFORMATION_OUT => open,
+               LVL1_INT_TRG_NUMBER_OUT  => open,
+
+               --Information about trigger handler errors
+               TRG_MULTIPLE_TRG_OUT     => open,
+               TRG_TIMEOUT_DETECTED_OUT => open,
+               TRG_SPURIOUS_TRG_OUT     => open,
+               TRG_MISSING_TMG_TRG_OUT  => open,
+               TRG_SPIKE_DETECTED_OUT   => open,
+
+               --Response from FEE
+               FEE_TRG_RELEASE_IN(0)       => '1',
+               FEE_TRG_STATUSBITS_IN       => (others => '0'),
+               FEE_DATA_IN                 => (others => '0'),
+               FEE_DATA_WRITE_IN(0)        => '0',
+               FEE_DATA_FINISHED_IN(0)     => '1',
+               FEE_DATA_ALMOST_FULL_OUT(0) => open,
+
+               -- Slow Control Data Port
+               REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+               REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+               REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+               REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+               REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+               REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+               REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+               REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+               REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+               REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+               BUS_ADDR_OUT         => regio_addr_out,
+               BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+               BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+               BUS_DATA_OUT         => regio_data_out,
+               BUS_DATA_IN          => regio_data_in,
+               BUS_DATAREADY_IN     => regio_dataready_in,
+               BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+               BUS_WRITE_ACK_IN     => regio_write_ack_in,
+               BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+               BUS_TIMEOUT_OUT      => regio_timeout_out,
+               ONEWIRE_INOUT        => TEMPSENS,
+               ONEWIRE_MONITOR_OUT  => open,
+
+               TIME_GLOBAL_OUT         => global_time,
+               TIME_LOCAL_OUT          => local_time,
+               TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+               TIME_TICKS_OUT          => timer_ticks,
+
+               STAT_DEBUG_IPU              => open,
+               STAT_DEBUG_1                => open,
+               STAT_DEBUG_2                => open,
+               STAT_DEBUG_DATA_HANDLER_OUT => open,
+               STAT_DEBUG_IPU_HANDLER_OUT  => open,
+               STAT_TRIGGER_OUT            => open,
+               CTRL_MPLEX                  => (others => '0'),
+               IOBUF_CTRL_GEN              => (others => '0'),
+               STAT_ONEWIRE                => open,
+               STAT_ADDR_DEBUG             => open,
+               DEBUG_LVL1_HANDLER_OUT      => open
+               );
 
 ---------------------------------------------------------------------------
 -- Bus Handler
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       3 => 4,       others => 0)
+      PORT_NUMBER    => 3,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 4,       others => 0)
       )
     port map(
-      CLK   => clk_sys_i,
-      RESET => reset_i,
-
-      DAT_ADDR_IN                                      => regio_addr_out,
-      DAT_DATA_IN                                      => regio_data_out,
-      DAT_DATA_OUT                             => regio_data_in,
-      DAT_READ_ENABLE_IN               => regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN              => regio_write_enable_out,
-      DAT_TIMEOUT_IN                           => regio_timeout_out,
-      DAT_DATAREADY_OUT                        => regio_dataready_in,
-      DAT_WRITE_ACK_OUT                        => regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT             => regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT             => regio_unknown_addr_in,
-
-      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-      BUS_READ_ENABLE_OUT(1)              => sci1_read,
-      BUS_READ_ENABLE_OUT(2)              => sci2_read,
-      BUS_READ_ENABLE_OUT(3)              => soda_read,
-
-      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-      BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
-      BUS_WRITE_ENABLE_OUT(3)             => soda_write,
-      
+               CLK   => clk_sys_i,
+               RESET => reset_i,
+
+               DAT_ADDR_IN                                     => regio_addr_out,
+               DAT_DATA_IN                                     => regio_data_out,
+               DAT_DATA_OUT                            => regio_data_in,
+               DAT_READ_ENABLE_IN              => regio_read_enable_out,
+               DAT_WRITE_ENABLE_IN             => regio_write_enable_out,
+               DAT_TIMEOUT_IN                          => regio_timeout_out,
+               DAT_DATAREADY_OUT                       => regio_dataready_in,
+               DAT_WRITE_ACK_OUT                       => regio_write_ack_in,
+               DAT_NO_MORE_DATA_OUT            => regio_no_more_data_in,
+               DAT_UNKNOWN_ADDR_OUT            => regio_unknown_addr_in,
+
+               BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
+               BUS_READ_ENABLE_OUT(1)              => sci1_read,
+               BUS_READ_ENABLE_OUT(2)              => soda_read,
+
+               BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
+               BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
+               BUS_WRITE_ENABLE_OUT(2)             => soda_write,
+
                BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
-      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
-      BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
-      
+               BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
+               BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+               BUS_DATA_OUT(2*32+31 downto 2*32)   => soda_data_in,
+
                BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-      BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci2_addr,
-      BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-      BUS_ADDR_OUT(3*16+3 downto 3*16)         => soda_addr,
-      BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-      
+               BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+               BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
+               BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
+               BUS_ADDR_OUT(2*16+3 downto 2*16)        => soda_addr,
+               BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
+
                BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_TIMEOUT_OUT(2)                  => open,
-      BUS_TIMEOUT_OUT(3)                  => open,
-      
+               BUS_TIMEOUT_OUT(1)                  => open,
+               BUS_TIMEOUT_OUT(2)                  => open,
+
                BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-      BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-      BUS_DATA_IN(2*32+7 downto 2*32)     => sci2_data_out,
-      BUS_DATA_IN(3*32+31 downto 3*32)    => soda_data_out,
-      
+               BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
+               BUS_DATA_IN(1*32+31 downto 1*32+8)  => open,
+               BUS_DATA_IN(2*32+31 downto 2*32)    => soda_data_out,
+
                BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-      BUS_DATAREADY_IN(1)                 => sci1_ack,
-      BUS_DATAREADY_IN(2)                 => sci2_ack,
-      BUS_DATAREADY_IN(3)                 => soda_ack,
-      
+               BUS_DATAREADY_IN(1)                 => sci1_ack,
+               BUS_DATAREADY_IN(2)                 => soda_ack,
+
                BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-      BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(2)                 => sci2_ack,
-      BUS_WRITE_ACK_IN(3)                 => soda_ack,
-      
+               BUS_WRITE_ACK_IN(1)                 => sci1_ack,
+               BUS_WRITE_ACK_IN(2)                 => soda_ack,
+
                BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-      BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_NO_MORE_DATA_IN(2)              => '0',
-      BUS_NO_MORE_DATA_IN(3)              => '0',
-      
+               BUS_NO_MORE_DATA_IN(1)              => '0',
+               BUS_NO_MORE_DATA_IN(2)              => '0',
+
                BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,
-      BUS_UNKNOWN_ADDR_IN(3)              => '0',
+               BUS_UNKNOWN_ADDR_IN(1)              => '0',
+               BUS_UNKNOWN_ADDR_IN(2)              => '0',
 
                STAT_DEBUG => open
-      );
+               );
 
 ---------------------------------------------------------------------------
 -- SPI / Flash
@@ -512,7 +493,7 @@ THE_SPI_RELOAD :  spi_flash_and_fpga_reload --.flash_reboot_arch
 -- The synchronous interface for Soda tests
 ---------------------------------------------------------------------------      
 
-THE_SYNC_LINK : med_ecp3_sfp_sync
+THE_SYNC_LINK : med_ecp3_sfp_sync_up
   generic map(
     SERDES_NUM  => 0,    --number of serdes in quad
     IS_SYNC_SLAVE => c_YES
@@ -523,14 +504,14 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
     RESET              => reset_i,
     CLEAR              => clear_i,
     --Internal Connection for TrbNet data -> not used a.t.m.
-    MED_DATA_IN        => med_data_out(31 downto 16),
-    MED_PACKET_NUM_IN  => med_packet_num_out(5 downto 3),
-    MED_DATAREADY_IN   => med_dataready_out(1),
-    MED_READ_OUT       => med_read_in(1),
-    MED_DATA_OUT       => med_data_in(31 downto 16),
-    MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
-    MED_DATAREADY_OUT  => med_dataready_in(1),
-    MED_READ_IN        => med_read_out(1),
+    MED_DATA_IN        => med_data_out(15 downto 0),
+    MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
+    MED_DATAREADY_IN   => med_dataready_out(0),
+    MED_READ_OUT       => med_read_in(0),
+    MED_DATA_OUT       => med_data_in(15 downto 0),
+    MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+    MED_DATAREADY_OUT  => med_dataready_in(0),
+    MED_READ_IN        => med_read_out(0),
     CLK_RX_HALF_OUT    => soda_rx_clock_half,
     CLK_RX_FULL_OUT    => soda_rx_clock_full,
     
@@ -549,16 +530,16 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
     SD_LOS_IN          => SFP_LOS(1),
     SD_TXDIS_OUT       => SFP_TXDIS(1),
     
-    SCI_DATA_IN        => sci2_data_in,
-    SCI_DATA_OUT       => sci2_data_out,
-    SCI_ADDR           => sci2_addr,
-    SCI_READ           => sci2_read,
-    SCI_WRITE          => sci2_write,
-    SCI_ACK            => sci2_ack,  
-    SCI_NACK           => sci2_nack,
+    SCI_DATA_IN        => sci1_data_in,
+    SCI_DATA_OUT       => sci1_data_out,
+    SCI_ADDR           => sci1_addr,
+    SCI_READ           => sci1_read,
+    SCI_WRITE          => sci1_write,
+    SCI_ACK            => sci1_ack,  
+    SCI_NACK           => sci1_nack,
     -- Status and control port
-    STAT_OP            => med_stat_op(31 downto 16),
-    CTRL_OP            => med_ctrl_op(31 downto 16),
+    STAT_OP            => med_stat_op(15 downto 0),
+    CTRL_OP            => med_ctrl_op(15 downto 0),
     STAT_DEBUG         => open,
     CTRL_DEBUG         => (others => '0')
    );      
@@ -607,7 +588,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
 ---------------------------------------------------------------------------
 -- DEBUG\r
 ---------------------------------------------------------------------------    
-       link_debug_in_S(31 downto 16)   <= med_stat_op(31 downto 16);
+       link_debug_in_S(31 downto 16)   <= med_stat_op(15 downto 0);
        link_debug_in_S(15 downto 0)    <= (3 => pll_lock, others => '0');
 ---------------------------------------------------------------------------
 -- Test Circuits
@@ -618,7 +599,12 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
                time_counter <= time_counter + 1;
        end process;
 
-
+       process(clk_soda_i) 
+       begin
+               if rising_edge(clk_soda_i) then
+                       soda_counter_i <= soda_counter_i+1;
+               end if;
+       end process;
 
 
 end trb3_periph_sodaclient_arch;

diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd
index 32ca6428d30a7ebd3be55dd97dba63d14be5509c..3a91b430ad8b13a70f05539ff7c281e2dfece28c 100644 (file)
--- a/source/trb3_periph_sodasource.vhd
+++ b/source/trb3_periph_sodasource.vhd
@@ -515,7 +515,7 @@ THE_SPI_RELOAD :  spi_flash_and_fpga_reload --.flash_reboot_arch
 -- The synchronous interface for Soda tests
 ---------------------------------------------------------------------------      
 
-THE_SYNC_LINK : med_ecp3_sfp_sync
+THE_SYNC_LINK : med_ecp3_sfp_sync_down
   generic map(
     SERDES_NUM  => 0,    --number of serdes in quad
     IS_SYNC_SLAVE => c_NO
@@ -573,7 +573,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
 
 THE_SOB_SOURCE : soda_start_of_burst_faker
        port map(
-               SYSCLK                                          => clk_sys_i,
+               SYSCLK                                          => clk_raw_internal,
                RESET                                                   => reset_i,
                SODA_BURST_PULSE_OUT            => SOB_S
        );
@@ -583,6 +583,7 @@ THE_SOB_SOURCE : soda_start_of_burst_faker
 THE_SODA_SOURCE : soda_source
        port map(
                SYSCLK                                  => clk_sys_i,
+               SODACLK                                 => clk_raw_internal,
                RESET                                           => reset_i,
                CLEAR                                           => clear_i,
                CLK_EN                                  => '1',