Adding hopefully reasonable input to TDC

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index 833e57a8bdab8aa3780655346be9a9d0513301a1..0e3df7dbeeb2e4eca2fb16514935d24127b8441c 100644 (file)
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -26,7 +26,9 @@ entity adc_handler is
     BUS_RX           : in  CTRLBUS_RX;
     BUS_TX           : out CTRLBUS_TX;
 
-    ADCSPI_CTRL      : out std_logic_vector(7 downto 0)
+    ADCSPI_CTRL      : out std_logic_vector(7 downto 0);
+    
+    ADC_CLK_TDC_OUT  : out std_logic
   );
 end entity;
 
@@ -385,7 +387,8 @@ begin
           DEBUG_BUFFER_DATA     => buffer_data(i),
           DEBUG_BUFFER_READY    => buffer_ready(i),
           READOUT_RX            => READOUT_RX,
-          READOUT_TX            => READOUT_TX(i)
+          READOUT_TX            => READOUT_TX(i),
+          ADC_CLK_TDC_OUT       => ADC_CLK_TDC_OUT
         );
     end generate;
 

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index 6556d8047caff7c21537c1e1fa73d932a3d890e6..91219e51a44f2aeec70b87794b41d29fe6f99096 100644 (file)
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -26,7 +26,9 @@ entity adc_processor_cfd is
     DEBUG_BUFFER_READY : out std_logic;
 
     READOUT_RX         : in  READOUT_RX;
-    READOUT_TX         : out READOUT_TX
+    READOUT_TX         : out READOUT_TX;
+    
+    ADC_CLK_TDC_OUT    : out std_logic
   );
 end entity adc_processor_cfd;
 
@@ -79,6 +81,9 @@ begin
   debug_sys <= debug_adc when rising_edge(CLK_SYS);
   busy_in_adc <= busy_in_sys when rising_edge(CLK_ADC);
   busy_out_sys <= busy_out_adc when rising_edge(CLK_SYS);
+  
+  ADC_CLK_TDC_OUT <= debug_adc(5).EpochCounter(10);
+  
   gen_cfd : for i in 0 to CHANNELS - 1 generate
     trigger_gen(i) <= debug_sys(i).Trigger;
         

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index f618e8d1285a9ae44f7541093d900064281b347e..1c558231f72f78339981987b1acbf6fc9be3f59b 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -428,7 +428,9 @@ gen_reallogic : if READOUT_MODE /= READOUT_MODE_DUMMY generate
       BUS_RX      => busadc_rx,
       BUS_TX      => busadc_tx,
       
-      ADCSPI_CTRL => adcspi_ctrl
+      ADCSPI_CTRL => adcspi_ctrl,
+      
+      ADC_CLK_TDC_OUT => tdc_inputs(0)
       );    
 end generate;