add settings for trigger window and max ToT

diff --git a/code/HitBuffer.vhd b/code/HitBuffer.vhd
index 8a5e66db8fb4a7de6694822a36b53ff044e652b8..8984abff4e3e83e4e00ea50df61267ced9d3b558 100644 (file)
--- a/code/HitBuffer.vhd
+++ b/code/HitBuffer.vhd
@@ -19,6 +19,7 @@ entity HitBuffer is
     THROWAWAY_TIME : in std_logic_vector(8 downto 0);
     READOUT_ACTIVE : in std_logic;
     SPIKE_SETTING  : in unsigned(3 downto 0);
+    MAXTOT_SETTING : in unsigned(7 downto 0);
     
     DATA_OUT   : out std_logic_vector(27 downto 0);
     DATA_VALID : out std_logic;
@@ -57,7 +58,8 @@ signal hit_buffer_reset                  : std_logic;
 signal hit_buffer_dout  : std_logic_vector(35 downto 0);
 signal hit_buffer_level : std_logic_vector(5 downto 0);
 
-signal spike_timer : unsigned(3 downto 0) := (others => '0');
+signal spike_timer  : unsigned(3 downto 0) := (others => '0');
+signal maxtot_timer : unsigned(7 downto 0) := (others => '0');
 signal hit_store : std_logic_vector(35 downto 0);
 alias hit_store_coarse  : std_logic_vector(8 downto 0) is hit_store(25 downto 17);
 
@@ -107,14 +109,20 @@ PROC_BUILD_HIT : process begin
   if spike_timer /= x"0" then
     spike_timer <= spike_timer - 1;
   end if;  
+  if maxtot_timer /= x"00" then
+    maxtot_timer <= maxtot_timer - 1;
+  else   
+    edge_rising_valid <= '0';
+  end if;  
   
   
   if cdc_valid = '1' and cdc_data(5) = '1' then
-    edge_rising <= '1' & cdc_data(4) & '0' & cdc_data(14 downto 6) & cdc_data(3 downto 0);
-    spike_timer <= SPIKE_SETTING;
+    edge_rising  <= '1' & cdc_data(4) & '0' & cdc_data(14 downto 6) & cdc_data(3 downto 0);
+    spike_timer  <= SPIKE_SETTING;
+    maxtot_timer <= MAXTOT_SETTING;
   end if;  
     
-  if cdc_valid = '1' and cdc_data(5) = '0' then
+  if cdc_valid = '1' and cdc_data(5) = '0' and edge_rising_valid = '1' then
     full_hit <= x"00" & cdc_data_error & edge_rising_error & edge_rising(12 downto 0) & cdc_data(14 downto 6) & cdc_data(3 downto 0);
     edge_rising_valid <= '0';
     if READOUT_ACTIVE = '0' and spike_timer = x"0" then
@@ -195,11 +203,11 @@ PROC_BUF : process begin
           buffer_state <= WAIT_READOUT;
         end if;
       else  
-        if READOUT_ACTIVE = '0' then
+        --if READOUT_ACTIVE = '0' then
           buffer_state <= GOT_HIT;
-        else
-          buffer_state <= DO_READOUT;
-        end if;  
+        --else
+          --buffer_state <= DO_READOUT;
+        --end if;  
       end if;  
       
     when WAIT_HIT2 =>

diff --git a/code/ReadoutHandler.vhd b/code/ReadoutHandler.vhd
index 64dc4a017db28867d48fd6ec64976fefb75bf05b..48b0c988e2f5ae276f78b5836514435415bcbe36 100644 (file)
--- a/code/ReadoutHandler.vhd
+++ b/code/ReadoutHandler.vhd
@@ -24,6 +24,7 @@ entity ReadoutHandler is
     DATA_READ_OUT : out std_logic_vector(NUM_CHANNELS-1 downto 0); 
     READOUT_ACTIVE: out std_logic; 
     CALIB_PULSE   : out std_logic;
+    TRIGGER_WINDOW: in  std_logic_vector(7 downto 0); 
 --     BUS_RX    : in CTRLBUS_RX;
 --     BUS_TX    : out CTRLBUS_TX;
     
@@ -79,21 +80,20 @@ PROC_RDO_SYSTEM : process begin
   READOUT_TX.data_write    <= '0';
   collect_start_sys        <= '0';
   got_collect_finish       <= '0';
-  last_cdc_empty <= cdc_empty;
+  last_cdc_empty           <= cdc_empty;
   CALIB_PULSE              <= '0';
   
   case state_rdo is
     when IDLE =>
       buf_READOUT_ACTIVE <= '0';
+      timer              <= (others => '0');
       if READOUT_RX.valid_timing_trg = '1' then
-        state_rdo         <= COLLECT;
-        collect_start_sys <= '1';
+        state_rdo         <= WAIT_WINDOW;
         is_calib_sys      <= '0';
-        buf_READOUT_ACTIVE    <= '1';
+        timer             <= TRIGGER_WINDOW;
       elsif READOUT_RX.valid_notiming_trg = '1' then
         state_rdo         <= CALIB;
         is_calib_sys      <= '1';
-        timer             <= (others => '0');
       elsif READOUT_RX.invalid_trg = '1' then
         state_rdo <= FINISH;
       end if;  
@@ -102,14 +102,19 @@ PROC_RDO_SYSTEM : process begin
       timer <= timer + 1;
       if timer >= x"05" and timer <= x"09" then
         CALIB_PULSE <= '1';
-      elsif timer = x"F0" then
+      elsif timer = x"64" then
         state_rdo <= COLLECT;
-        buf_READOUT_ACTIVE    <= '1';       
-        collect_start_sys <= '1';        
+        buf_READOUT_ACTIVE  <= '1';       
+        collect_start_sys   <= '1';        
       end if;
       
     when WAIT_WINDOW =>
-      null;
+      timer <= timer - 1;
+      if timer = 0 then
+        collect_start_sys  <= '1';
+        buf_READOUT_ACTIVE <= '1';
+        state_rdo          <= COLLECT;
+      end if;
       
     when COLLECT =>
       READOUT_TX.data       <= cdc_data_out(31 downto 0);

diff --git a/code/TDC_FF.vhd b/code/TDC_FF.vhd
index f1bc77dc455b7f7fc7a3b8361f5cef1b91248e9b..8171c748fa9be60d584ff9cfbda33c169df2ae1f 100644 (file)
--- a/code/TDC_FF.vhd
+++ b/code/TDC_FF.vhd
@@ -52,10 +52,14 @@ type status_t is array(0 to 31) of std_logic_vector(95 downto 0);
 signal hitbuffer_status : status_t;
 
 signal CONF_enable : std_logic_vector(31 downto 0) := (others => '1');
-signal CONF_configure : std_logic_vector(31 downto 0) := x"00000300";
+signal CONF_configure : std_logic_vector(31 downto 0) := x"64139301";
 alias CONF_externalcalibration : std_logic is CONF_configure(0);
 alias CONF_SPIKE               : std_logic_vector(3 downto 0) is CONF_configure(11 downto 8);
-alias CONF_window              : std_logic_vector(8 downto 0) is CONF_configure(24 downto 16);
+alias CONF_window              : std_logic_vector(8 downto 0) is CONF_configure(20 downto 12);
+alias CONF_windowafter         : std_logic_vector(7 downto 0) is CONF_configure(31 downto 24);
+
+signal CONF_configure2         : std_logic_vector(31 downto 0) := x"0000004d";
+alias CONF_maxTot              : std_logic_vector(7 downto 0) is CONF_configure2(7 downto 0);
 
 signal status_rdo_handler : std_logic_vector(63 downto 0);
 begin
@@ -126,7 +130,8 @@ gen_CHANNELS : for i in 0 to NUM_CHANNELS-1 generate
       COARSE_TIME_IN => std_logic_vector(coarse_time),
       THROWAWAY_TIME => std_logic_vector(throwaway_time),
       READOUT_ACTIVE => readout_active_i(i/16),
-      SPIKE_SETTING => unsigned(CONF_SPIKE),
+      SPIKE_SETTING  => unsigned(CONF_SPIKE),
+      MAXTOT_SETTING => unsigned(CONF_maxTot),
       
       DATA_OUT       => tdc_data(i),
       DATA_VALID     => tdc_data_valid(i),
@@ -149,14 +154,15 @@ THE_RDO_HANDLER_1 : entity work.ReadoutHandler
     CLK_SYS    => CLK_SYS,
     RESET_IN   => RESET_IN,
     
-    REFERENCE_IN => ref_timestamp,
+    REFERENCE_IN   => ref_timestamp,
     
-    DATA_IN       => tdc_data(15 downto 0),
-    DATA_VALID_IN => tdc_data_valid(15 downto 0),
-    DATA_EMPTY_IN => tdc_data_empty(15 downto 0),
-    DATA_READ_OUT => tdc_data_read(15 downto 0),
+    DATA_IN        => tdc_data(15 downto 0),
+    DATA_VALID_IN  => tdc_data_valid(15 downto 0),
+    DATA_EMPTY_IN  => tdc_data_empty(15 downto 0),
+    DATA_READ_OUT  => tdc_data_read(15 downto 0),
     READOUT_ACTIVE => readout_active_i(0),
-    CALIB_PULSE   => calibration_pulse(0),    
+    CALIB_PULSE    => calibration_pulse(0),
+    TRIGGER_WINDOW => CONF_windowafter,
     
     READOUT_RX  => READOUT_RX,
     READOUT_TX  => READOUT_TX(0),
@@ -173,14 +179,15 @@ THE_RDO_HANDLER_2 : entity work.ReadoutHandler
     CLK_SYS    => CLK_SYS,
     RESET_IN   => RESET_IN,
     
-    REFERENCE_IN => ref_timestamp,
+    REFERENCE_IN   => ref_timestamp,
     
-    DATA_IN       => tdc_data(31 downto 16),
-    DATA_VALID_IN => tdc_data_valid(31 downto 16),
-    DATA_EMPTY_IN => tdc_data_empty(31 downto 16),
-    DATA_READ_OUT => tdc_data_read(31 downto 16),
+    DATA_IN        => tdc_data(31 downto 16),
+    DATA_VALID_IN  => tdc_data_valid(31 downto 16),
+    DATA_EMPTY_IN  => tdc_data_empty(31 downto 16),
+    DATA_READ_OUT  => tdc_data_read(31 downto 16),
     READOUT_ACTIVE => readout_active_i(1),
-    CALIB_PULSE   => calibration_pulse(1),    
+    CALIB_PULSE    => calibration_pulse(1),    
+    TRIGGER_WINDOW => CONF_windowafter,
     
     READOUT_RX  => READOUT_RX,
     READOUT_TX  => READOUT_TX(1),
@@ -210,6 +217,8 @@ begin
       CONF_enable <= BUS_RX.data;
    elsif BUS_RX.addr = x"0001" then
       CONF_configure <= BUS_RX.data;
+   elsif BUS_RX.addr = x"0002" then
+      CONF_configure2 <= BUS_RX.data;
     else
       BUS_TX.ack  <= '0';   
       BUS_TX.unknown <= '1';
@@ -220,6 +229,8 @@ begin
       BUS_TX.data <= CONF_enable;
     elsif BUS_RX.addr = x"0001" then
       BUS_TX.data <= CONF_configure;
+    elsif BUS_RX.addr = x"0002" then
+      BUS_TX.data <= CONF_configure2;
     elsif BUS_RX.addr = x"0010" then
       BUS_TX.data <= status_rdo_handler(31 downto 0);
     elsif BUS_RX.addr = x"0011" then