signal pll_adc_sampling_clk_o : std_logic;
signal pll_adc_sampling_clk_lock : std_logic;
- signal pll_adc_sampling_clk_reset : std_logic;
-- PLL ADC Monitor
signal pll_adc_not_lock : std_logic;
signal adc_debug_type : std_logic_vector(3 downto 0);
-- Merge Data Streams
+ signal merge_handler_reset_i : std_logic;
+ signal merge_handler_reset : std_logic;
signal data_frame : std_logic_vector(43 downto 0);
signal data_frame_clk : std_logic;
signal merge_timeout_ctr : unsigned(3 downto 0);
signal R_STATE : R_STATES;
signal frame_rates_reset : std_logic;
- signal sampling_clk_reset : std_logic;
+ signal pll_adc_sampling_clk_reset : std_logic;
signal adc_reset_handler : std_logic;
signal adc_reset_p : std_logic;
signal output_handler_reset : std_logic;
DEBUG_OUT(8) <= reset_for_offline;
DEBUG_OUT(9) <= fifo_reset_handler;
DEBUG_OUT(10) <= reset_handler_busy;
- DEBUG_OUT(11) <= sampling_clk_reset;
+ DEBUG_OUT(11) <= pll_adc_sampling_clk_reset;
DEBUG_OUT(15 downto 12) <= debug_state;
when "010" =>
DEBUG_OUT(8) <= error_adc0;
DEBUG_OUT(9) <= adc_frame_rate_error;
DEBUG_OUT(10) <= fifo_reset_handler;
- DEBUG_OUT(11) <= sampling_clk_reset;
+ DEBUG_OUT(11) <= pll_adc_sampling_clk_reset;
DEBUG_OUT(12) <= adc_reset_handler;
DEBUG_OUT(13) <= output_handler_reset;
DEBUG_OUT(14) <= frame_rate_error;
std_logic_vector(13 + pll_adc_sample_clk_dphase_r);
pll_adc_sample_clk_finedelb <=
std_logic_vector(8 + pll_adc_sample_clk_finedelb_r);
-
- pll_adc_sampling_clk_reset <= sampling_clk_reset;
end if;
end process PROC_PLL_PHASE_SETUP;
-----------------------------------------------------------------------------
-- Merge Data Streams Timestamps and ADC Value
-----------------------------------------------------------------------------
-
+ merge_handler_reset_i <=
+ output_handler_reset when rising_edge(NX_TIMESTAMP_CLK_IN);
+ merge_handler_reset <=
+ merge_handler_reset_i when rising_edge(NX_TIMESTAMP_CLK_IN);
+
PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if (RESET_NX_TIMESTAMP_CLK_IN = '1' or output_handler_reset = '1') then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1' or merge_handler_reset = '1') then
merge_timeout_ctr <= (others => '0');
merge_timeout_error <= '0';
merge_error_ctr <= (others => '0');
if( RESET_IN = '1' ) then
frame_rates_reset <= '0';
fifo_reset_handler <= '0';
- sampling_clk_reset <= '0';
+ pll_adc_sampling_clk_reset <= '0';
adc_reset_p <= '0';
adc_reset_handler <= '0';
output_handler_reset <= '0';
else
frame_rates_reset <= '0';
fifo_reset_handler <= '0';
- sampling_clk_reset <= '0';
+ pll_adc_sampling_clk_reset <= '0';
adc_reset_p <= '0';
adc_reset_handler <= '0';
output_handler_reset <= '0';
when R_RESET_TIMESTAMP =>
-- must reset/resync Timestamp clock and data trnasmission clock
-- of nxyter first, afterwards wait a bit to let settle down
- reset_handler_counter <= reset_handler_counter + 1;
- nx_timestamp_reset_o <= '1';
- rs_wait_timer_start <= '1'; -- wait 1mue to settle
- R_STATE <= R_WAIT_0;
- debug_state <= x"1";
+ reset_handler_counter <= reset_handler_counter + 1;
+ nx_timestamp_reset_o <= '1';
+ rs_wait_timer_start <= '1'; -- wait 1mue to settle
+ R_STATE <= R_WAIT_0;
+ debug_state <= x"1";
when R_WAIT_0 =>
if (rs_wait_timer_done = '0') then
- R_STATE <= R_WAIT_0;
+ R_STATE <= R_WAIT_0;
else
- R_STATE <= R_SET_ALL_RESETS;
+ R_STATE <= R_SET_ALL_RESETS;
end if;
- debug_state <= x"2";
+ debug_state <= x"2";
when R_SET_ALL_RESETS =>
-- timer reset should be finished, can we check status,To be done?
-- now set reset of all handlers
- frame_rates_reset <= '1';
- sampling_clk_reset <= '1';
- adc_reset_p <= '1';
- adc_reset_handler <= '1';
- output_handler_reset <= '1';
- fifo_reset_handler <= '1';
+ frame_rates_reset <= '1';
+ pll_adc_sampling_clk_reset <= '1';
+ adc_reset_p <= '1';
+ adc_reset_handler <= '1';
+ output_handler_reset <= '1';
+ fifo_reset_handler <= '1';
-- give resets 1mue to take effect
- rs_wait_timer_start <= '1';
- R_STATE <= R_WAIT_1;
- debug_state <= x"3";
+ rs_wait_timer_start <= '1';
+ R_STATE <= R_WAIT_1;
+ debug_state <= x"3";
when R_WAIT_1 =>
- sampling_clk_reset <= '1';
- adc_reset_handler <= '1';
- output_handler_reset <= '1';
- fifo_reset_handler <= '1';
+ pll_adc_sampling_clk_reset <= '1';
+ adc_reset_handler <= '1';
+ output_handler_reset <= '1';
+ fifo_reset_handler <= '1';
if (rs_wait_timer_done = '0') then
- R_STATE <= R_WAIT_1;
+ R_STATE <= R_WAIT_1;
else
-- now start timeout timer and begin to release resets
-- step by step
if (nx_frame_rate_offline = '0' and
nx_frame_rate_error = '0') then
-- Next: Release PLL Reset, i.e. sampling_clk_reset
- adc_reset_handler <= '1';
- output_handler_reset <= '1';
- fifo_reset_handler <= '1';
- R_STATE <= R_PLL_WAIT_LOCK;
+ adc_reset_handler <= '1';
+ output_handler_reset <= '1';
+ fifo_reset_handler <= '1';
+ R_STATE <= R_PLL_WAIT_LOCK;
else
- sampling_clk_reset <= '1';
- adc_reset_handler <= '1';
- output_handler_reset <= '1';
- fifo_reset_handler <= '1';
- R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
+ pll_adc_sampling_clk_reset <= '1';
+ adc_reset_handler <= '1';
+ output_handler_reset <= '1';
+ fifo_reset_handler <= '1';
+ R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
end if;
debug_state <= x"5";
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
-
- -- Give status info to the TRB Slow Control Channel
- PROC_SLAVE_BUS: process(CLK_IN)
+ PROC_SLAVE_BUS_BUFFER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
fifo_full_r <= fifo_full;
adc_notlock_ctr_r <= adc_notlock_ctr;
merge_error_ctr_r <= merge_error_ctr;
nx_frame_synced_r <= nx_frame_synced;
-
+ end if;
+ end process PROC_SLAVE_BUS_BUFFER;
+
+ -- Give status info to the TRB Slow Control Channel
+ PROC_SLAVE_BUS: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
+
reset_resync_ctr <= '0';
reset_parity_error_ctr <= '0';
- debug_mode <= (others => '0');
johnson_counter_sync_r <= "00";
pll_adc_sample_clk_dphase_r <= x"d";
pll_adc_sample_clk_finedelb_r <= (others => '0');
reset_handler_start_r <= '0';
adc_bit_shift <= x"0";
adc_debug_type <= (others => '0');
- fifo_full_r <= '0';
- fifo_empty_r <= '0';
+ debug_mode <= (others => '0');
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"001c" =>
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '1';
-
when x"001e" =>
slv_data_out_o(2 downto 0) <= debug_mode;
slv_data_out_o(31 downto 3) <= (others => '0');
-- Rate Calculation
signal nx_trigger_ctr_t : unsigned(27 downto 0);
+ signal nx_trigger_ctr_t_nr : unsigned(31 downto 0);
signal nx_frame_ctr_t : unsigned(27 downto 0);
signal nx_pileup_ctr_t : unsigned(27 downto 0);
signal nx_overflow_ctr_t : unsigned(27 downto 0);
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
nx_trigger_ctr_t <= (others => '0');
+ nx_trigger_ctr_t_nr <= (others => '0');
nx_frame_ctr_t <= (others => '0');
nx_rate_timer <= (others => '0');
nx_hit_rate <= (others => '0');
if (nx_rate_timer < x"5f5e100") then
if (trigger_rate_inc = '1') then
nx_trigger_ctr_t <= nx_trigger_ctr_t + 1;
+ nx_trigger_ctr_t_nr <= nx_trigger_ctr_t_nr + 1;
end if;
if (frame_rate_inc = '1') then
nx_frame_ctr_t <= nx_frame_ctr_t + 1;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
slv_ack_o <= '1';
-
+
+ when x"0010" =>
+ slv_data_out_o <= nx_trigger_ctr_t_nr;
+ slv_ack_o <= '1';
+ slv_ack_o <= '1';
+
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
+
-- Debug Line
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
signal accepted_trigger_rate : unsigned(27 downto 0);
signal testpulse_rate : unsigned(27 downto 0);
signal invalid_t_trigger_ctr_clear : std_logic;
-
+ signal bypass_ctr_trigger : std_logic;
+
-- Reset
signal RESET_NX_MAIN_CLK_IN : std_logic;
STATE <= S_WAIT_TRG_DATA_VALID;
elsif (LVL1_VALID_TIMING_TRG_IN = '1') then
- if (NXYTER_OFFLINE_IN = '0') then
+ if (NXYTER_OFFLINE_IN = '1' or bypass_ctr_trigger = '1') then
+ -- Ignore Trigger for nxyter is or pretends to be offline
+ TRIGGER_TYPE <= T_IGNORE;
+ STATE <= S_WAIT_TRG_DATA_VALID;
+ else
-- Normal Trigger
TRIGGER_TYPE <= T_TIMING;
STATE <= S_CTS_TRIGGER;
- else
- -- Ignore Trigger for nxyter is offline
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_WAIT_TRG_DATA_VALID;
end if;
- elsif (INTERNAL_TRIGGER_IN = '1') then
- -- Internal Trigger, not defined yet
- TRIGGER_TYPE <= T_INTERNAL;
- STATE <= S_INTERNAL_TRIGGER;
else
trigger_busy_o <= '0';
TRIGGER_TYPE <= T_UNDEF;
reg_testpulse_length <= x"064";
reg_testpulse_enable <= '0';
invalid_t_trigger_ctr_clear <= '1';
+ bypass_ctr_trigger <= '0';
else
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
when x"0003" =>
invalid_t_trigger_ctr_clear <= '1';
slv_ack_o <= '1';
+
+ when x"0006" =>
+ bypass_ctr_trigger <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
std_logic_vector(accepted_trigger_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0005" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(testpulse_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
+
+ when x"0006" =>
+ slv_data_out_o(0) <= bypass_ctr_trigger;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
FEE_TRG_RELEASE_OUT <= fee_trg_release_o;
FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;
- NX_TESTPULSE_OUT <= testpulse_o;
+ NX_TESTPULSE_OUT <= testpulse_o or INTERNAL_TRIGGER_IN;
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
signal validation_busy : std_logic_vector(1 downto 0);
-- Rate Calculations
+ signal data_rate_ctr_nr : unsigned(31 downto 0);
signal data_rate_ctr : unsigned(27 downto 0);
signal data_rate : unsigned(27 downto 0);
signal rate_timer_ctr : unsigned(27 downto 0);
begin
if (rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
+ data_rate_ctr_nr <= (others => '0');
data_rate_ctr <= (others => '0');
data_rate <= (others => '0');
rate_timer_ctr <= (others => '0');
if (d_data_clk_o = '1') then
data_rate_ctr <= data_rate_ctr + 1;
+ data_rate_ctr_nr <= data_rate_ctr_nr + 1;
end if;
else
rate_timer_ctr <= (others => '0');
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
+ --when x"001e" =>
+ -- slv_data_out_o(15 downto 0) <=
+ -- std_logic_vector(out_of_window_h_ctr_r);
+ -- slv_data_out_o(31 downto 16) <= (others => '0');
+ -- slv_ack_o <= '1';
+
when x"001e" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(out_of_window_h_ctr_r);
- slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
when x"001f" =>
- slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate);
+ slv_data_out_o <=
+ std_logic_vector(data_rate_ctr_nr);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
FEE_DATA_WRITE_0_IN => fee_data_write_o_0,
FEE_DATA_1_IN => fee_data_o_1,
FEE_DATA_WRITE_1_IN => fee_data_write_o_1,
- INTERNAL_TRIGGER_IN => '0', --internal_trigger,
+ INTERNAL_TRIGGER_IN => internal_trigger,
TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy,
TRIGGER_BUSY_0_IN => trigger_evt_busy_0,
# Relax some of the timing constraints
#################################################################
-BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*";
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_status_*/nx_ts_reset_o" 100 ns;
+#BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*";
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_sync_o*" 10 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns;
-MULTICYCLE TO CELL "*/timestamp_sync_o*" 10 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY/*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/output_handler_reset*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_r*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_rnx_*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/sampling_clk_reset*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_bit_shift*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_r*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_clk_ok" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns;
+
#SPI Interface
REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
jspc29 / trb3.git / commitdiff