--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant FPGA_SIZE : string := "85KUM";
+-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+-- -- 0: single edge only,
+-- -- 1: same channel,
+-- -- 2: alternating channels,
+-- -- 3: same channel with stretcher
+-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+-- -- mode: 0, 1, 2, 3, 7
+-- -- size: 32, 64, 96, 128, dyn
+-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+-- -- 0: Single fine time as the sum of the two transitions
+-- -- 1: Double fine time, individual transitions
+-- -- 13: Debug - fine time + (if 0x3ff full chain)
+-- -- 14: Debug - single fine time and the ROM addresses for the two transitions
+-- -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+ constant USE_GBE : integer := c_YES;
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F586";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86";
+
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_ADC : integer := c_YES;
+ constant INCLUDE_I2C : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_STATISTICS : integer := c_NO;
+ constant TRIG_GEN_INPUT_NUM : integer := 16;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 16;
+
+
+
+ constant GEN_BUSY_OUTPUT : integer := c_NO;
+
+ constant TRIGGER_COIN_COUNT : integer := 0;
+ constant TRIGGER_PULSER_COUNT : integer := 2;
+ constant TRIGGER_RAND_PULSER : integer := 0;
+ constant TRIGGER_ADDON_COUNT : integer := 1;
+ constant PERIPH_TRIGGER_COUNT : integer := 0;
+ constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter
+ constant CTS_OUTPUT_MULTIPLEXERS : integer := 0;
+--TODO:
+-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
+--Which external trigger module (ETM) to use?
+ constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO;
+ type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B);
+ constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
+ constant ETM_ID : std_logic_vector(7 downto 0);
+
+ constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+ type hub_ct is array(0 to 16) of integer;
+ type intlist_t is array(0 to 7) of integer;
+
+
+ constant INTERFACE_NUM : integer := 1;
+ constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+ constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+ constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+
+ constant cts_rdo_additional_ports : integer := 1; --for internal endpoint
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000100";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+ constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+
+
+ function etm_id_func return std_logic_vector is
+ variable res : unsigned(7 downto 0);
+ begin
+ res := x"00";
+ if INCLUDE_ETM=c_YES then
+ res := x"60";
+ res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4);
+ end if;
+ return std_logic_vector(res);
+ end function;
+
+ constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func;
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+-- t(15) := '1'; --TDC
+-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+ t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1));
+ t(28 downto 28) := std_logic_vector(to_unsigned(0,1));
+
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_mimosis"
+set_option -resource_sharing false
+set_option -vhdl2008 true
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_mimosis.edf"
+set_option log_file "workdir/trb5sc_mimosis.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
+
+#channel 1, SFP
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
+##########################################
+
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
+#Hub
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd"
+
+
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v"
+# Choose your SerDes location here
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd"
+
+
+add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd"
+
+add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd"
+add_file -vhdl -lib work "../mimosis/cores/testout.vhd"
+add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd"
+add_file -vhdl -lib work "../mimosis/code/InputStage.vhd"
+add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd"
+add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd"
+
+
+
+add_file -vhdl -lib work "./trb5sc_mimosis.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+-- use work.med_sync_define.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.trb_net_gbe_components.all;\r
+use work.cts_pkg.all;\r
+\r
+\r
+entity trb5sc_mimosis is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+\r
+ --HDMI AddOn\r
+ LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
+\r
+ RJ : inout std_logic_vector(3 downto 0);\r
+ H1 : inout std_logic_vector(4 downto 0);\r
+ H2 : inout std_logic_vector(4 downto 0);\r
+ H3 : inout std_logic_vector(3 downto 0);\r
+ H4 : inout std_logic_vector(4 downto 0);\r
+ H5 : inout std_logic_vector(3 downto 0);\r
+ H6 : inout std_logic_vector(4 downto 0);\r
+ H7 : inout std_logic_vector(4 downto 0);\r
+\r
+ PIN : out std_logic_vector(8 downto 1);\r
+\r
+ MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
+\r
+\r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+\r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only\r
+ );\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+end entity;\r
+\r
+architecture arch of trb5sc_mimosis is\r
+\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc : std_logic;\r
+ signal clk_40, clk_80, clk_160, clk_320 : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal external_clock_lock : std_logic := '0';\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+ signal reboot_from_gbe : std_logic;\r
+ signal reset_via_gbe : std_logic;\r
+\r
+\r
+\r
+ signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+ signal rdack, wrack : std_logic;\r
+\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0);\r
+ alias led_off : std_logic is add_reg(0);\r
+\r
+ signal gbe_status : std_logic_vector(15 downto 0);\r
+\r
+ signal clk_350, clk_50, clk_200bypass : std_logic;\r
+\r
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);\r
+ signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);\r
+ signal trigger_busy_i : std_logic;\r
+ signal cts_trigger_out : std_logic;\r
+\r
+ signal gbe_cts_number : std_logic_vector(15 downto 0);\r
+ signal gbe_cts_code : std_logic_vector(7 downto 0);\r
+ signal gbe_cts_information : std_logic_vector(7 downto 0);\r
+ signal gbe_cts_start_readout : std_logic;\r
+ signal gbe_cts_readout_type : std_logic_vector(3 downto 0);\r
+ signal gbe_cts_readout_finished : std_logic;\r
+ signal gbe_cts_status_bits : std_logic_vector(31 downto 0);\r
+ signal gbe_fee_data : std_logic_vector(15 downto 0);\r
+ signal gbe_fee_dataready : std_logic;\r
+ signal gbe_fee_read : std_logic;\r
+ signal gbe_fee_status_bits : std_logic_vector(31 downto 0);\r
+ signal gbe_fee_busy : std_logic;\r
+\r
+ signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);\r
+ signal gsc_init_read, gsc_reply_read : std_logic;\r
+ signal gsc_init_dataready, gsc_reply_dataready : std_logic;\r
+ signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);\r
+ signal gsc_busy : std_logic;\r
+\r
+ signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal cts_rdo_data : std_logic_vector(31 downto 0);\r
+ signal cts_rdo_write : std_logic;\r
+ signal cts_rdo_finished : std_logic;\r
+\r
+ -- signal cts_ext_trigger : std_logic;\r
+ -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0');\r
+ -- signal cts_ext_control : std_logic_vector(31 downto 0);\r
+ -- signal cts_ext_debug : std_logic_vector(31 downto 0);\r
+ -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00";\r
+\r
+ signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0);\r
+ signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0');\r
+ signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1');\r
+ signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0');\r
+\r
+ signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1);\r
+ signal cts_rdo_rx : READOUT_RX;\r
+\r
+\r
+ signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0);\r
+ signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0);\r
+\r
+\r
+ signal cts_trg_send : std_logic;\r
+ signal cts_trg_type : std_logic_vector(3 downto 0);\r
+ signal cts_trg_number : std_logic_vector(15 downto 0);\r
+ signal cts_trg_information : std_logic_vector(23 downto 0);\r
+ signal cts_trg_code : std_logic_vector(7 downto 0);\r
+ signal cts_trg_status_bits : std_logic_vector(31 downto 0);\r
+ signal cts_trg_busy : std_logic;\r
+\r
+ signal cts_ipu_send : std_logic;\r
+ signal cts_ipu_type : std_logic_vector(3 downto 0);\r
+ signal cts_ipu_number : std_logic_vector(15 downto 0);\r
+ signal cts_ipu_information : std_logic_vector(7 downto 0);\r
+ signal cts_ipu_code : std_logic_vector(7 downto 0);\r
+ signal cts_ipu_status_bits : std_logic_vector(31 downto 0);\r
+ signal cts_ipu_busy : std_logic;\r
+\r
+ signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic;\r
+\r
+ \r
+ signal inp_i : std_logic_vector( 7 downto 0);\r
+\r
+ signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
+ signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ signal counter : unsigned(23 downto 0);\r
+\r
+begin\r
+\r
+ -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => make_reset,--med2int(0).stat_op(13),\r
+ SEND_RESET_IN => '0', --med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+ \r
+\r
+ THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40,\r
+ CLKOS3=> clk_80\r
+ );\r
+\r
+ H3(3) <= clk_320;\r
+\r
+ -- For IPHC Proxy\r
+ -- RJ(0) <= clk_40;\r
+ -- For IKF Proxy\r
+ H1(4) <= clk_40;\r
+\r
+ \r
+ proc_make_reset : process begin\r
+ wait until rising_edge(clk_sys);\r
+ if(reset_via_gbe = '1') then\r
+ reset_via_gbe_long <= '1';\r
+ reset_via_gbe_timer <= '1';\r
+ end if;\r
+ if timer.tick_us = '1' then\r
+ reset_via_gbe_timer <= '0';\r
+ reset_via_gbe_long <= reset_via_gbe_timer;\r
+ end if;\r
+ last_reset_via_gbe_long <= reset_via_gbe_long;\r
+ make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long;\r
+ end process; \r
+ \r
+---------------------------------------------------------------------------\r
+-- GbE\r
+---------------------------------------------------------------------------\r
+ GBE : entity work.gbe_wrapper\r
+ generic map(\r
+ DO_SIMULATION => 0,\r
+ INCLUDE_DEBUG => 0,\r
+ USE_INTERNAL_TRBNET_DUMMY => 0,\r
+ USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+ RX_PATH_ENABLE => 1,\r
+ FIXED_SIZE_MODE => 1,\r
+ INCREMENTAL_MODE => 1,\r
+ FIXED_SIZE => 100,\r
+ FIXED_DELAY_MODE => 1,\r
+ UP_DOWN_MODE => 0,\r
+ UP_DOWN_LIMIT => 100,\r
+ FIXED_DELAY => 100,\r
+\r
+ NUMBER_OF_GBE_LINKS => 1,\r
+ LINKS_ACTIVE => "0001",\r
+\r
+ LINK_HAS_READOUT => "0001",\r
+ LINK_HAS_SLOWCTRL => "0001",\r
+ LINK_HAS_DHCP => "0001",\r
+ LINK_HAS_ARP => "0001",\r
+ LINK_HAS_PING => "0001",\r
+ LINK_HAS_FWD => "0000"\r
+ )\r
+\r
+ port map(\r
+ CLK_SYS_IN => clk_sys,\r
+ CLK_125_IN => CLK_125,\r
+ RESET => reset_i,\r
+ GSR_N => GSR_N,\r
+\r
+ TRIGGER_IN => cts_rdo_rx.data_valid,\r
+\r
+ SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
+ SD_LOS_IN(0) => SFP_LOS,\r
+ SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
+\r
+ CTS_NUMBER_IN => gbe_cts_number,\r
+ CTS_CODE_IN => gbe_cts_code,\r
+ CTS_INFORMATION_IN => gbe_cts_information,\r
+ CTS_READOUT_TYPE_IN => gbe_cts_readout_type,\r
+ CTS_START_READOUT_IN => gbe_cts_start_readout,\r
+ CTS_DATA_OUT => open,\r
+ CTS_DATAREADY_OUT => open,\r
+ CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,\r
+ CTS_READ_IN => '1',\r
+ CTS_LENGTH_OUT => open,\r
+ CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,\r
+\r
+ FEE_DATA_IN => gbe_fee_data,\r
+ FEE_DATAREADY_IN => gbe_fee_dataready,\r
+ FEE_READ_OUT => gbe_fee_read,\r
+ FEE_STATUS_BITS_IN => gbe_fee_status_bits,\r
+ FEE_BUSY_IN => gbe_fee_busy,\r
+\r
+ MC_UNIQUE_ID_IN => timer.uid,\r
+ MY_TRBNET_ADDRESS_IN => timer.network_address,\r
+ ISSUE_REBOOT_OUT => reboot_from_gbe,\r
+\r
+ GSC_CLK_IN => clk_sys,\r
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,\r
+ GSC_INIT_DATA_OUT => gsc_init_data,\r
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,\r
+ GSC_INIT_READ_IN => gsc_init_read,\r
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,\r
+ GSC_REPLY_DATA_IN => gsc_reply_data,\r
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,\r
+ GSC_REPLY_READ_OUT => gsc_reply_read,\r
+ GSC_BUSY_IN => gsc_busy,\r
+\r
+ BUS_IP_RX => busgbeip_rx,\r
+ BUS_IP_TX => busgbeip_tx,\r
+ BUS_REG_RX => busgbereg_rx,\r
+ BUS_REG_TX => busgbereg_tx,\r
+\r
+ MAKE_RESET_OUT => reset_via_gbe,\r
+ STATUS_OUT => gbe_status, --open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Hub\r
+---------------------------------------------------------------------------\r
+ THE_HUB : trb_net16_hub_streaming_port_sctrl_cts\r
+ generic map(\r
+ INIT_ADDRESS => INIT_ADDRESS,\r
+ MII_NUMBER => INTERFACE_NUM,\r
+ MII_IS_UPLINK => IS_UPLINK,\r
+ MII_IS_DOWNLINK => IS_DOWNLINK,\r
+ MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,\r
+ HARDWARE_VERSION => HARDWARE_INFO,\r
+ INCLUDED_FEATURES => INCLUDED_FEATURES,\r
+ INIT_ENDPOINT_ID => x"0001",\r
+ BROADCAST_BITMASK => x"7E",\r
+ CLOCK_FREQUENCY => 100,\r
+ USE_ONEWIRE => c_I2C,\r
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,\r
+ RDO_ADDITIONAL_PORT => cts_rdo_additional_ports,\r
+ RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ RDO_HEADER_BUFFER_DEPTH => 9,\r
+ RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16\r
+ )\r
+ port map (\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_EN => '1',\r
+ \r
+ -- Media interfacces ---------------------------------------------------------------\r
+ MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open,\r
+ MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open,\r
+ MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open,\r
+ MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'),\r
+ MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'),\r
+ MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'),\r
+ MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'),\r
+ MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open,\r
+ MED_STAT_OP(2 downto 0) => ERROR_NC,\r
+ MED_STAT_OP(INTERFACE_NUM*16-1 downto 3) => (others => '0'),\r
+ MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => open,\r
+ \r
+ -- Gbe Read-out Path ---------------------------------------------------------------\r
+ --Event information coming from CTS for GbE\r
+ GBE_CTS_NUMBER_OUT => gbe_cts_number,\r
+ GBE_CTS_CODE_OUT => gbe_cts_code,\r
+ GBE_CTS_INFORMATION_OUT => gbe_cts_information,\r
+ GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,\r
+ GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout,\r
+ --Information sent to CTS\r
+ GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,\r
+ GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits,\r
+ -- Data from Frontends\r
+ GBE_FEE_DATA_OUT => gbe_fee_data,\r
+ GBE_FEE_DATAREADY_OUT => gbe_fee_dataready,\r
+ GBE_FEE_READ_IN => gbe_fee_read,\r
+ GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits,\r
+ GBE_FEE_BUSY_OUT => gbe_fee_busy,\r
+ \r
+ -- CTS Request Sending -------------------------------------------------------------\r
+ --LVL1 trigger\r
+ CTS_TRG_SEND_IN => cts_trg_send,\r
+ CTS_TRG_TYPE_IN => cts_trg_type,\r
+ CTS_TRG_NUMBER_IN => cts_trg_number,\r
+ CTS_TRG_INFORMATION_IN => cts_trg_information,\r
+ CTS_TRG_RND_CODE_IN => cts_trg_code,\r
+ CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits,\r
+ CTS_TRG_BUSY_OUT => cts_trg_busy,\r
+ --IPU Channel\r
+ CTS_IPU_SEND_IN => cts_ipu_send,\r
+ CTS_IPU_TYPE_IN => cts_ipu_type,\r
+ CTS_IPU_NUMBER_IN => cts_ipu_number,\r
+ CTS_IPU_INFORMATION_IN => cts_ipu_information,\r
+ CTS_IPU_RND_CODE_IN => cts_ipu_code,\r
+ -- Receiver port\r
+ CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits,\r
+ CTS_IPU_BUSY_OUT => cts_ipu_busy,\r
+ \r
+ -- CTS Data Readout ----------------------------------------------------------------\r
+ --Trigger to CTS out\r
+ RDO_TRIGGER_IN => cts_trigger_out,\r
+ RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid,\r
+ RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg,\r
+ RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg,\r
+ RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg,\r
+ RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type,\r
+ RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code,\r
+ RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information,\r
+ RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number,\r
+ \r
+ --Data from CTS in\r
+ RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts,\r
+ RDO_DATA_IN => cts_rdo_data,\r
+ RDO_DATA_WRITE_IN => cts_rdo_write,\r
+ RDO_DATA_FINISHED_IN => cts_rdo_finished,\r
+ --Data from additional modules\r
+ RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional,\r
+ RDO_ADDITIONAL_DATA => cts_rdo_additional_data,\r
+ RDO_ADDITIONAL_WRITE => cts_rdo_additional_write,\r
+ RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished,\r
+ \r
+ -- Slow Control --------------------------------------------------------------------\r
+ COMMON_STAT_REGS => open,\r
+ COMMON_CTRL_REGS => common_ctrl_reg,\r
+ ONEWIRE => open,\r
+ ONEWIRE_MONITOR_IN => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ MY_ADDRESS_OUT => timer.network_address,\r
+ UNIQUE_ID_OUT => timer.uid,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ TIMER_TICKS_OUT(0) => timer.tick_us,\r
+ TIMER_TICKS_OUT(1) => timer.tick_ms,\r
+ TEMPERATURE_OUT => timer.temperature,\r
+ EXTERNAL_SEND_RESET => reset_via_gbe,\r
+ \r
+ REGIO_ADDR_OUT => ctrlbus_rx.addr,\r
+ REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,\r
+ REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,\r
+ REGIO_DATA_OUT => ctrlbus_rx.data,\r
+ REGIO_DATA_IN => ctrlbus_tx.data,\r
+ REGIO_DATAREADY_IN => rdack,\r
+ REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,\r
+ REGIO_WRITE_ACK_IN => wrack,\r
+ REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,\r
+ REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,\r
+ \r
+ --Gbe Sctrl Input\r
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,\r
+ GSC_INIT_DATA_IN => gsc_init_data,\r
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,\r
+ GSC_INIT_READ_OUT => gsc_init_read,\r
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,\r
+ GSC_REPLY_DATA_OUT => gsc_reply_data,\r
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,\r
+ GSC_REPLY_READ_IN => gsc_reply_read,\r
+ GSC_BUSY_OUT => gsc_busy,\r
+ \r
+ --status and control ports\r
+ HUB_STAT_CHANNEL => open,\r
+ HUB_STAT_GEN => open,\r
+ MPLEX_CTRL => (others => '0'),\r
+ MPLEX_STAT => open,\r
+ STAT_REGS => open,\r
+ STAT_CTRL_REGS => open,\r
+ \r
+ --Fixed status and control ports\r
+ STAT_DEBUG => open,\r
+ CTRL_DEBUG => (others => '0')\r
+ );\r
+ \r
+ \r
+ gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate\r
+ cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data;\r
+ cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits;\r
+ \r
+ cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write;\r
+ cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished;\r
+ \r
+ end generate;\r
+ \r
+ \r
+ rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;\r
+ wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;\r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- CTS\r
+---------------------------------------------------------------------------\r
+ THE_CTS : CTS\r
+ generic map (\r
+ EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic\r
+ PLATTFORM => 5, --TRB5sc\r
+ OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,\r
+ ADDON_GROUPS => 1,\r
+ ADDON_GROUP_UPPER => (0, others => 0)\r
+ )\r
+ port map (\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ \r
+ TRIGGER_BUSY_OUT => trigger_busy_i,\r
+ TIME_REFERENCE_OUT => cts_trigger_out,\r
+ \r
+ ADDON_TRIGGERS_IN => cts_addon_triggers_in,\r
+ ADDON_GROUP_ACTIVITY_OUT => open,\r
+ ADDON_GROUP_SELECTED_OUT => open,\r
+ \r
+ EXT_TRIGGER_IN => '0',\r
+ EXT_STATUS_IN => (others => '0'),\r
+ EXT_CONTROL_OUT => open,\r
+ EXT_HEADER_BITS_IN => (others => '0'),\r
+ EXT_FORCE_TRIGGER_INFO_IN => (others => '0'),\r
+ \r
+ PERIPH_TRIGGER_IN => (others => '0'),\r
+ \r
+ OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out,\r
+ \r
+ CTS_TRG_SEND_OUT => cts_trg_send,\r
+ CTS_TRG_TYPE_OUT => cts_trg_type,\r
+ CTS_TRG_NUMBER_OUT => cts_trg_number,\r
+ CTS_TRG_INFORMATION_OUT => cts_trg_information,\r
+ CTS_TRG_RND_CODE_OUT => cts_trg_code,\r
+ CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits,\r
+ CTS_TRG_BUSY_IN => cts_trg_busy,\r
+ \r
+ CTS_IPU_SEND_OUT => cts_ipu_send,\r
+ CTS_IPU_TYPE_OUT => cts_ipu_type,\r
+ CTS_IPU_NUMBER_OUT => cts_ipu_number,\r
+ CTS_IPU_INFORMATION_OUT => cts_ipu_information,\r
+ CTS_IPU_RND_CODE_OUT => cts_ipu_code,\r
+ CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits,\r
+ CTS_IPU_BUSY_IN => cts_ipu_busy,\r
+ \r
+ CTS_REGIO_ADDR_IN => buscts_rx.addr,\r
+ CTS_REGIO_DATA_IN => buscts_rx.data,\r
+ CTS_REGIO_READ_ENABLE_IN => buscts_rx.read,\r
+ CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write,\r
+ CTS_REGIO_DATA_OUT => buscts_tx.data,\r
+ CTS_REGIO_DATAREADY_OUT => buscts_tx.rack,\r
+ CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack,\r
+ CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown,\r
+ \r
+ LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid,\r
+ LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg,\r
+ LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg,\r
+ LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg,\r
+ \r
+ FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts,\r
+ FEE_DATA_OUT => cts_rdo_data,\r
+ FEE_DATA_WRITE_OUT => cts_rdo_write,\r
+ FEE_DATA_FINISHED_OUT => cts_rdo_finished\r
+ );\r
+ \r
+ -- cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16);\r
+ -- cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i;\r
+ \r
+ buscts_tx.nack <= '0';\r
+ buscts_tx.ack <= '0';\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 7,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ \r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+ \r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ -- BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(1) => buscts_rx,\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => busmimosis_rx,\r
+ BUS_RX(4) => busgbeip_rx,\r
+ BUS_RX(5) => busgbereg_rx,\r
+ BUS_RX(6) => busi2c_rx,\r
+ \r
+ BUS_TX(0) => bustools_tx,\r
+ -- BUS_TX(1) => bussci_tx,\r
+ BUS_TX(1) => buscts_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => busmimosis_tx,\r
+ BUS_TX(4) => busgbeip_tx,\r
+ BUS_TX(5) => busgbereg_tx,\r
+ BUS_TX(6) => busi2c_tx,\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ generic map(\r
+ ADC_CMD_1 => x"2c3cb",\r
+ ADC_CMD_2 => x"1d5cb",\r
+ ADC_CMD_3 => x"1e3cb",\r
+ ADC_CMD_4 => x"2f5cb",\r
+ ADC_CMD_T => x"1F393",\r
+ NUM_COINCIDENCES => 4,\r
+ NUM_MULTIPLICITIES => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe,\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ --HEADER_IO => open,\r
+ -- HEADER_IO(7) => HDR_IO(6),\r
+ -- HEADER_IO(8) => HDR_IO(7),\r
+ ADDITIONAL_REG => add_reg,\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor\r
+ MONITOR_INPUTS(11 downto 0) => x"000",\r
+ MONITOR_INPUTS(15 downto 12) => x"0",\r
+ TRIG_GEN_INPUTS(11 downto 0) => x"000",\r
+ TRIG_GEN_INPUTS(15 downto 12) => x"0",\r
+\r
+ TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i,\r
+\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+ PIN(5) <= '0' when (add_reg(30) = '0') else 'Z';\r
+\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- I2C\r
+---------------------------------------------------------------------------\r
+ THE_I2C : entity work.i2c_slim2\r
+ port map(\r
+ CLOCK => clk_40,\r
+ RESET => reset_i,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => i2c_go,\r
+ ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
+ WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ DIRECT_IN => i2c_reg_1(4), -- don't send command\r
+ I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
+ I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
+ I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
+ STATUS_OUT => i2c_reg_4(23 downto 16),\r
+ VALID_OUT => i2c_reg_4(31),\r
+ I2C_BUSY_OUT => i2c_reg_4(30),\r
+ I2C_DONE_OUT => i2c_reg_4(29),\r
+ -- I2C connections\r
+ SDA_IN => PIN(4),\r
+ SDA_OUT => mimosis_sda_drv,\r
+ SCL_IN => PIN(3),\r
+ SCL_OUT => mimosis_scl_drv,\r
+ -- Debug\r
+ BSM_OUT => i2c_reg_4(27 downto 24)\r
+ );\r
+\r
+-- I2C signal open collector driver\r
+-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+ PIN(4) <= MIMOSIS_SDA;\r
+ PIN(3) <= MIMOSIS_SCL;\r
+ MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+ MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+ H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
+ PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
+ PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
+\r
+ PROC_I2C_REGS : process\r
+ begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '0';\r
+ busi2c_tx.nack <= '0';\r
+ busi2c_tx.data <= (others => '0');\r
+ i2c_go_100 <= '0';\r
+\r
+ if busi2c_rx.write = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ i2c_reg_0 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ i2c_reg_1 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ i2c_reg_2 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ i2c_go_100 <= busi2c_rx.data(0);\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ i2c_reg_5 <= busi2c_rx.data;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+ end if;\r
+ elsif busi2c_rx.read = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ busi2c_tx.data <= i2c_reg_0;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ busi2c_tx.data <= i2c_reg_1;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ busi2c_tx.data <= i2c_reg_2;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ busi2c_tx.data <= (others => '0');\r
+ elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
+ busi2c_tx.data <= i2c_reg_4;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ busi2c_tx.data <= i2c_reg_5;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ THE_I2C_GO_SYNC : pulse_sync\r
+ port map(\r
+ CLK_A_IN => clk_sys,\r
+ RESET_A_IN => reset_i,\r
+ PULSE_A_IN => i2c_go_100,\r
+ CLK_B_IN => clk_40,\r
+ RESET_B_IN => reset_i,\r
+ PULSE_B_OUT => i2c_go\r
+ );\r
+\r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
+ generic map(\r
+ WIDTH => 32,\r
+ DEPTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_40,\r
+ D_IN => i2c_reg_5,\r
+ D_OUT => i2c_reg_5_40\r
+ );\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ THE_MIMOSIS : entity work.MimosisInput\r
+ port map(\r
+ CLK => clk_160,\r
+ CLK_SYS => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ INPUT => inp_i,\r
+\r
+ BUSRDO_RX => cts_rdo_rx,\r
+ BUSRDO_TX => cts_rdo_additional(0),\r
+\r
+ BUS_RX => busmimosis_rx,\r
+ BUS_TX => busmimosis_tx\r
+ );\r
+\r
+-- inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
+ inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0);\r
+ \r
+ \r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+ LED_SFP_GREEN <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0';\r
+ LED_SFP_YELLOW <= gbe_status(8);\r
+ LED_SFP_RED <= not (gbe_status(3) or gbe_status(4)); --'0';\r
+\r
+ -- LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ -- LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"FF";\r
+ LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
+ LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
+ LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
+ LED_RJ_RED(0) <= '1'; --on if backplane is used (next to SFP)\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
+\r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i; --for v1 boards\r
+\r
+ FLASH_NCS <= flash_ncs_i;\r
+\r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+-- cts_rdo_additional(0).data_finished <= '1';\r
+-- cts_rdo_additional(0).data_write <= '0';\r
+-- cts_rdo_additional(0).busy_release <= '1';\r
+ \r
+ \r
+end architecture;\r
jspc29 / trb5sc.git / commitdiff