\r
\r
\r
-\r
--- component trb_net16_gbe_buf is\r
--- generic(\r
--- DO_SIMULATION : integer range 0 to 1 := 1;\r
--- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
--- );\r
--- port(\r
--- CLK : in std_logic;\r
--- TEST_CLK : in std_logic; -- only for simulation!\r
--- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
--- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
--- RESET : in std_logic;\r
--- GSR_N : in std_logic;\r
--- -- Debug\r
--- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
--- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
--- -- configuration interface\r
--- IP_CFG_START_IN : in std_logic;\r
--- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
--- IP_CFG_DONE_OUT : out std_logic;\r
--- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
--- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
--- IP_CFG_MEM_CLK_OUT : out std_logic;\r
--- MR_RESET_IN : in std_logic;\r
--- MR_MODE_IN : in std_logic;\r
--- MR_RESTART_IN : in std_logic;\r
--- -- gk 29.03.10\r
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
--- SLV_READ_IN : in std_logic;\r
--- SLV_WRITE_IN : in std_logic;\r
--- SLV_BUSY_OUT : out std_logic;\r
--- SLV_ACK_OUT : out std_logic;\r
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
--- -- gk 22.04.10\r
--- -- registers setup interface\r
--- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
--- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
--- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
--- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
--- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
--- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
--- -- gk 23.04.10\r
--- LED_PACKET_SENT_OUT : out std_logic;\r
--- LED_AN_DONE_N_OUT : out std_logic;\r
--- -- CTS interface\r
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
--- CTS_START_READOUT_IN : in std_logic;\r
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
--- CTS_DATAREADY_OUT : out std_logic;\r
--- CTS_READOUT_FINISHED_OUT : out std_logic;\r
--- CTS_READ_IN : in std_logic;\r
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
--- -- Data payload interface\r
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
--- FEE_DATAREADY_IN : in std_logic;\r
--- FEE_READ_OUT : out std_logic;\r
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
--- FEE_BUSY_IN : in std_logic;\r
--- --SFP Connection\r
--- SFP_RXD_P_IN : in std_logic;\r
--- SFP_RXD_N_IN : in std_logic;\r
--- SFP_TXD_P_OUT : out std_logic;\r
--- SFP_TXD_N_OUT : out std_logic;\r
--- SFP_REFCLK_P_IN : in std_logic;\r
--- SFP_REFCLK_N_IN : in std_logic;\r
--- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
--- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
--- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
--- -- debug ports\r
--- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
--- );\r
--- end component;\r
-\r
-\r
+ component adc_ltc2308_readout is\r
+ generic(\r
+ CLOCK_FREQUENCY : integer := 100 --MHz\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ ADC_SCK : out std_logic;\r
+ ADC_SDI : out std_logic;\r
+ ADC_SDO : in std_logic;\r
+ ADC_CONVST : out std_logic;\r
+ \r
+ DAT_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ DAT_READ_EN_IN : in std_logic;\r
+ DAT_WRITE_EN_IN : in std_logic;\r
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DAT_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_DATAREADY_OUT : out std_logic;\r
+ DAT_NO_MORE_DATA_OUT : out std_logic;\r
+ DAT_WRITE_ACK_OUT : out std_logic;\r
+ DAT_UNKNOWN_ADDR_OUT : out std_logic;\r
+ DAT_TIMEOUT_IN : in std_logic;\r
+ \r
+ STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_addresses is\r
+ generic(\r
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ RAM_DATA_IN : in std_logic_vector(15 downto 0);\r
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ RAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
+ RAM_WR_IN : in std_logic;\r
+ API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ ADDRESS_REJECTED : out std_logic;\r
+ DONT_UNDERSTAND_OUT : out std_logic;\r
+ API_SEND_OUT : out std_logic;\r
+ ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_api_base is\r
+ generic (\r
+ API_TYPE : integer range 0 to 1 := c_API_PASSIVE;\r
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; --std_FIFO_DEPTH;\r
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; --std_FIFO_DEPTH;\r
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES;\r
+ APL_WRITE_ALL_WORDS : integer range 0 to 1 := c_NO;\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"\r
+ );\r
+ \r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ -- APL Transmitter port\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic;\r
+ APL_READ_OUT : out std_logic;\r
+ APL_SHORT_TRANSFER_IN : in std_logic;\r
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+ APL_SEND_IN : in std_logic;\r
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- the target (only for active APIs)\r
+ -- Receiver port\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic;\r
+ APL_READ_IN : in std_logic;\r
+ -- APL Control port\r
+ APL_RUN_OUT : out std_logic;\r
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);\r
+ APL_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0);\r
+ -- Internal direction port\r
+ -- the ports with master or slave in their name are to be mapped by the active api\r
+ -- to the init respectivly the reply path and vice versa in the passive api.\r
+ -- lets define: the "master" path is the path that I send data on.\r
+ -- master_data_out and slave_data_in are only used in active API for termination\r
+ INT_MASTER_DATAREADY_OUT : out std_logic;\r
+ INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_IN : in std_logic;\r
+ INT_MASTER_DATAREADY_IN : in std_logic;\r
+ INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_OUT : out std_logic;\r
+ INT_SLAVE_DATAREADY_OUT : out std_logic;\r
+ INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_IN : in std_logic;\r
+ INT_SLAVE_DATAREADY_IN : in std_logic;\r
+ INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ CTRL_SEQNR_RESET : in std_logic;\r
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);\r
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_api_ipu_streaming is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ -- Internal direction port\r
+ \r
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_INIT_DATAREADY_OUT : out std_logic;\r
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_INIT_READ_IN : in std_logic;\r
+ \r
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_REPLY_DATAREADY_IN : in std_logic;\r
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_REPLY_READ_OUT : out std_logic;\r
+ \r
+ CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_INIT_DATAREADY_IN : in std_logic;\r
+ CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_INIT_READ_OUT : out std_logic;\r
+ \r
+ CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_REPLY_DATAREADY_OUT : out std_logic;\r
+ CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_REPLY_READ_IN : in std_logic;\r
+ \r
+ --Event information coming from CTS\r
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ CTS_START_READOUT_OUT : out std_logic;\r
+ \r
+ --Information sent to CTS\r
+ --status data, equipped with DHDR\r
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);\r
+ CTS_DATAREADY_IN : in std_logic;\r
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM\r
+ CTS_READ_OUT : out std_logic;\r
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+ \r
+ -- Data from Frontends\r
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);\r
+ FEE_DATAREADY_OUT : out std_logic;\r
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready\r
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ FEE_BUSY_OUT : out std_logic;\r
+ \r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ CTRL_SEQNR_RESET : in std_logic\r
+ \r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net16_api_ipu_streaming_internal is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ -- Internal direction port\r
+ \r
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_INIT_DATAREADY_OUT : out std_logic;\r
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_INIT_READ_IN : in std_logic;\r
+ \r
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_REPLY_DATAREADY_IN : in std_logic;\r
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_REPLY_READ_OUT : out std_logic;\r
+ \r
+ --Event information coming from CTS\r
+ CTS_SEND_IN : in std_logic;\r
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --valid while start_readout is high\r
+ CTS_CODE_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --valid while start_readout is high\r
+ \r
+ CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ CTS_BUSY_OUT : out std_logic; --goes high after CTS_SEND_IN, goes low after GBE_READOUT_FINISHED_IN\r
+ \r
+ --connection to GbE\r
+ GBE_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high\r
+ GBE_CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ GBE_CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ GBE_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high\r
+ GBE_CTS_START_READOUT_OUT : out std_logic;\r
+ \r
+ GBE_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle\r
+ GBE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high\r
+ \r
+ GBE_FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE\r
+ GBE_FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid\r
+ GBE_FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready\r
+ GBE_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again\r
+ GBE_FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE\r
+ --has been read.\r
+ \r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ CTRL_SEQNR_RESET : in std_logic\r
+ \r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net_bridge_pcie_apl is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES)\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ --TrbNet connect\r
+ APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (3*4-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0);\r
+ \r
+ --Internal Data Bus\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ \r
+ EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ --DMA interface\r
+ \r
+ --Debug\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net_bridge_pcie_endpoint is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES)\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ \r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ \r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ \r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ \r
+ MED_ERROR_IN : in std_logic_vector(2 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ STAT : out std_logic_vector(31 downto 0);\r
+ STAT_ENDP : out std_logic_vector(31 downto 0);\r
+ STAT_API1 : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net_bridge_pcie_endpoint_hub is\r
+ generic(\r
+ NUM_LINKS : integer range 1 to 4 := 2;\r
+ COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ RESET_TRBNET : in std_logic;\r
+ CLK : in std_logic;\r
+ CLK_125_IN : in std_logic;\r
+ \r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ \r
+ SPI_CLK_OUT : out std_logic;\r
+ SPI_D_OUT : out std_logic;\r
+ SPI_D_IN : in std_logic;\r
+ SPI_CE_OUT : out std_logic;\r
+ \r
+ MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+ \r
+ MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+ \r
+ MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ \r
+ REQUESTOR_ID_IN : in std_logic_vector(15 downto 0);\r
+ TX_ST_OUT : out std_logic; --tx first word\r
+ TX_END_OUT : out std_logic; --tx last word\r
+ TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit\r
+ TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out\r
+ TX_REQ_OUT : out std_logic; --tx request out\r
+ TX_RDY_IN : in std_logic; --tx arbiter can read\r
+ TX_VAL_IN : in std_logic; --tx data is valid\r
+ TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write\r
+ TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words\r
+ TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read\r
+ \r
+ RX_CR_CPLH_OUT : out std_logic;\r
+ RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0);\r
+ UNEXP_CMPL_OUT : out std_logic;\r
+ RX_ST_IN : in std_logic;\r
+ RX_END_IN : in std_logic;\r
+ RX_DWEN_IN : in std_logic;\r
+ RX_DATA_IN : in std_logic_vector(63 downto 0);\r
+ \r
+ PROGRMN_OUT : out std_logic;\r
+ SEND_RESET_OUT : out std_logic;\r
+ MAKE_RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ component trb_net_CRC is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ CRC_OUT : out std_logic_vector(15 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net_CRC8 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(7 downto 0);\r
+ CRC_OUT : out std_logic_vector(7 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ component ddr_off is\r
+ port (\r
+ Clk : in std_logic;\r
+ Data : in std_logic_vector(1 downto 0);\r
+ Q : out std_logic_vector(0 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ component dll_in100_out100 is\r
+ port (\r
+ clk : in std_logic;\r
+ aluhold : in std_logic;\r
+ clkop : out std_logic;\r
+ clkos : out std_logic;\r
+ lock : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component dll_in200_out100 is\r
+ port (\r
+ clk : in std_logic;\r
+ aluhold : in std_logic;\r
+ clkop : out std_logic;\r
+ clkos : out std_logic;\r
+ lock : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net16_dummy_fifo is\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
+ READ_ENABLE_IN : in std_logic;\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_endpoint_hades_full is\r
+ generic (\r
+ USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES);\r
+ IBUF_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1);\r
+ IBUF_SECURE_MODE : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ API_SECURE_MODE_TO_APL : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ API_SECURE_MODE_TO_INT : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+ \r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+ \r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+ \r
+ -- LVL1 trigger APL\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received\r
+ \r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+ \r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ \r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+ \r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+ TRG_LONG_TRG_OUT : out std_logic;\r
+ --Data Port\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT : out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+ \r
+ \r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ --IDRAM is used if no 1-wire interface, onewire used otherwise\r
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
+ REGIO_IDRAM_WR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+ \r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ MED_STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net16_endpoint_hades_full_handler is\r
+ generic (\r
+ IBUF_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8\r
+ );\r
+ \r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+ \r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+ \r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic;\r
+ --LVL1 trigger to FEE\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+ \r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+ \r
+ --Response from FEE\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ \r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+ \r
+ --Slow Control Port\r
+ --common registers\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ --user defined registers\r
+ REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');\r
+ REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
+ REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --internal data port\r
+ BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ BUS_READ_ENABLE_OUT : out std_logic;\r
+ BUS_WRITE_ENABLE_OUT : out std_logic;\r
+ BUS_TIMEOUT_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ BUS_DATAREADY_IN : in std_logic := '0';\r
+ BUS_WRITE_ACK_IN : in std_logic := '0';\r
+ BUS_NO_MORE_DATA_IN : in std_logic := '0';\r
+ BUS_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ --Onewire\r
+ ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ ONEWIRE_MONITOR_OUT : out std_logic;\r
+ --Config endpoint id, if not statically assigned\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');\r
+ \r
+ --Timing registers\r
+ TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds\r
+ TIME_LOCAL_OUT : out std_logic_vector (7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger\r
+ TIME_TICKS_OUT : out std_logic_vector (1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ \r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ component trb_net16_endpoint_hades_cts is\r
+ generic(\r
+ USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES);\r
+ IBUF_DEPTH : channel_config_t := (1, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (1, 1, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 6, 6, 6);\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ \r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ \r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+ \r
+ --LVL1 trigger\r
+ TRG_SEND_IN : in std_logic;\r
+ TRG_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ TRG_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);\r
+ TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ TRG_BUSY_OUT : out std_logic;\r
+ \r
+ --IPU Channel\r
+ IPU_SEND_IN : in std_logic;\r
+ IPU_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ -- Receiver port\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_BUSY_OUT : out std_logic;\r
+ \r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ REGIO_ONEWIRE_INOUT : inout std_logic;\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+ TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received\r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ STAT_DEBUG_1 : out std_logic_vector(31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector(31 downto 0)\r
+ );\r
+ \r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ component etrax_interface is\r
+ generic(\r
+ STATUS_REGISTERS : integer := 4;\r
+ CONTROL_REGISTERS : integer := 4\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ --Connection to Etrax\r
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);\r
+ ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);\r
+ ETRAX_BUS_BUSY : out std_logic;\r
+ --Connection to internal FPGA logic (all addresses above 0x100)\r
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);\r
+ INTERNAL_READ_OUT : out std_logic;\r
+ INTERNAL_WRITE_OUT : out std_logic;\r
+ INTERNAL_DATAREADY_IN : in std_logic;\r
+ INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)\r
+ FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);\r
+ FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);\r
+ --Reset FPGA via Etrax\r
+ EXTERNAL_RESET : out std_logic;\r
+ STAT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_fifo is\r
+ generic (\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_NO;\r
+ USE_DATA_COUNT : integer range 0 to 1 := c_NO;\r
+ DEPTH : integer := 6\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
+ READ_ENABLE_IN : in std_logic;\r
+ DATA_COUNT_OUT : out std_logic_vector(10 downto 0);\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net_fifo_16bit_bram_dualport is\r
+ generic(\r
+ USE_STATUS_FLAGS : integer := c_YES\r
+ );\r
+ port(read_clock_in : in std_logic;\r
+ write_clock_in : in std_logic;\r
+ read_enable_in : in std_logic;\r
+ write_enable_in : in std_logic;\r
+ fifo_gsr_in : in std_logic;\r
+ write_data_in : in std_logic_vector(17 downto 0);\r
+ read_data_out : out std_logic_vector(17 downto 0);\r
+ full_out : out std_logic;\r
+ empty_out : out std_logic;\r
+ fifostatus_out : out std_logic_vector(3 downto 0);\r
+ valid_read_out : out std_logic;\r
+ almost_empty_out : out std_logic;\r
+ almost_full_out : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component fifo_dualclock_width_16_reg is\r
+ port (\r
+ Data : in std_logic_vector(17 downto 0);\r
+ WrClock : in std_logic;\r
+ RdClock : in std_logic;\r
+ WrEn : in std_logic;\r
+ RdEn : in std_logic;\r
+ Reset : in std_logic;\r
+ RPReset : in std_logic;\r
+ Q : out std_logic_vector(17 downto 0);\r
+ Empty : out std_logic;\r
+ Full : out std_logic);\r
+ end component;\r
+ \r
+ \r
+ \r
---component fifo_var_oreg is\r
---generic(\r
- --FIFO_WIDTH : integer range 1 to 64 := 36;\r
- --FIFO_DEPTH : integer range 1 to 16 := 8\r
- --);\r
---port(\r
- --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);\r
- --Clock : in std_logic;\r
- --WrEn : in std_logic;\r
- --RdEn : in std_logic;\r
- --Reset : in std_logic;\r
- --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);\r
- --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);\r
- --WCNT : out std_logic_vector(FIFO_DEPTH downto 0);\r
- --Empty : out std_logic;\r
- --Full : out std_logic;\r
- --AlmostFull : out std_logic\r
- --);\r
---end component;\r
-\r
-\r
-\r
+ component fpga_reboot is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DO_REBOOT : in std_logic;\r
+ PROGRAMN : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component handler_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ \r
+ --LVL1 Handler\r
+ LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type\r
+ LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number\r
+ LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+ \r
+ --FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ \r
+ --IPU Handler\r
+ IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+ \r
+ IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_HDR_DATA_READ_IN : in std_logic;\r
+ IPU_HDR_DATA_EMPTY_OUT : out std_logic;\r
+ \r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF";\r
+ --Status\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+ \r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ \r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component handler_ipu is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ \r
+ --From Data Handler\r
+ DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+ DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_HDR_DATA_READ_OUT : out std_logic;\r
+ DAT_HDR_DATA_EMPTY_IN : in std_logic;\r
+ \r
+ --To IPU Channel\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ \r
+ --Debug\r
+ STATUS_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ \r
+ end component;\r
+ \r
+ \r
+ \r
+ component handler_lvl1 is\r
+ generic(\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ RESET_FLAGS_IN : in std_logic;\r
+ RESET_STATS_IN : in std_logic;\r
+ CLOCK : in std_logic;\r
+ --Timing Trigger\r
+ LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics\r
+ LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger\r
+ --LVL1_handler connection\r
+ LVL1_TRG_RECEIVED_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS\r
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS\r
+ \r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release\r
+ LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter\r
+ LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter\r
+ \r
+ --FEE logic / Data Handler\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+ LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected\r
+ LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_LONG_TRG_OUT : out std_logic;\r
+ SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10\r
+ \r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE\r
+ \r
+ --Stat/Control\r
+ STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers\r
+ TRG_ENABLE_IN : in std_logic; -- trigger enable flag\r
+ TRG_INVERT_IN : in std_logic; -- trigger invert flag\r
+ COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0);\r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component handler_trigger_and_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ RESET_IPU : in std_logic;\r
+ \r
+ --To Endpoint\r
+ --Timing Trigger (registered)\r
+ LVL1_VALID_TRIGGER_IN : in std_logic;\r
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ --LVL1_handler connection\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+ \r
+ --IPU channel\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+ \r
+ --To FEE\r
+ --FEE to Trigger\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ \r
+ --Data Input from FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ \r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF";\r
+ --Status Registers\r
+ STATUS_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector(1 downto 0);\r
+ STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);\r
+ STATISTICS_READY_OUT : out std_logic;\r
+ STATISTICS_READ_IN : in std_logic;\r
+ STATISTICS_UNKNOWN_OUT : out std_logic;\r
+ \r
+ --Debug\r
+ DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);\r
+ DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)\r
+ \r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_ibuf is\r
+ generic (\r
+ DEPTH : integer range 0 to 7 := c_FIFO_BRAM;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
+ -- Status and control port\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component fifo_36x512 is\r
+ port (\r
+ Data : in std_logic_vector(35 downto 0);\r
+ Clock : in std_logic;\r
+ WrEn : in std_logic;\r
+ RdEn : in std_logic;\r
+ Reset : in std_logic;\r
+ Q : out std_logic_vector(35 downto 0);\r
+ Empty : out std_logic;\r
+ Full : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net16_iobuf is\r
+ generic (\r
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; --std_FIFO_DEPTH;\r
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; --std_IBUF_SECURE_MODE;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;\r
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_INIT_DATAREADY_OUT : out std_logic;\r
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_INIT_READ_IN : in std_logic;\r
+ MED_REPLY_DATAREADY_OUT : out std_logic;\r
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_REPLY_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_INIT_DATAREADY_IN : in std_logic;\r
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_OUT : out std_logic;\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_REPLY_DATAREADY_IN : in std_logic;\r
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ STAT_GEN : out std_logic_vector (31 downto 0);\r
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_GEN : in std_logic_vector (31 downto 0);\r
+ CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');\r
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
\r
- -- component trb_net16_gbe_buf is\r
- -- generic(\r
- -- DO_SIMULATION : integer range 0 to 1 := 1;\r
- -- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
- -- );\r
- -- port(\r
- -- CLK : in std_logic;\r
- -- TEST_CLK : in std_logic; -- only for simulation!\r
- -- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
- -- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
- -- RESET : in std_logic;\r
- -- GSR_N : in std_logic;\r
- -- -- Debug\r
- -- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
- -- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
- -- -- configuration interface\r
- -- IP_CFG_START_IN : in std_logic;\r
- -- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
- -- IP_CFG_DONE_OUT : out std_logic;\r
- -- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
- -- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
- -- IP_CFG_MEM_CLK_OUT : out std_logic;\r
- -- MR_RESET_IN : in std_logic;\r
- -- MR_MODE_IN : in std_logic;\r
- -- MR_RESTART_IN : in std_logic;\r
- -- -- gk 29.03.10\r
- -- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
- -- SLV_READ_IN : in std_logic;\r
- -- SLV_WRITE_IN : in std_logic;\r
- -- SLV_BUSY_OUT : out std_logic;\r
- -- SLV_ACK_OUT : out std_logic;\r
- -- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- -- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- -- gk 22.04.10\r
- -- -- registers setup interface\r
- -- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
- -- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- -- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
- -- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
- -- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
- -- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
- -- -- gk 23.04.10\r
- -- LED_PACKET_SENT_OUT : out std_logic;\r
- -- LED_AN_DONE_N_OUT : out std_logic;\r
- -- -- CTS interface\r
- -- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- -- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
- -- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- -- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
- -- CTS_START_READOUT_IN : in std_logic;\r
- -- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
- -- CTS_DATAREADY_OUT : out std_logic;\r
- -- CTS_READOUT_FINISHED_OUT : out std_logic;\r
- -- CTS_READ_IN : in std_logic;\r
- -- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- -- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- -- -- Data payload interface\r
- -- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
- -- FEE_DATAREADY_IN : in std_logic;\r
- -- FEE_READ_OUT : out std_logic;\r
- -- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
- -- FEE_BUSY_IN : in std_logic;\r
- -- --SFP Connection\r
- -- SFP_RXD_P_IN : in std_logic;\r
- -- SFP_RXD_N_IN : in std_logic;\r
- -- SFP_TXD_P_OUT : out std_logic;\r
- -- SFP_TXD_N_OUT : out std_logic;\r
- -- SFP_REFCLK_P_IN : in std_logic;\r
- -- SFP_REFCLK_N_IN : in std_logic;\r
- -- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- -- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- -- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- -- debug ports\r
- -- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- -- );\r
- -- end component;\r
\r
\r
- component fpga_reboot is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- DO_REBOOT : in std_logic;\r
- PROGRAMN : out std_logic\r
- );\r
- end component;\r
- \r
- \r
- component handler_data is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- \r
- --LVL1 Handler\r
- LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts\r
- LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type\r
- LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number\r
- LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
- LVL1_TRG_RELEASE_OUT : out std_logic;\r
- \r
- --FEE\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- \r
- --IPU Handler\r
- IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
- IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
- \r
- IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
- IPU_HDR_DATA_READ_IN : in std_logic;\r
- IPU_HDR_DATA_EMPTY_OUT : out std_logic;\r
- \r
- TMG_TRG_ERROR_IN : in std_logic;\r
- MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; \r
- --Status\r
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
- \r
- --Debug\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
- \r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- component handler_ipu is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- \r
- --From Data Handler\r
- DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
- DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
- DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);\r
- DAT_HDR_DATA_READ_OUT : out std_logic;\r
- DAT_HDR_DATA_EMPTY_IN : in std_logic;\r
- \r
- --To IPU Channel\r
- IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
- IPU_START_READOUT_IN : in std_logic;\r
- IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_OUT : out std_logic;\r
- IPU_READOUT_FINISHED_OUT : out std_logic;\r
- IPU_READ_IN : in std_logic;\r
- IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- \r
- --Debug\r
- STATUS_OUT : out std_logic_vector(31 downto 0)\r
- );\r
- \r
- end component;\r
- \r
- \r
- \r
- component handler_lvl1 is\r
- generic(\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- RESET : in std_logic;\r
- RESET_FLAGS_IN : in std_logic;\r
- RESET_STATS_IN : in std_logic;\r
- CLOCK : in std_logic;\r
- --Timing Trigger\r
- LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics\r
- LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger\r
- --LVL1_handler connection\r
- LVL1_TRG_RECEIVED_IN : in std_logic;\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS\r
- LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS\r
- \r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release\r
- LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter\r
- LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter\r
- \r
- --FEE logic / Data Handler\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid\r
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received\r
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received\r
- LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
- LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected\r
- LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_LONG_TRG_OUT : out std_logic; \r
- SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10\r
- \r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE\r
- LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE\r
- \r
- --Stat/Control\r
- STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers\r
- TRG_ENABLE_IN : in std_logic; -- trigger enable flag\r
- TRG_INVERT_IN : in std_logic; -- trigger invert flag\r
- COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0);\r
- --Debug\r
- DEBUG_OUT : out std_logic_vector (15 downto 0)\r
- );\r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- component handler_trigger_and_data is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- RESET_IPU : in std_logic;\r
- \r
- --To Endpoint\r
- --Timing Trigger (registered)\r
- LVL1_VALID_TRIGGER_IN : in std_logic;\r
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- --LVL1_handler connection\r
- LVL1_TRG_DATA_VALID_IN : in std_logic;\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
- LVL1_TRG_RELEASE_OUT : out std_logic;\r
- \r
- --IPU channel\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
- IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);\r
- IPU_START_READOUT_IN : in std_logic;\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0);\r
- IPU_DATAREADY_OUT : out std_logic;\r
- IPU_READOUT_FINISHED_OUT : out std_logic;\r
- IPU_READ_IN : in std_logic;\r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
- \r
- --To FEE\r
- --FEE to Trigger\r
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- \r
- --Data Input from FEE\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- \r
- TMG_TRG_ERROR_IN : in std_logic;\r
- MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0);\r
- --Status Registers\r
- STATUS_OUT : out std_logic_vector(127 downto 0);\r
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
- TIMER_TICKS_IN : in std_logic_vector(1 downto 0);\r
- STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);\r
- STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);\r
- STATISTICS_READY_OUT : out std_logic;\r
- STATISTICS_READ_IN : in std_logic;\r
- STATISTICS_UNKNOWN_OUT : out std_logic;\r
- \r
- --Debug\r
- DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);\r
- DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)\r
- \r
- );\r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- component trb_net16_ibuf is\r
- generic (\r
- DEPTH : integer range 0 to 7 := c_FIFO_BRAM;\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
- USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
- -- Internal direction port\r
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_DATAREADY_OUT : out std_logic;\r
- INT_INIT_READ_IN : in std_logic;\r
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_DATAREADY_OUT : out std_logic;\r
- INT_REPLY_READ_IN : in std_logic;\r
- INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
- -- Status and control port\r
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_BUFFER : out std_logic_vector (31 downto 0);\r
- CTRL_STAT : in std_logic_vector (15 downto 0)\r
- );\r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- \r
- component fifo_36x512 is\r
- port (\r
- Data: in std_logic_vector(35 downto 0);\r
- Clock: in std_logic;\r
- WrEn: in std_logic;\r
- RdEn: in std_logic;\r
- Reset: in std_logic;\r
- Q: out std_logic_vector(35 downto 0);\r
- Empty: out std_logic;\r
- Full: out std_logic\r
- );\r
- end component;\r
- \r
- \r
- --component fifo_var_oreg is\r
- --generic(\r
- --FIFO_WIDTH : integer range 1 to 64 := 36;\r
- --FIFO_DEPTH : integer range 1 to 16 := 8\r
- --);\r
- --port(\r
- --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);\r
- --Clock : in std_logic;\r
- --WrEn : in std_logic;\r
- --RdEn : in std_logic;\r
- --Reset : in std_logic;\r
- --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);\r
- --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);\r
- --WCNT : out std_logic_vector(FIFO_DEPTH downto 0);\r
- --Empty : out std_logic;\r
- --Full : out std_logic;\r
- --AlmostFull : out std_logic\r
- --);\r
- --end component;\r
- \r
- \r
- \r
- component trb_net16_iobuf is\r
- generic (\r
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;\r
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
- SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;\r
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;\r
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
- USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES;\r
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_INIT_DATAREADY_OUT : out std_logic;\r
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_INIT_READ_IN : in std_logic;\r
- MED_REPLY_DATAREADY_OUT : out std_logic;\r
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_REPLY_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
- -- Internal direction port\r
- INT_INIT_DATAREADY_OUT : out std_logic;\r
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_READ_IN : in std_logic;\r
- INT_INIT_DATAREADY_IN : in std_logic;\r
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_READ_OUT : out std_logic;\r
- INT_REPLY_DATAREADY_OUT : out std_logic;\r
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_READ_IN : in std_logic;\r
- INT_REPLY_DATAREADY_IN : in std_logic;\r
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_READ_OUT : out std_logic;\r
- -- Status and control port\r
- STAT_GEN : out std_logic_vector (31 downto 0);\r
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);\r
- CTRL_GEN : in std_logic_vector (31 downto 0);\r
- CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');\r
- STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
- TIMER_TICKS_IN : in std_logic_vector (1 downto 0);\r
- CTRL_STAT : in std_logic_vector (15 downto 0)\r
- );\r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- \r
- component trb_net16_io_multiplexer is\r
- generic(\r
- USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_IN : in STD_LOGIC;\r
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out STD_LOGIC;\r
- MED_DATAREADY_OUT : out STD_LOGIC;\r
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in STD_LOGIC;\r
- -- Internal direction port\r
- INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);\r
- INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
- INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
- INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
- INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
- -- Status and control port\r
- CTRL : in STD_LOGIC_VECTOR (31 downto 0);\r
- STAT : out STD_LOGIC_VECTOR (31 downto 0)\r
- );\r
- end component;\r
- \r
- \r
- \r
- \r
- \r
- component trb_net16_ipudata is\r
- generic(\r
- DO_CHECKS : integer range c_NO to c_YES := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Port to API\r
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_DATAREADY_OUT : out std_logic;\r
- API_READ_IN : in std_logic;\r
- API_SHORT_TRANSFER_OUT : out std_logic;\r
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- API_SEND_OUT : out std_logic;\r
- -- Receiver port\r
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_TYP_IN : in std_logic_vector (2 downto 0);\r
- API_DATAREADY_IN : in std_logic;\r
- API_READ_OUT : out std_logic;\r
- -- APL Control port\r
- API_RUN_IN : in std_logic;\r
- API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
- API_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
- \r
- --Information received with request\r
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);\r
- --start strobe\r
- IPU_START_READOUT_OUT: out std_logic;\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_IN : in std_logic;\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN : in std_logic;\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT : out std_logic;\r
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
- \r
- STAT_DEBUG : out std_logic_vector(31 downto 0)\r
- );\r
- end component;\r
+ \r
+ \r
+ \r
+ component trb_net16_io_multiplexer is\r
+ generic(\r
+ USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ -- Internal direction port\r
+ INT_DATA_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);\r
+ INT_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_DATAREADY_IN : in std_logic_vector (2**c_MUX_WIDTH-1 downto 0);\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_READ_OUT : out std_logic_vector (2**c_MUX_WIDTH-1 downto 0);\r
+ -- Status and control port\r
+ CTRL : in std_logic_vector (31 downto 0);\r
+ STAT : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ component trb_net16_ipudata is\r
+ generic(\r
+ DO_CHECKS : integer range c_NO to c_YES := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Port to API\r
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ API_SHORT_TRANSFER_OUT : out std_logic;\r
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ API_SEND_OUT : out std_logic;\r
+ -- Receiver port\r
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_TYP_IN : in std_logic_vector (2 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ -- APL Control port\r
+ API_RUN_IN : in std_logic;\r
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
+ API_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ \r
+ --Information received with request\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT : out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+ \r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
-- \r
-- component trb_net16_gbe_buf is\r
-- generic(\r
jspc29 / trbnet.git / commitdiff