cleanup of some code issues

diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd
index f2542321503d2960ee566ca3c483641a8b0c128a..5686b7479ebfc8549d0b7738ac506ec50b67845f 100644 (file)
--- a/releases/tdc_v2.3/Encoder_288_Bit.vhd
+++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd
@@ -182,7 +182,7 @@ begin
 
 gen_ROM_5 : if FPGA_TYPE = 5 generate  
 --  The_ROM : entity work.ROM_encoder_3 --SIMULATION
-  The_ROM_5 : entity work.ROM_encoder_4   --REAL
+  The_ROM_5 : ROM_encoder_4   --REAL
     port map (
       Address    => address,
       OutClock   => CLK,
@@ -191,7 +191,7 @@ gen_ROM_5 : if FPGA_TYPE = 5 generate
       Q          => q_reg);
 end generate;
 gen_ROM_3 : if FPGA_TYPE = 3 generate  
-  The_ROM_3 : entity work.ROM_encoder_3   --REAL
+  The_ROM_3 : ROM_encoder_3   --REAL
     port map (
       Address    => address,
       OutClock   => CLK,

diff --git a/releases/tdc_v2.3/tdc_components.vhd b/releases/tdc_v2.3/tdc_components.vhd
index 9aabf2a513e94bed3d0750c015a83e4a60cfe432..fcad7f3a32a8a0aa135c680bf0c232b4bd678c41 100644 (file)
--- a/releases/tdc_v2.3/tdc_components.vhd
+++ b/releases/tdc_v2.3/tdc_components.vhd
@@ -445,7 +445,16 @@ package tdc_components is
       Reset      : in  std_logic;
       Q          : out std_logic_vector(7 downto 0));
   end component;
-
+  
+  component ROM_encoder_4
+    port (
+      Address    : in  std_logic_vector(9 downto 0);
+      OutClock   : in  std_logic;
+      OutClockEn : in  std_logic;
+      Reset      : in  std_logic;
+      Q          : out std_logic_vector(7 downto 0));
+  end component;
+  
   component ROM4_Encoder is
     port (
       Address    : in  std_logic_vector(9 downto 0);

diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
index 087b8bcefd3e2f082402ac1ba7990056e72c3f32..e9d68ed8d1f0bd4c2c725d1a51d1d0b0be338a1a 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
+++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
@@ -9,7 +9,7 @@ use work.trb3_components.all;
 use work.tdc_components.all;
 use work.config.all;
 use work.tdc_version.all;
-use work.version.all;
+use work.version.all; 
 
 
 entity trb3_periph_32PinAddOn is
@@ -25,8 +25,6 @@ entity trb3_periph_32PinAddOn is
     --Serdes
     CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
     CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
---     SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
---     SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
     --Inter-FPGA Communication
     FPGA5_COMM           : inout std_logic_vector(11 downto 0);
                                         --Bit 0/1 input, serial link RX active
@@ -202,12 +200,6 @@ begin
       MED_READ_IN        => '1',
       REFCLK2CORE_OUT    => open,
       --SFP Connection
---       SD_RXD_P_IN        => SERDES_INT_RX(2),
---       SD_RXD_N_IN        => SERDES_INT_RX(3),
---       SD_TXD_P_OUT       => SERDES_INT_TX(2),
---       SD_TXD_N_OUT       => SERDES_INT_TX(3),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
       SD_PRSNT_N_IN      => FPGA5_COMM(0),
       SD_LOS_IN          => FPGA5_COMM(0),
       SD_TXDIS_OUT       => FPGA5_COMM(2),