\begin{tabular}{ll}
Name & Bereich\\
RAM & 0x000 - 0x0FF\\
-STATUS & 0x100 - 0x11F\\
-CONTROL & 0x120 - 0x13F\\
DEBUG & 0x140 - 0x15F\\
STATUS2 & 0x160 - 0x17F\\
\end{tabular}
-\caption{Die 5 Adressbereiche des JTAG-Chain-Controllers.}
+\caption{Die Adressbereiche des JTAG-Chain-Controllers.}
\label{table:trbnet_address_ranges}
\end{table}
\subsubsection{RAM-Adressen}
Das RAM \textbf{ram1a}, das die JTAG-Register für alle Sensoren speichert, kann über diesen Adressbereich mit 256 32-bit Wörtern
beschrieben und ausgelesen werden (Tabelle \ref{table:ram_addrs}).
Die 8 bit dieses Adressraums entsprechen den 8 niederwertigsten Bits der \textbf{ram1a}-Adresse.
-Die höheren Adressbits werden über das im folgenden Abschitt
-"`CONTROL-Adressen"' beschriebene Register mit der Adresse 0x121 eingestellt.
+Die höheren Adressbits werden über das im folgenden Abschitt zu findende Register eingestellt.
In der Standardeinstellung ist der Block für einen Sensor auch 256 32-bit Wörter (entspricht 8 kbit Speicherbereichen) groß.
Die höherwertigen Adressbits geben in diesem Fall an, welcher Sensor ausgewählt ist.\footnote{Wenn die Speichergröße für einen Sensor
von 8 kbit abweichend gewählt wird, enthalten die 256 Wörter dieses Adressbereichs
\caption{Register im RAM-Adressbereich.}
\label{table:ram_addrs}
\end{table}
-\subsubsection{STATUS-Adressen}
-\label{section_addresses_status}
-Unter der Adresse 0x100 kann für die ersten 32 Sensoren der Status des CRC-Checks des \textbf{ram1a}-Speicherbereichs abgefragt werden (Tabelle \ref{table:status_addrs}). Bei erfolgreichem
-CRC-Check ist das Bit auf 1 gesetzt. Dabei gehört das niederwertigste Bit zum ersten Sensor.
-\begin{table}
-\renewcommand{\arraystretch}{1.4}
-\begin{tabular}{p{3.5cm}lp{8cm}}
-Name & Adresse & Beschreibung\\
-CRC\_STATUS & 0x100 & 32 bit Status-Register des letzten CRC-Checks für die ersten 32 Sensoren. "`Bit i"' = 1 $\to$ CRC-Check ok für Sensor i.\\
-\end{tabular}
-\caption{Register im STATUS-Adressbereich.}
-\label{table:status_addrs}
-\end{table}
-\subsubsection{CONTROL-Adressen}
-\label{abschnitt_control}
-Die Register sind in Tabelle \ref{table:control_addrs} zusammengefasst.
-Es gibt ein Befehls- und ein Datenregister, die bei
-(hexadezimal) 0x120 und 0x122 liegen.
-
-Das Register 0x121 wählt den Speicherbereich aus \textbf{ram1a} aus, der durch die im Abschnitt "`RAM-Adressen"' beschriebenen Adressen
-zugänglich ist.
-\begin{table}
-\renewcommand{\arraystretch}{1.4}
-\begin{tabular}{p{3.5cm}lp{8cm}}
-Name & Adresse & Beschreibung\\
-CMD & 0x120 & Befehlsregister, siehe Abschnitt \ref{abschnitt_control}.\\
-RAM\_BASEADDR & 0x121 & Wählt einen Speicherbereich mit 256 32-bit Worten aus \textbf{ram1a} aus. Diese Adresse entspricht der RAM-Adresse ohne die 8 niederwertigsten Bits. \\
-DATA\_REGISTER & 0x122 & Datenregister, siehe Abschnitt \ref{abschnitt_control}.\\
-\end{tabular}
-\caption{Register im CONTROL-Adressbereich.}
-\label{table:control_addrs}
-\end{table}
-Ein Befehl wird ausgeführt, indem per TrbNet ein 8 bit-Code an die untersten 8 bit des 32-bit-Befehlsregisters geschrieben wird.
-Das Datenregister kann per TrbNet beschrieben werden, aber auch von ausgeführten Befehlen verändert werden.
-Auf das Datenregister kann man auch lesend zugreifen, um das Ergebnis eines Befehls auszulesen.
+\subsubsection{Control \& Status-Adressen}
+
+
+Eine Liste der Befehle, deren Code in \texttt{jtag\_constants.vhd} festgelegt ist, findet sich in
+Tabelle \ref{table:trbnet_commands}.
-Eine Liste der Befehle, deren Code in \texttt{jtag\_constants.vhd} festgelegt ist, findet sich in den Tabellen
-\ref{table:trbnet_commands} und \ref{table:trbnet_commands2}.
\begin{table}
-\renewcommand{\arraystretch}{1.4}
-\begin{tabular}{p{5cm}lp{10cm}}
-Name & Code & Beschreibung\\
-NONE & 00 & Leerer Befehl.\\
-START & 09 & Aktiviert das Warten auf den \texttt{OFF\_SPILL\_IN}-Trigger (\texttt{jtag\_refresh\_active} = 1).\\
-STOP & 0A & Beendet sowohl Warten auf \texttt{OFF\_SPILL\_IN}-Trigger (\texttt{jtag\_refresh\_active} = 0) als auch check1 (\texttt{jtag\_check1\_active} = 0). Nach Beendigung eventuell noch laufender Programmiervorgänge wird der STOP-Zustand erreicht (\texttt{m26cs\_stopped} = 1).\\
-REMOVE\_SENSOR & 10 & Wenn gestoppt (\texttt{m26cs\_stopped} = 1), wird der im Datenregister eingestellte Sensor als nicht in der Kette befindlich markiert und dadurch bei kommenden Programmiervorgängen übersprungen, so dass eine Kette mit weniger Sensoren programmiert wird.\\
-INSERT\_SENSOR & 11 & Wenn gestoppt (\texttt{m26cs\_stopped} = 1), wird der im Datenregister eingestellte Sensor als nicht in der Kette befindlich markiert und dadurch bei kommenden Programmiervorgängen übersprungen, so dass eine Kette mit weniger Sensoren programmiert wird.\\
-GET\_NUMCHIPS\_CONFIGURED & 12& Die eingestellte Anzahl der im RAM zu liegenden Sensor-Blöcke wird ins Datenregister geschrieben.\\
-SET\_NUMCHIPS\_CONFIGURED & 33 & Aus dem Datenregister wird die Anzahl der im RAM zu liegenden Sensor-Blöcke übernommen.\\
-GET\_NUMCHIPS\_ACTIVE & 13& Die Anzahl nicht entfernter Sensoren wird ins Datenregister geschrieben.\\
-GET\_TRIGGER\_COUNT &14 & Die Zahl der \texttt{OFF\_SPILL\_IN}-Trigger wird ins Datenregister kopiert.\\
-GET\_REMOVED &1d& Schreibt 1 ins Datenregister, wenn der vorher im Datenregister eingestellte Sensor als entfernt markiert ist.\\
-GET\_REMOVED32 &1e& Schreibt für die ersten maximal 32 Sensoren die Entfernt-Markierung in das 32-bit Datenregister. (1 = entfernt, 0 = nicht entfernt).\\
-SET\_BREAKPOINTS & 53 & Setzt \texttt{breakpoint\_active}, siehe VHDL-Code \texttt{jtag\_cmd\_m26c.vhd} für Stellen, an denen die State-Machine angehalten wird.\\
-GET\_BREAKPOINTS & 52 & Schreibt \texttt{breakpoint\_active} ins Datenregister.\\
-SET\_JTAG\_CLOCK\_CYCLE\-\_LENGTH & 40 & setzt die Dauer des JTAG-Takzyklus (\texttt{jtag\_clock\_cycle\_length}, angegeben in Systemtakten).\\
-GET\_JTAG\_CLOCK\_CYCLE\-\_LENGTH &41 & schreibt die Dauer des JTAG-Takzyklus (\texttt{jtag\_clock\_cycle\_length}, in Systemtakten) in das Datenregister.\\
-SET\_JTAG\_CLOCK\_TIME1 &42 & Setzt den Zeitpunkt der steigenden TCK-Taktflanke (\texttt{jtag\_clock\_time1}) innerhalb des durch jtag\_clock\_cycle\_length gegebenen Bereichs.\\
-GET\_JTAG\_CLOCK\_TIME1 & 43& schreibt den Wert von \texttt{jtag\_clock\_time1} in das Datenregister.\\
-SET\_JTAG\_CLOCK\_TIME2 &44& Setzt den Zeitpunkt der fallenden TCK-Taktflanke (\texttt{jtag\_clock\_time2}) innerhalb des durch jtag\_clock\_cycle\_length gegebenen Bereichs.\\
-GET\_JTAG\_CLOCK\_TIME2 &45& schreibt den Wert von \texttt{jtag\_clock\_time2} in das Datenregister.\\
-\end{tabular}
+\renewcommand{\arraystretch}{1.4}
+\begin{tabular}{p{5cm}llp{9cm}}
+Name & Alt & Neu & Beschreibung\\
+SET\_NUMCHIPS\_CONFIGURED & 33 & 00 & Zahl der im RAM vorhandenen Sensor-Blöcke.\\
+SET\_JTAG\_CLOCK\_CYCLE\-\_LENGTH & 40 & 01 & setzt die Dauer des JTAG-Taktzyklus
+(\texttt{jtag\_clock\_cycle\_length} in Systemtakten).\\
+SET\_JTAG\_CLOCK\_TIME1 &42 & 02 & Setzt den Zeitpunkt der steigenden TCK-Taktflanke
+(\texttt{jtag\_clock\_time1}) innerhalb des durch jtag\_clock\_cycle\_length gegebenen Bereichs.\\
+SET\_JTAG\_CLOCK\_TIME2 &44 & 03 & Setzt den Zeitpunkt der fallenden TCK-Taktflanke
+(\texttt{jtag\_clock\_time2}) innerhalb des durch jtag\_clock\_cycle\_length gegebenen Bereichs.\\
+SET\_JTAG\_SAMPLE\_TIME1 &46 & 04 & Setzt den Zeitpunkt der ersten Abtastung des TDO\_IN-Signals
+(\texttt{jtag\_sample\_time1}).\\
+SET\_JTAG\_SAMPLE\_TIME2 &48 & 05 & Setzt den Zeitpunkt der zweiten Abtastung des TDO\_IN-Signals
+(\texttt{jtag\_sample\_time2}).\\
+SET\_JTAG\_SAMPLE\_TIME3 &4a & 06 & Setzt den Zeitpunkt der dritten Abtastung des TDO\_IN-Signals
+(\texttt{jtag\_sample\_time3}).\\
+SET\_JTAG\_SET\_DATA\_TIME&4c & 07 & Setzt den Zeitpunkt für das Ändern der TMS und TDI-Ausgänge des
+FPGA
+(\texttt{set\_data\_time}).\\
+SET\_DELAY\_EXPECTED\-\_VALUES &67& 08 & Setze die Zahl der TCK-Takte, um die das TDO-Signal des
+letzten
+Sensors verzögert eintrifft (\texttt{jtag\_delay\_expvalues}, Wertebereich 0 - 3).\\
+\hline
+GET\_RUN\_COUNT &50& 10 & Liest den Wert des Durchlauf-Zählers, \texttt{run\_counter}.\\
+GET\_NUMCHIPS\_ACTIVE & 13& 11 & Liest die Anzahl nicht entfernter Sensoren.\\
+GET\_TRIGGER\_COUNT &14 & 12 & Liest die Zahl der \texttt{OFF\_SPILL\_IN}-Trigger.\\
+GET\_LAST\_NOT\_REMOVED & 1c & 13 & Nummer des letzten, nicht entfernten Sensors.\\
+GET\_CRC\_STATUS & 100 & 14 & Status flags of CRC check for 32 sensors.\\
+\hline
+START & 09 & 40 & Aktiviert das Warten auf den \texttt{OFF\_SPILL\_IN}-Trigger
+\texttt{jtag\_refresh\_active} = Bit 0, \texttt{jtag\_check1\_active} = Bit 1 (überspringen des
+Schreibens der Register)\\
+REMOVE\_SENSOR & 10 & 41 & Wenn gestoppt (\texttt{m26cs\_stopped} = 1), wird der im Datenregister
+eingestellte Sensor als nicht in der Kette befindlich markiert. Bit 31 = 1: Sensor wird entfernt,
+Bit 31 = 0: Sensor wird hinzugefügt.\\
+SET\_CSOPTIONS &65& 42 & Setze Optionen (\texttt{m26csoptions}): bit 0 $\to$ Überspringe
+\textbf{BYPASSREG\_TESTCHAIN}.\\
+RAM\_BASEADDR & 121 & 43 & Wählt einen Speicherbereich mit 256 32-bit Worten aus \textbf{ram1a}
+aus. Diese Adresse entspricht der RAM-Adresse ohne die 8 niederwertigsten Bits. \\
+\hline
+SET\_BREAKPOINTS & 53 & 50 & Setzt \texttt{breakpoint\_active}, siehe VHDL-Code
+\texttt{jtag\_cmd\_m26c.vhd} für Stellen, an denen die State-Machine angehalten wird.\\
+COPY\_TO\_STATUS2 &63& 51 & Das Kopieren von \textbf{ram3a} in \textbf{ram3b} wird nach Beenden des
+Durchlaufs aus Abb. \ref{fig:m26controller_simple} durchgeführt.\\
+COPY\_RAM1B1C\_SINGLE\-\_TRIGGER &64& 52 & Setze den Trigger für das Kopieren von \textbf{ram1b}
+nach
+\textbf{ram1c} (siehe Abschnitt MA:\ref{MA-rams_description}) auf bit 0 $\to$ read error, 1 $\to$
+write error, 2 $\to$ data changed, 3 $\to$ next run.\\
+\end{tabular}
\caption{Befehle für den JTAG-Chain-Controller, die per TrbNet geschickt werden können.}
\label{table:trbnet_commands}
\end{table}
-\begin{table}
-\renewcommand{\arraystretch}{1.4}
-\begin{tabular}{p{5cm}lp{10cm}}
-SET\_JTAG\_SAMPLE\_TIME1 &46 & Setzt den Zeitpunkt der ersten Abtastung des TDO\_IN-Signals (\texttt{jtag\_sample\_time1}).\\
-GET\_JTAG\_SAMPLE\_TIME1 &47 & Schreibt den Wert von \texttt{jtag\_sample\_time1} ins Datenregister.\\
-SET\_JTAG\_SAMPLE\_TIME2 &48 & Setzt den Zeitpunkt der zweiten Abtastung des TDO\_IN-Signals (\texttt{jtag\_sample\_time2}).\\
-GET\_JTAG\_SAMPLE\_TIME2 &49 & Schreibt den Wert von \texttt{jtag\_sample\_time2} ins Datenregister.\\
-SET\_JTAG\_SAMPLE\_TIME3 &4a & Setzt den Zeitpunkt der dritten Abtastung des TDO\_IN-Signals (\texttt{jtag\_sample\_time3}).\\
-GET\_JTAG\_SAMPLE\_TIME3 &4b & Schreibt den Wert von \texttt{jtag\_sample\_time3} ins Datenregister.\\
-SET\_JTAG\_SET\_DATA\_TIME&4c & Setzt den Zeitpunkt für das Ändern der TMS und TDI-Ausgänge des FPGA (\texttt{set\_data\_time}).\\
-GET\_JTAG\_SET\_DATA\_TIME&4d& Schreibt den Wert von set\_data\_time ins Datenregister.\\
-GET\_RUN\_COUNT &50& Schreibt den Wert des Durchlauf-Zählers, \texttt{run\_counter}, in das Datenregister.\\
-START\_CHECK1 &60& Setzt \texttt{jtag\_check1\_active} auf 1. Damit wird das Schreiben der Register der Sensoren übersprungen.\\
-COPY\_TO\_STATUS2 &63& Das Kopieren von \textbf{ram3a} in \textbf{ram3b} wird nach Beenden des Durchlaufs aus Abb. \ref{fig:m26controller_simple} durchgeführt.\\
-COPY\_RAM1B1C\_SINGLE\-\_TRIGGER &64& Setze den Trigger für das Kopieren von \textbf{ram1b} nach \textbf{ram1c} (siehe Abschnitt MA:\ref{MA-rams_description}) auf bit 0 $\to$ read error, 1 $\to$ write error, 2 $\to$ data changed, 3 $\to$ next run.\\
-SET\_CSOPTIONS &65& Setze Optionen (\texttt{m26csoptions}): bit 0 $\to$ Überspringe \textbf{BYPASSREG\_TESTCHAIN}.\\
-GET\_CSOPTIONS &66& Schreibe \texttt{m26csoptions} in das Datenregister.\\
-SET\_DELAY\_EXPECTED\-\_VALUES &67& Setze die Zahl der TCK-Takte, um die das TDO-Signal des letzten Sensors verzögert eintrifft (\texttt{jtag\_delay\_expvalues}, Wertebereich 0 - 3).\\
-GET\_DELAY\_EXPECTED\-\_VALUES &68& Schreibe \texttt{jtag\_delay\_expvalues} in das Datenregister.\\
-GET\_ACTIVITY &69& Schreibt die Werte der folgenden internen Variablen ins Datenregister: bit 0 $\to$ jtag\_refresh\_active, bit 1 $\to$ jtag\_check1\_active.\\
-\end{tabular}
-\caption{Fortsetzung von Tabelle \ref{table:trbnet_commands}.}
-\label{table:trbnet_commands2}
-\end{table}
+
\subsubsection{DEBUG-Adressen}
Im DEBUG-Adressraum 0x140-0x15F liegen die in Tabelle \ref{table:debug_addrs} angegebenen Register.
my ($chain, $fpga_addr, $cmd_base_addr) = @_;
# return sub {
init_msg( "read ram1b word " . $chain);
- send_write_command($fpga_addr,$cmd_base_addr,0x00000008,0x00000064); #M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER with unconditional trigger
+ send_write_command($fpga_addr,$cmd_base_addr,0x00000008,0x00000052); #M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER with unconditional trigger
# }
}
my($chain, $fpga_addr, $command_base_addr) = @_;
# return sub {
init_msg("timing 10 MHz $chain.");
- send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000009);#M26C_CMD_STOP
- send_write_command($fpga_addr,$command_base_addr,0x0000000A,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
- send_write_command($fpga_addr,$command_base_addr,0x00000003,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x00000008,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x00000004,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x00000004,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x00000004,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
- send_write_command($fpga_addr,$command_base_addr,0x00000009,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
- send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000009);#M26C_CMD_START
+ send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000040);#M26C_CMD_STOP
+ send_write_command($fpga_addr,$command_base_addr,0x0000000A,0x00000001);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$command_base_addr,0x00000003,0x00000002);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x00000008,0x00000003);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x00000004,0x00000004);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x00000004,0x00000005);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x00000004,0x00000006);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$command_base_addr,0x00000009,0x00000007);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000040);#M26C_CMD_START
# }
}
my($chain, $fpga_addr, $command_base_addr) = @_;
# return sub {
init_msg("timing 1 MHz $chain.");
- send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000009);#M26C_CMD_STOP
- send_write_command($fpga_addr,$command_base_addr,0x00000064,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
- send_write_command($fpga_addr,$command_base_addr,0x00000031,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x00000062,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x00000030,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x00000030,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x00000030,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
- send_write_command($fpga_addr,$command_base_addr,0x00000063,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
- send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000009);#M26C_CMD_START
+ send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000040);#M26C_CMD_STOP
+ send_write_command($fpga_addr,$command_base_addr,0x00000064,0x00000001);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$command_base_addr,0x00000031,0x00000002);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x00000062,0x00000003);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x00000030,0x00000004);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x00000030,0x00000005);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x00000030,0x00000006);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$command_base_addr,0x00000063,0x00000007);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000040);#M26C_CMD_START
# }
}
my($chain, $fpga_addr, $command_base_addr) = @_;
# return sub {
init_msg("timing 100 kHz $chain.");
- send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000009);#M26C_CMD_STOP
- send_write_command($fpga_addr,$command_base_addr,0x000003E8,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
- send_write_command($fpga_addr,$command_base_addr,0x000001CC,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x000003C0,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
- send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
- send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
- send_write_command($fpga_addr,$command_base_addr,0x000003E7,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
- send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000009);#M26C_CMD_START
+ send_write_command($fpga_addr,$command_base_addr,0x00000000,0x00000040);#M26C_CMD_STOP
+ send_write_command($fpga_addr,$command_base_addr,0x000003E8,0x00000001);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$command_base_addr,0x000001CC,0x00000002);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x000003C0,0x00000003);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x00000004);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x00000005);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$command_base_addr,0x000001F0,0x00000006);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$command_base_addr,0x000003E7,0x00000007);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$command_base_addr,0x00000001,0x00000040);#M26C_CMD_START
# }
}
my($chain, $fpga_addr, $command_base_addr, $delay) = @_;
# return sub {
init_msg("Delay $delay $chain.");
- send_write_command($fpga_addr,$command_base_addr,$delay,0x00000067);
+ send_write_command($fpga_addr,$command_base_addr,$delay,0x00000008);
# }
}
push(@{$memhash->{$setting_name}},$crc1_rn & 0xFFFFFFFF);
}
}
- trb_register_write($fpga_addr ,$cmd_base_addr+0x9,0x0) or die trb_strerror();
+ trb_register_write($fpga_addr ,$cmd_base_addr+0x40,0x0) or die trb_strerror();
# trb_register_write($fpga_addr ,$data_reg_addr,scalar @sensors) or die trb_strerror();
- trb_register_write($fpga_addr ,$cmd_base_addr+0x33,scalar @sensors) or die trb_strerror();
+ trb_register_write($fpga_addr ,$cmd_base_addr+0x00,scalar @sensors) or die trb_strerror();
for(my $i=0;$i<scalar @settingnames;$i++) {
# write RAM base pointer
if(not defined($opt_quiet)) { print "set RAM base pointer: \n"; }
- trb_register_write($fpga_addr, $ram_base_addr, $i) or die trb_strerror();
+ trb_register_write($fpga_addr, $cmd_base_addr+0x43, $i) or die trb_strerror();
# write to configuration RAM
if(not defined($opt_quiet)) { print "write max. 256 32-bit-words: \n"; }
trb_register_write_mem($fpga_addr,$ram_addr,0,$memhash->{$settingnames[$i]},scalar @{$memhash->{$settingnames[$i]}}) or die trb_strerror();
}
- trb_register_write($fpga_addr, $cmd_base_addr+0x09, 0x1) or die trb_strerror();
+ trb_register_write($fpga_addr, $cmd_base_addr+0x40, 0x1) or die trb_strerror();
if(not defined($opt_quiet)) { print "\n"; }
print "done.\n";
signal bus2_ram_nack_in : std_logic;
signal ram1a_read_delay, ram1a_read_delay2 : std_logic;
-
-signal bus2_status_addr_out : std_logic_vector(15 downto 0);
-signal bus2_status_data_out : std_logic_vector(31 downto 0);
-signal bus2_status_read_enable_out : std_logic;
-signal bus2_status_write_enable_out : std_logic;
-signal bus2_status_data_in : std_logic_vector(31 downto 0);
-signal bus2_status_ack_in : std_logic;
-signal bus2_status_nack_in : std_logic;
-
signal bus2_status2_addr_out : std_logic_vector(15 downto 0);
signal bus2_status2_data_out : std_logic_vector(31 downto 0);
signal bus2_status2_read_enable_out : std_logic;
signal status2_chain_status, status2_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
signal status2_copy_finished: std_logic;
-
---signal bus2_control_addr_out : std_logic_vector(4 downto 0);
-signal bus2_control_addr_out : std_logic_vector(15 downto 0);
-signal bus2_control_data_out : std_logic_vector(31 downto 0);
-signal bus2_control_read_enable_out : std_logic;
-signal bus2_control_write_enable_out : std_logic;
-signal bus2_control_data_in : std_logic_vector(31 downto 0);
-signal bus2_control_ack_in : std_logic;
-signal bus2_control_nack_in : std_logic;
-
--signal bus2_debug_addr_out : std_logic_vector(4 downto 0);
signal bus2_debug_addr_out : std_logic_vector(15 downto 0);
signal bus2_debug_data_out : std_logic_vector(31 downto 0);
the_bus_handler : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", 5 => x"0200", others => (others => '0')),
- PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, 5 => 8, others => 0)
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0140", 2 => x"0160", 3 => x"0200", others => (others => '0')),
+ PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 8, others => 0)
)
port map(
CLK => CLK_IN,
DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, -- don't disturb me now
DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT, -- noone here to answer your request
- --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
BUS_ADDR_OUT(0*16+15 downto 0*16) => bus2_ram_addr_out,
- --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
- BUS_ADDR_OUT(1*16+15 downto 1*16) => bus2_status_addr_out,
- --BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => bus2_control_addr_out,
- --BUS_ADDR_OUT(3*16+15 downto 3*16+5) => open,
- BUS_ADDR_OUT(3*16+15 downto 3*16) => bus2_debug_addr_out,
- BUS_ADDR_OUT(4*16+15 downto 4*16) => bus2_status2_addr_out,
- BUS_ADDR_OUT(5*16+15 downto 5*16) => bus_command_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => bus2_debug_addr_out,
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => bus2_status2_addr_out,
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => bus_command_addr,
BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out,
- BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_status_data_out,
- BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_control_data_out,
- BUS_DATA_OUT(3*32+31 downto 3*32) => bus2_debug_data_out,
- BUS_DATA_OUT(4*32+31 downto 4*32) => bus2_status2_data_out,
- BUS_DATA_OUT(5*32+31 downto 5*32) => bus_command_data_out,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_debug_data_out,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_status2_data_out,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => bus_command_data_out,
BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out,
- BUS_READ_ENABLE_OUT(1) => bus2_status_read_enable_out,
- BUS_READ_ENABLE_OUT(2) => bus2_control_read_enable_out,
- BUS_READ_ENABLE_OUT(3) => bus2_debug_read_enable_out,
- BUS_READ_ENABLE_OUT(4) => bus2_status2_read_enable_out,
- BUS_READ_ENABLE_OUT(5) => bus_command_read,
+ BUS_READ_ENABLE_OUT(1) => bus2_debug_read_enable_out,
+ BUS_READ_ENABLE_OUT(2) => bus2_status2_read_enable_out,
+ BUS_READ_ENABLE_OUT(3) => bus_command_read,
BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out,
- BUS_WRITE_ENABLE_OUT(1) => bus2_status_write_enable_out,
- BUS_WRITE_ENABLE_OUT(2) => bus2_control_write_enable_out,
- BUS_WRITE_ENABLE_OUT(3) => bus2_debug_write_enable_out,
- BUS_WRITE_ENABLE_OUT(4) => bus2_status2_write_enable_out,
- BUS_WRITE_ENABLE_OUT(5) => bus_command_write,
+ BUS_WRITE_ENABLE_OUT(1) => bus2_debug_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(2) => bus2_status2_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(3) => bus_command_write,
BUS_TIMEOUT_OUT => open,
BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in,
- BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => bus2_control_data_in,
- BUS_DATA_IN(3*32+31 downto 3*32) => bus2_debug_data_in,
- BUS_DATA_IN(4*32+31 downto 4*32) => bus2_status2_data_in,
- BUS_DATA_IN(5*32+31 downto 5*32) => bus_command_data_in,
+ BUS_DATA_IN(1*32+31 downto 1*32) => bus2_debug_data_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => bus2_status2_data_in,
+ BUS_DATA_IN(3*32+31 downto 3*32) => bus_command_data_in,
BUS_DATAREADY_IN(0) => bus2_ram_ack_in,
- BUS_DATAREADY_IN(1) => bus2_status_ack_in,
- BUS_DATAREADY_IN(2) => bus2_control_ack_in,
- BUS_DATAREADY_IN(3) => bus2_debug_ack_in,
- BUS_DATAREADY_IN(4) => bus2_status2_ack_in,
- BUS_DATAREADY_IN(5) => bus_command_ack,
+ BUS_DATAREADY_IN(1) => bus2_debug_ack_in,
+ BUS_DATAREADY_IN(2) => bus2_status2_ack_in,
+ BUS_DATAREADY_IN(3) => bus_command_ack,
BUS_WRITE_ACK_IN(0) => bus2_ram_ack_in,
- BUS_WRITE_ACK_IN(1) => bus2_status_ack_in,
- BUS_WRITE_ACK_IN(2) => bus2_control_ack_in,
- BUS_WRITE_ACK_IN(3) => bus2_debug_ack_in,
- BUS_WRITE_ACK_IN(4) => bus2_status2_ack_in,
- BUS_WRITE_ACK_IN(5) => bus_command_ack,
+ BUS_WRITE_ACK_IN(1) => bus2_debug_ack_in,
+ BUS_WRITE_ACK_IN(2) => bus2_status2_ack_in,
+ BUS_WRITE_ACK_IN(3) => bus_command_ack,
BUS_NO_MORE_DATA_IN(0) => bus2_ram_nack_in,
BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => bus2_control_nack_in,
+ BUS_NO_MORE_DATA_IN(2) => '0',
BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_NO_MORE_DATA_IN(5) => '0',
BUS_UNKNOWN_ADDR_IN(0) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => bus2_status_nack_in,
- BUS_UNKNOWN_ADDR_IN(2) => bus_command_nack,
- BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_nack_in,
- BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_nack_in,
- BUS_UNKNOWN_ADDR_IN(5) => bus_command_retry
+ BUS_UNKNOWN_ADDR_IN(1) => bus2_debug_nack_in,
+ BUS_UNKNOWN_ADDR_IN(2) => bus2_status2_nack_in,
+ BUS_UNKNOWN_ADDR_IN(3) => bus_command_retry
);
end if;
end process;
-BUS2_STATUS_R : process begin
- wait until rising_edge(CLK_IN);
- bus2_status_data_in <= (others => '0');
- bus2_status_ack_in <= '0';
- bus2_status_nack_in <= '0';
-
- if(bus2_status_read_enable_out='1') then
- if(bus2_status_addr_out(4 downto 0) = "00000") then
- bus2_status_data_in(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0);
- bus2_status_ack_in <= '1';
- else
- bus2_status_nack_in <= '1';
- end if;
- end if;
- if(bus2_status_write_enable_out='1') then
- bus2_status_nack_in <= '1';
- end if;
-end process;
-
-
BUS2_COMMAND_RW : process begin
wait until rising_edge(CLK_IN);
bus_command_data_in(1) <= jtag_check1_active;
when M26C_CMD_REMOVE_SENSOR =>
bus_command_data_in(MAX_NUMCHIPS -1 downto 0) <= removed_chips;
- when M26C_CMD_INSERT_SENSOR =>
- bus_command_data_in(MAX_NUMCHIPS -1 downto 0) <= removed_chips;
when M26C_CMD_SET_NUMCHIPS_CONFIGURED =>
bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured);
when M26C_CMD_GET_NUMCHIPS_ACTIVE =>
bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_set_data_time);
when M26C_CMD_GET_RUN_COUNT =>
bus_command_data_in(31 downto 0) <= std_logic_vector(run_counter);
+ when M26C_CMD_GET_CRC_STATUS =>
+ bus_command_data_in(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0);
+ when M26C_CMD_SET_RAMBASE =>
+ bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr;
when M26C_CMD_SET_CSOPTIONS =>
bus_command_data_in(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest
when M26C_CMD_SET_DELAY_EXPECTED_VALUES =>
jtag_check1_active <= bus_command_data_out(1);
when M26C_CMD_REMOVE_SENSOR =>
if m26cs_stopped = '1' then
- if(unsigned(bus_command_data_out)<MAX_NUMCHIPS) then
- removed_chips(to_integer(unsigned(bus_command_data_out))) <= '1';
+ if(unsigned(bus_command_data_out(15 downto 0))<MAX_NUMCHIPS) then
+ removed_chips(to_integer(unsigned(bus_command_data_out(15 downto 0)))) <= bus_command_data_out(31);
end if;
else
bus_command_ack <= '0';
bus_command_retry <= '1';
end if;
- when M26C_CMD_INSERT_SENSOR =>
- if m26cs_stopped = '1' then
- if(unsigned(bus_command_data_out)<MAX_NUMCHIPS) then
- removed_chips(to_integer(unsigned(bus_command_data_out))) <= '0';
- end if;
- else
- bus_command_ack <= '0';
- bus_command_retry <= '1';
- end if;
when M26C_CMD_SET_NUMCHIPS_CONFIGURED =>
numchips_configured <= unsigned(bus_command_data_out(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0));
when M26C_CMD_SET_BREAKPOINTS =>
jtag_set_data_time <= unsigned(bus_command_data_out(9 downto 0));
when M26C_CMD_COPY_TO_STATUS2 =>
jtag_status2_copy_request_strobe <= '1';
+ when M26C_CMD_SET_RAMBASE =>
+ ram1a_a1_base_addr <= bus_command_data_out(MAX_NUMCHIPS_LD-1 downto 0);
when M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER =>
ram1b1c_copy_trigger_strobe(3 downto 0) <= bus_command_data_out(3 downto 0);
-- trigger on: bit 0 => read error, 1 => write error, 2 => data changed, 3=>next run
-BUS2_CONTROL_RW : process begin
- wait until rising_edge(CLK_IN);
- bus2_control_ack_in <= '0';
- bus2_control_nack_in <= '0';
- bus2_control_data_in <= (others => '0');
-
- if(bus2_control_write_enable_out='1') then
- if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
- ram1a_a1_base_addr <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0);
- bus2_control_ack_in <= '1';
- else
- bus2_control_nack_in <= '1';
- end if;
- elsif(bus2_control_read_enable_out='1') then
- if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
- bus2_control_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr;
- bus2_control_ack_in <= '1';
- else
- bus2_control_nack_in <= '1';
- end if;
- end if;
-end process;
-
-
BUS2_DEBUG_R : process begin
wait until rising_edge(CLK_IN);
bus2_debug_ack_in <= '0';
-- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
-- 5: DATA_CHANGED, 6: reserved, 7: reserved
if(bus2_status2_addr_out(4) = '1') then -- ram3b
- ram3b_a2_rel_addr <= bus2_status_addr_out(3 downto 0);
+ ram3b_a2_rel_addr <= bus2_status2_addr_out(3 downto 0);
bus2_status2_read_ram3b <= '1';
else
bus2_status2_ack_in <= '1';
constant CMD_UPDATE_DR : std_logic_vector (3 downto 0) := x"6";
constant CMD_RESET_JTAG : std_logic_vector (3 downto 0) := x"7";
constant CMD_READ_TDO : std_logic_vector (3 downto 0) := x"8";
--- constant M26C_CMD_NONE : std_logic_vector (7 downto 0) := x"00";
-constant M26C_CMD_START : std_logic_vector (7 downto 0) := x"09";
--- constant M26C_CMD_STOP : std_logic_vector (7 downto 0) := x"0A";
-constant M26C_CMD_REMOVE_SENSOR : std_logic_vector (7 downto 0) := x"10";
-constant M26C_CMD_INSERT_SENSOR : std_logic_vector (7 downto 0) := x"11";
--- constant M26C_CMD_GET_NUMCHIPS_CONFIGURED:std_logic_vector (7 downto 0) := x"12";
-constant M26C_CMD_GET_NUMCHIPS_ACTIVE : std_logic_vector (7 downto 0) := x"13";
-constant M26C_CMD_GET_TRIGGER_COUNT : std_logic_vector (7 downto 0) := x"14";
-constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"1c";
--- constant M26C_CMD_GET_REMOVED : std_logic_vector (7 downto 0) := x"1d";
--- constant M26C_CMD_GET_REMOVED32 : std_logic_vector (7 downto 0) := x"1e";
--- constant M26C_CMD_GET_WRITE_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"20";
--- constant M26C_CMD_GET_WRITE_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"21";
--- constant M26C_CMD_GET_WRITE_DATA_CHANGED_COUNTER :std_logic_vector (7 downto 0) := x"22";
--- constant M26C_CMD_GET_READ_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"23";
--- constant M26C_CMD_GET_READ_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"24";
--- constant M26C_CMD_GET_JTAG_M26_DEV_ID :std_logic_vector (7 downto 0) := x"30";
-constant M26C_CMD_SET_NUMCHIPS_CONFIGURED : std_logic_vector (7 downto 0) := x"33";
-constant M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"40";
--- constant M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"41";
-constant M26C_CMD_SET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"42";
--- constant M26C_CMD_GET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"43";
-constant M26C_CMD_SET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"44";
--- constant M26C_CMD_GET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"45";
-constant M26C_CMD_SET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"46";
--- constant M26C_CMD_GET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"47";
-constant M26C_CMD_SET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"48";
--- constant M26C_CMD_GET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"49";
-constant M26C_CMD_SET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4a";
--- constant M26C_CMD_GET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4b";
-constant M26C_CMD_SET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4c";
--- constant M26C_CMD_GET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4d";
-constant M26C_CMD_GET_RUN_COUNT : std_logic_vector(7 downto 0) := x"50";
--- constant M26C_CMD_GET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"52";
-constant M26C_CMD_SET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"53";
--- constant M26C_CMD_START_CHECK1 : std_logic_vector (7 downto 0) := x"60";
-constant M26C_CMD_COPY_TO_STATUS2 : std_logic_vector (7 downto 0) := x"63";
-constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER : std_logic_vector (7 downto 0) := x"64"; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
--- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR : std_logic_vector (7 downto 0) := x"6a"; --
--- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR : std_logic_vector (7 downto 0) := x"6b"; --
--- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED : std_logic_vector (7 downto 0) := x"6c"; --
--- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW : std_logic_vector (7 downto 0) := x"6d"; --
-constant M26C_CMD_SET_CSOPTIONS : std_logic_vector (7 downto 0) := x"65"; -- bit 0 => skip BYPASS CHAINTEST
--- constant M26C_CMD_GET_CSOPTIONS : std_logic_vector (7 downto 0) := x"66"; -- bit 0 => skip BYPASS CHAINTEST
-constant M26C_CMD_SET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"67"; -- bits 1 downto 0 as unsigned number of TCK clocks expected values are delayed
--- constant M26C_CMD_GET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"68";
--- constant M26C_CMD_GET_ACTIVITY : std_logic_vector (7 downto 0) := x"69"; -- bit 0 => jtag_refresh_active, bit 1 => jtag_check1_active.
+
+constant M26C_CMD_START : std_logic_vector (7 downto 0) := x"40";
+constant M26C_CMD_REMOVE_SENSOR : std_logic_vector (7 downto 0) := x"41";
+constant M26C_CMD_GET_NUMCHIPS_ACTIVE : std_logic_vector (7 downto 0) := x"11";
+constant M26C_CMD_GET_TRIGGER_COUNT : std_logic_vector (7 downto 0) := x"12";
+constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"13";
+constant M26C_CMD_GET_CRC_STATUS : std_logic_vector (7 downto 0) := x"14";
+constant M26C_CMD_SET_NUMCHIPS_CONFIGURED : std_logic_vector (7 downto 0) := x"00";
+constant M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"01";
+constant M26C_CMD_SET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"02";
+constant M26C_CMD_SET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"03";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"04";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"05";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"06";
+constant M26C_CMD_SET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"07";
+constant M26C_CMD_GET_RUN_COUNT : std_logic_vector (7 downto 0) := x"10";
+constant M26C_CMD_SET_BREAKPOINTS : std_logic_vector (7 downto 0) := x"50";
+constant M26C_CMD_COPY_TO_STATUS2 : std_logic_vector (7 downto 0) := x"51";
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER : std_logic_vector (7 downto 0) := x"52"; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+constant M26C_CMD_SET_CSOPTIONS : std_logic_vector (7 downto 0) := x"42"; -- bit 0 => skip BYPASS CHAINTEST
+constant M26C_CMD_SET_RAMBASE : std_logic_vector (7 downto 0) := x"43"; -- bit 0 => skip BYPASS CHAINTEST
+constant M26C_CMD_SET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"08"; -- bits 1 downto 0 as unsigned number of TCK clocks expected values are delayed
-- 0xb100 - 0xb2ff
-- RAM: 0xb000 - 0xb0ff
jspc29 / jtag_mvd.git / commitdiff