TDC version v1.6.3 brought uptodate with the new config file

diff --git a/tdc_releases/tdc_v1.6.3/Channel.vhd b/tdc_releases/tdc_v1.6.3/Channel.vhd
index f9e5a1223525dea874ec46caa73db1d717bde7bc..e9d0494667fbb7e34fd56aa8723b07db5d3f4b88 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Channel.vhd
+++ b/tdc_releases/tdc_v1.6.3/Channel.vhd
@@ -155,7 +155,7 @@ begin
       FIFO_WRITE_OUT        => fifo_write_i,
       CHANNEL_200_DEBUG     => channel_200_debug_i);
 
-  Buffer_128 : if RING_BUFFER_SIZE = 128 generate
+  Buffer_128 : if RING_BUFFER_SIZE = 3 generate
     The_Buffer : FIFO_36x128_OutReg
       port map (
         Data        => ch_data_i,
@@ -168,7 +168,7 @@ begin
         Full        => buf_full_i);
   end generate Buffer_128;
 
-  Buffer_64 : if RING_BUFFER_SIZE = 64 generate
+  Buffer_64 : if RING_BUFFER_SIZE = 1 generate
     The_Buffer : FIFO_36x64_OutReg
       port map (
         Data        => ch_data_i,
@@ -181,7 +181,7 @@ begin
         Full        => buf_full_i);
   end generate Buffer_64;
 
-  Buffer_32 : if RING_BUFFER_SIZE = 32 generate
+  Buffer_32 : if RING_BUFFER_SIZE = 0 generate
     The_Buffer : FIFO_36x32_OutReg
       port map (
         Data        => ch_data_i,
@@ -194,19 +194,6 @@ begin
         Full        => buf_full_i);
   end generate Buffer_32;
 
-  Buffer_16 : if RING_BUFFER_SIZE = 16 generate
-    The_Buffer : FIFO_36x16_OutReg
-      port map (
-        Data        => ch_data_i,
-        Clock       => CLK_100,
-        WrEn        => ch_data_valid_i,
-        RdEn        => READ_EN_IN,
-        Reset       => RESET_100,
-        Q           => buf_data_i,
-        Empty       => buf_empty_i,
-        Full        => buf_full_i);
-  end generate Buffer_16;
-
   FIFO_DATA_OUT         <= buf_data_i;
   FIFO_DATA_VALID_OUT   <= buf_data_valid_i;
   FIFO_EMPTY_OUT        <= buf_empty_i;

diff --git a/tdc_releases/tdc_v1.6.3/Channel_200.vhd b/tdc_releases/tdc_v1.6.3/Channel_200.vhd
index 1999cae6e2cdfa3895f67c7079982e316d12413e..b73e24a3a2b94e94906d3cd5a016101c95aa6946 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Channel_200.vhd
+++ b/tdc_releases/tdc_v1.6.3/Channel_200.vhd
@@ -5,7 +5,7 @@
 -- File       : Channel_200.vhd
 -- Author     : c.ugur@gsi.de
 -- Created    : 2012-08-28
--- Last update: 2014-05-07
+-- Last update: 2014-07-16
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -281,7 +281,7 @@ begin  -- Channel_200
       BINARY_CODE_OUT => encoder_data_out_i,
       ENCODER_DEBUG   => encoder_debug_i);
 
-  RingBuffer_128 : if RING_BUFFER_SIZE = 128 generate
+  RingBuffer_128 : if RING_BUFFER_SIZE = 3 generate
     FIFO : FIFO_DC_36x128_OutReg
       port map (
         Data       => ringBuffer_data_in_i,
@@ -297,7 +297,7 @@ begin  -- Channel_200
         AlmostFull => ringBuffer_almost_full_i);
   end generate RingBuffer_128;
 
-  RingBuffer_64 : if RING_BUFFER_SIZE = 64 generate
+  RingBuffer_64 : if RING_BUFFER_SIZE = 1 generate
     FIFO : FIFO_DC_36x64_OutReg
       port map (
         Data       => ringBuffer_data_in_i,
@@ -313,7 +313,7 @@ begin  -- Channel_200
         AlmostFull => ringBuffer_almost_full_i);
   end generate RingBuffer_64;
 
-  RingBuffer_32 : if RING_BUFFER_SIZE = 32 generate
+  RingBuffer_32 : if RING_BUFFER_SIZE = 0 generate
     FIFO : FIFO_DC_36x32_OutReg
       port map (
         Data       => ringBuffer_data_in_i,
@@ -329,22 +329,6 @@ begin  -- Channel_200
         AlmostFull => ringBuffer_almost_full_i);
   end generate RingBuffer_32;
 
-  RingBuffer_16 : if RING_BUFFER_SIZE = 16 generate
-    FIFO : FIFO_DC_36x16_OutReg
-      port map (
-        Data       => ringBuffer_data_in_i,
-        WrClock    => CLK_200,
-        RdClock    => CLK_100,
-        WrEn       => ringBuffer_wr_en_i,
-        RdEn       => ringBuffer_rd_en_i,
-        Reset      => RESET_100,
-        RPReset    => RESET_100,
-        Q          => ringBuffer_data_out_i,
-        Empty      => ringBuffer_empty_i,
-        Full       => ringBuffer_full_i,
-        AlmostFull => ringBuffer_almost_full_i);
-  end generate RingBuffer_16;
-
   ringBuffer_almost_full_sync <= ringBuffer_almost_full_i                            when rising_edge(CLK_100);
   ringBuffer_rd_en_i          <= ringBuffer_rd_data_i or ringBuffer_almost_full_sync when rising_edge(CLK_100);
 

diff --git a/tdc_releases/tdc_v1.6.3/unimportant_lines_constraints.lpf b/tdc_releases/tdc_v1.6.3/unimportant_lines_constraints.lpf
index 91e28db2c332b165f2058b98c13c6e6d7910a2a4..2d469dbb3ae79b89caa3e70f771bee9212134f19 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/unimportant_lines_constraints.lpf
+++ b/tdc_releases/tdc_v1.6.3/unimportant_lines_constraints.lpf
@@ -18,10 +18,8 @@ MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" T
 MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 3 X;
 MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 3 X;
 
-MULTICYCLE TO CELL "THE_TDC/TheFirstReadout/TW_pre*" 4 x;
-MULTICYCLE TO CELL "THE_TDC/TheFirstReadout/TW_post*" 4 x;
-MULTICYCLE TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/TW_pre*" 4 x;
-MULTICYCLE TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/TW_post*" 4 x;
+MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x;
+MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x;
 
 
 
@@ -33,8 +31,7 @@ MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;
 
 ## Maybe effective
 
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheFirstReadout/rd_en*" 2 X;
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/rd_en*" 2 X;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X;