--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.ALL;
+
+package adcmv3_components is
+
+-------------------------------------------------------------------------------
+-- Components by Michael Boehmer
+-------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- TRBNet interfaces
+-------------------------------------------------------------------------------
+component slave_bus
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_TIMEOUT_IN : in std_logic;
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ SDA_IN : in std_logic;
+ SDA_OUT : out std_logic;
+ SCL_IN : in std_logic;
+ SCL_OUT : out std_logic;
+ SPI_CS_OUT : out std_logic;
+ SPI_SCK_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic;
+ SPI_SDO_OUT : out std_logic);
+end component slave_bus;
+
+
+component slv_register
+ generic (
+ RESET_VALUE : std_logic_vector(31 downto 0));
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ BUSY_IN : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ REG_DATA_IN : in std_logic_vector(31 downto 0);
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT : out std_logic_vector(31 downto 0));
+end component slv_register;
+
+
+component slv_ped_thr_mem
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);
+ MEM_CLK_IN : in std_logic;
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);
+ STAT : out std_logic_vector(31 downto 0));
+end component slv_ped_thr_mem;
+
+-------------------------------------------------------------------------------
+-- I2C INterfaces
+-------------------------------------------------------------------------------
+
+component i2c_master
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SDA_IN : in std_logic;
+ SDA_OUT : out std_logic;
+ SCL_IN : in std_logic;
+ SCL_OUT : out std_logic;
+ STAT : out std_logic_vector(31 downto 0));
+end component i2c_master;
+
+
+component I2C_GSTART
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ START_IN : in std_logic;
+ DOSTART_IN : in std_logic;
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);
+ SDONE_OUT : out std_logic;
+ SOK_OUT : out std_logic;
+ SDA_IN : in std_logic;
+ SCL_IN : in std_logic;
+ R_SCL_OUT : out std_logic;
+ S_SCL_OUT : out std_logic;
+ R_SDA_OUT : out std_logic;
+ S_SDA_OUT : out std_logic;
+ BSM_OUT : out std_logic_vector(3 downto 0));
+end component I2C_GSTART;
+
+
+component i2c_sendb
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ DOBYTE_IN : in std_logic;
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);
+ I2C_BYTE_IN : in std_logic_vector(8 downto 0);
+ I2C_BACK_OUT : out std_logic_vector(8 downto 0);
+ SDA_IN : in std_logic;
+ R_SDA_OUT : out std_logic;
+ S_SDA_OUT : out std_logic;
+ R_SCL_OUT : out std_logic;
+ S_SCL_OUT : out std_logic;
+ BDONE_OUT : out std_logic;
+ BOK_OUT : out std_logic;
+ BSM_OUT : out std_logic_vector(3 downto 0));
+end component i2c_sendb;
+
+
+component i2c_slim
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ I2C_GO_IN : in std_logic;
+ ACTION_IN : in std_logic;
+ I2C_SPEED_IN : in std_logic_vector(5 downto 0);
+ I2C_ADR_IN : in std_logic_vector(7 downto 0);
+ I2C_CMD_IN : in std_logic_vector(7 downto 0);
+ I2C_DW_IN : in std_logic_vector(7 downto 0);
+ I2C_DR_OUT : out std_logic_vector(7 downto 0);
+ STATUS_OUT : out std_logic_vector(7 downto 0);
+ I2C_BUSY_OUT : out std_logic;
+ SDA_IN : in std_logic;
+ SDA_OUT : out std_logic;
+ SCL_IN : in std_logic;
+ SCL_OUT : out std_logic;
+ STAT : out std_logic_vector(31 downto 0));
+end component i2c_slim;
+
+end package;
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity I2C_GSTART is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ DOSTART_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of I2C_GSTART is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ P_SCL,\r
+ WCTR0,\r
+ P_SDA,\r
+ WCTR1,\r
+ P_CHK,\r
+ S_CHK0,\r
+ RS_SDA,\r
+ S_CHK1,\r
+ ERROR,\r
+ DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal bsm : std_logic_vector(3 downto 0);\r
+ signal cctr : std_logic_vector(7 downto 0); -- counter for bit length\r
+\r
+ signal cycdone_x : std_logic;\r
+ signal cycdone : std_logic; -- one counter period done\r
+\r
+ signal load_cyc_x : std_logic;\r
+ signal load_cyc : std_logic;\r
+ signal dec_cyc_x : std_logic;\r
+ signal dec_cyc : std_logic;\r
+ signal sdone_x : std_logic;\r
+ signal sdone : std_logic; -- Start/Stop done\r
+ signal sok_x : std_logic;\r
+ signal sok : std_logic; -- Start/Stop OK\r
+\r
+ signal r_scl : std_logic;\r
+ signal s_scl : std_logic;\r
+ signal r_sda : std_logic;\r
+ signal s_sda : std_logic;\r
+\r
+-- Moduls\r
+\r
+begin\r
+\r
+-- Countdown for one half of SCL (adjustable clock width)\r
+ THE_CYC_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ cctr <= (others => '0');\r
+ elsif( load_cyc = '1' ) then\r
+ cctr <= i2c_speed_in;\r
+ elsif( dec_cyc = '1' ) then\r
+ cctr <= cctr - 1;\r
+ end if;\r
+ end if;\r
+ end process THE_CYC_CTR_PROC;\r
+\r
+-- end of cycle recognition\r
+ cycdone_x <= '1' when (cctr = x"00") else '0';\r
+\r
+-- The main state machine\r
+-- State memory process\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if ( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ load_cyc <= '0';\r
+ dec_cyc <= '0';\r
+ sdone <= '0';\r
+ sok <= '0';\r
+ cycdone <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ load_cyc <= load_cyc_x;\r
+ dec_cyc <= dec_cyc_x;\r
+ sdone <= sdone_x;\r
+ sok <= sok_x;\r
+ cycdone <= cycdone_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process(CURRENT_STATE, dostart_in, start_in, sda_in, scl_in, cycdone)\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ load_cyc_x <= '0';\r
+ dec_cyc_x <= '0';\r
+ sdone_x <= '0';\r
+ sok_x <= '1';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then\r
+ NEXT_STATE <= S_CHK0; -- generate a start condition\r
+ load_cyc_x <= '1';\r
+ elsif( (dostart_in = '1') and (start_in = '0') ) then\r
+ NEXT_STATE <= P_SCL; -- generate a stop condition\r
+ load_cyc_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when P_SCL => NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ NEXT_STATE <= RS_SDA;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when RS_SDA => NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then\r
+ NEXT_STATE <= S_CHK1;\r
+ elsif( (cycdone = '1') and (start_in = '0') ) then\r
+ NEXT_STATE <= P_SDA;\r
+ load_cyc_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when P_SDA => NEXT_STATE <= WCTR1;\r
+ dec_cyc_x <= '1';\r
+ when WCTR1 => if( (cycdone = '1') ) then\r
+ NEXT_STATE <= P_CHK;\r
+ else\r
+ NEXT_STATE <= WCTR1;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ sdone_x <= '1';\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when ERROR => if( dostart_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sdone_x <= '1';\r
+ sok_x <= '0';\r
+ end if;\r
+ when DONE => if( dostart_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ sdone_x <= '1';\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
+\r
+-- Output decoding\r
+ DECODE: process(CURRENT_STATE)\r
+ begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= x"0";\r
+ when S_CHK0 => bsm <= x"1";\r
+ when RS_SDA => bsm <= x"2";\r
+ when P_SCL => bsm <= x"3";\r
+ when WCTR0 => bsm <= x"4";\r
+ when S_CHK1 => bsm <= x"5";\r
+ when P_SDA => bsm <= x"6";\r
+ when WCTR1 => bsm <= x"7";\r
+ when P_CHK => bsm <= x"8";\r
+ when DONE => bsm <= x"9";\r
+ when ERROR => bsm <= x"e";\r
+ when others => bsm <= x"f";\r
+ end case;\r
+ end process DECODE;\r
+\r
+ S_R_GEN: process(CURRENT_STATE)\r
+ begin\r
+ if ( CURRENT_STATE = P_SCL ) then\r
+ r_scl <= '0';\r
+ s_scl <= '1';\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ elsif( CURRENT_STATE = RS_SDA ) then\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '1';\r
+ s_sda <= '0';\r
+ elsif( CURRENT_STATE = P_SDA ) then\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '0';\r
+ s_sda <= '1';\r
+ else\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ end if;\r
+ end process S_R_GEN;\r
+\r
+-- Outputs\r
+ r_scl_out <= r_scl;\r
+ s_scl_out <= s_scl;\r
+ r_sda_out <= r_sda;\r
+ s_sda_out <= s_sda;\r
+ sdone_out <= sdone;\r
+ sok_out <= sok;\r
+\r
+-- Debug\r
+ bsm_out <= bsm;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity i2c_master is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of i2c_master is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ RD_BSY,\r
+ WR_BSY,\r
+ RD_RDY,\r
+ WR_RDY,\r
+ RD_ACK,\r
+ WR_ACK,\r
+ DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+ signal reg_busy : std_logic;\r
+\r
+ signal status_data : std_logic_vector(31 downto 0);\r
+ signal i2c_debug : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- I2C master --\r
+---------------------------------------------------------\r
+\r
+ THE_I2C_SLIM: i2c_slim\r
+ port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => reg_slv_data_in(31),\r
+ ACTION_IN => reg_slv_data_in(30),\r
+ I2C_SPEED_IN => reg_slv_data_in(29 downto 24),\r
+ I2C_ADR_IN => reg_slv_data_in(23 downto 16),\r
+ I2C_CMD_IN => reg_slv_data_in(15 downto 8),\r
+ I2C_DW_IN => reg_slv_data_in(7 downto 0),\r
+ I2C_DR_OUT => status_data(7 downto 0),\r
+ STATUS_OUT => status_data(31 downto 24),\r
+ I2C_BUSY_OUT => reg_busy,\r
+ -- I2C connections\r
+ SDA_IN => sda_in,\r
+ SDA_OUT => sda_out,\r
+ SCL_IN => scl_in,\r
+ SCL_OUT => scl_out,\r
+ -- Debug\r
+ STAT => i2c_debug\r
+ );\r
+\r
+ status_data(23 downto 21) <= (others => '0');\r
+ status_data(20 downto 16) <= i2c_debug(4 downto 0);\r
+ status_data(15 downto 8) <= (others => '0');\r
+\r
+-- Fake\r
+ stat <= i2c_debug;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ when RD_ACK => if ( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if ( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY => if ( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY => if ( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+ THE_WRITE_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_in <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ reg_slv_data_in <= slv_data_in;\r
+ end if;\r
+ end if;\r
+ end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+ THE_READ_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= status_data;\r
+ end if;\r
+ end if;\r
+ end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+ slv_ack_out <= slv_ack;\r
+ slv_busy_out <= slv_busy;\r
+ slv_data_out <= reg_slv_data_out;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity i2c_sendb is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector( 7 downto 0 );\r
+ I2C_BYTE_IN : in std_logic_vector( 8 downto 0 );\r
+ I2C_BACK_OUT : out std_logic_vector( 8 downto 0 );\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector( 3 downto 0 )\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of i2c_sendb is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ LCL,\r
+ WCL,\r
+ LCH,\r
+ WCH,\r
+ FREE,\r
+ DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal bsm : std_logic_vector( 3 downto 0 );\r
+\r
+ signal inc_bit_x : std_logic;\r
+ signal inc_bit : std_logic; -- increment bit counter for byte to send\r
+ signal rst_bit_x : std_logic;\r
+ signal rst_bit : std_logic; -- reset bit counter for byte to send\r
+ signal load_cyc_x : std_logic;\r
+ signal load_cyc : std_logic; -- load cycle counter (SCL length)\r
+ signal dec_cyc_x : std_logic;\r
+ signal dec_cyc : std_logic; -- decrement cycle counter (SCL length)\r
+ signal load_sr_x : std_logic;\r
+ signal load_sr : std_logic; -- load output shift register\r
+ signal shift_o_x : std_logic;\r
+ signal shift_o : std_logic; -- output shift register control\r
+ signal shift_i_x : std_logic;\r
+ signal shift_i : std_logic; -- input shift register control\r
+ signal bdone_x : std_logic;\r
+ signal bdone : std_logic;\r
+ signal r_scl_x : std_logic;\r
+ signal r_scl : std_logic; -- output for SCL\r
+ signal s_scl_x : std_logic;\r
+ signal s_scl : std_logic; -- output for SCL\r
+\r
+ signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9)\r
+ signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length\r
+ signal bok : std_logic;\r
+ signal cycdone : std_logic; -- one counter period done\r
+ signal bytedone : std_logic; -- all bits sents\r
+ signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+ signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out\r
+ signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+ signal r_sda : std_logic; -- output for SDA\r
+ signal s_sda : std_logic; -- output for SDA\r
+ signal load : std_logic; -- delay register\r
+ signal i2c_d : std_logic; -- auxiliary register\r
+\r
+-- Moduls\r
+\r
+begin\r
+\r
+-- Bit counter (for byte to send)\r
+ THE_BIT_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ bctr <= (others => '0');\r
+ elsif( rst_bit = '1' ) then\r
+ bctr <= (others => '0');\r
+ elsif( inc_bit = '1' ) then\r
+ bctr <= bctr + 1;\r
+ end if;\r
+ end if;\r
+ end process THE_BIT_CTR_PROC;\r
+\r
+-- end of byte recognition\r
+ bytedone <= '1' when (bctr = x"9") else '0';\r
+\r
+-- Countdown for one half of SCL (adjustable clock width)\r
+ THE_CYC_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ cctr <= (others => '0');\r
+ elsif( load_cyc = '1' ) then\r
+ cctr <= i2c_speed_in;\r
+ elsif( dec_cyc = '1' ) then\r
+ cctr <= cctr - 1;\r
+ end if;\r
+ end if;\r
+ end process THE_CYC_CTR_PROC;\r
+\r
+-- end of cycle recognition\r
+ cycdone <= '1' when (cctr = x"00") else '0';\r
+\r
+-- Bit output\r
+ THE_BIT_OUT_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ out_sr <= (others => '0');\r
+ i2c_d <= '1';\r
+ elsif( load_sr = '1' ) then\r
+ out_sr <= i2c_byte_in;\r
+ i2c_d <= '1';\r
+ elsif( shift_o = '1' ) then\r
+ i2c_d <= out_sr(8);\r
+ out_sr(8 downto 0) <= out_sr(7 downto 0) & '0';\r
+ end if;\r
+ end if;\r
+ end process THE_BIT_OUT_PROC;\r
+\r
+-- Bit input\r
+ THE_BIT_IN_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ in_sr <= (others => '1');\r
+ elsif( shift_o = '1' ) then\r
+ in_sr(8 downto 1) <= in_sr(7 downto 0);\r
+ in_sr(0) <= sda_in;\r
+ end if;\r
+ end if;\r
+ end process THE_BIT_IN_PROC;\r
+\r
+-- Output register for readback data (could be reduced to SR_IN_INT)\r
+ THE_I2C_BACK_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ i2c_back <= (others => '1');\r
+ elsif( shift_i = '1' ) then\r
+ i2c_back(8 downto 1) <= in_sr(7 downto 0);\r
+ i2c_back(0) <= sda_in;\r
+ end if;\r
+ end if;\r
+ end process THE_I2C_BACK_PROC;\r
+\r
+-- ByteOK is the inverted ACK bit from readback data.\r
+ bok <= not i2c_back(0); -- BUG\r
+\r
+-- The main state machine\r
+-- State memory process\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1') then\r
+ CURRENT_STATE <= SLEEP;\r
+ inc_bit <= '0';\r
+ rst_bit <= '0';\r
+ load_cyc <= '0';\r
+ dec_cyc <= '0';\r
+ load_sr <= '0';\r
+ shift_o <= '0';\r
+ shift_i <= '0';\r
+ bdone <= '0';\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ inc_bit <= inc_bit_x;\r
+ rst_bit <= rst_bit_x;\r
+ load_cyc <= load_cyc_x;\r
+ dec_cyc <= dec_cyc_x;\r
+ load_sr <= load_sr_x;\r
+ shift_o <= shift_o_x;\r
+ shift_i <= shift_i_x;\r
+ bdone <= bdone_x;\r
+ r_scl <= r_scl_x;\r
+ s_scl <= s_scl_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process(CURRENT_STATE, dobyte_in, cycdone, bytedone)\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ inc_bit_x <= '0';\r
+ rst_bit_x <= '0';\r
+ load_cyc_x <= '0';\r
+ dec_cyc_x <= '0';\r
+ load_sr_x <= '0';\r
+ shift_o_x <= '0';\r
+ shift_i_x <= '0';\r
+ bdone_x <= '0';\r
+ r_scl_x <= '0';\r
+ s_scl_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( dobyte_in = '1' ) then\r
+ NEXT_STATE <= LCL;\r
+ inc_bit_x <= '1';\r
+ load_cyc_x <= '1';\r
+ shift_o_x <= '1';\r
+ r_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ load_sr_x <= '1';\r
+ end if;\r
+ when LCL => NEXT_STATE <= WCL;\r
+ dec_cyc_x <= '1';\r
+ when WCL => if( cycdone = '1' ) then\r
+ NEXT_STATE <= LCH;\r
+ load_cyc_x <= '1';\r
+ s_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCL;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when LCH => NEXT_STATE <= WCH;\r
+ dec_cyc_x <= '1';\r
+ when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then\r
+ NEXT_STATE <= LCL;\r
+ inc_bit_x <= '1';\r
+ load_cyc_x <= '1';\r
+ shift_o_x <= '1';\r
+ r_scl_x <= '1';\r
+ elsif( (cycdone = '1') and (bytedone = '1') ) then\r
+ NEXT_STATE <= FREE;\r
+ shift_o_x <= '1';\r
+ shift_i_x <= '1';\r
+ r_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCH;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when FREE => NEXT_STATE <= DONE;\r
+ rst_bit_x <= '1';\r
+ bdone_x <= '1';\r
+ when DONE => if( dobyte_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ rst_bit_x <= '1';\r
+ bdone_x <= '1';\r
+ end if;\r
+ -- Just in case...\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
+\r
+-- Output decoding\r
+ DECODE: process(CURRENT_STATE)\r
+ begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= x"0";\r
+ when LCL => bsm <= x"1";\r
+ when WCL => bsm <= x"2";\r
+ when LCH => bsm <= x"3";\r
+ when WCH => bsm <= x"4";\r
+ when FREE => bsm <= x"5";\r
+ when DONE => bsm <= x"6";\r
+ when others => bsm <= x"f";\r
+ end case;\r
+ end process DECODE;\r
+\r
+-- SCL and SDA output pulses\r
+ THE_SDA_OUT_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ load <= '0'; -- was a bug, found 081008\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ else\r
+ load <= shift_o;\r
+ r_sda <= load and not i2c_d;\r
+ s_sda <= load and i2c_d;\r
+ end if;\r
+ end if;\r
+ end process THE_SDA_OUT_PROC;\r
+\r
+-- Outputs\r
+ r_scl_out <= r_scl;\r
+ s_scl_out <= s_scl;\r
+ r_sda_out <= r_sda;\r
+ s_sda_out <= s_sda;\r
+\r
+ i2c_back_out <= i2c_back;\r
+\r
+ bdone_out <= bdone;\r
+ bok_out <= bok;\r
+\r
+-- Debugging\r
+ bsm_out <= bsm;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- BUG: does alway set bit 0 of address byte to zero !!!!\r
+-- REMARK: this is not a bug, but a feature....\r
+\r
+entity i2c_slim is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+end i2c_slim;\r
+\r
+architecture Behavioral of i2c_slim is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ LOADA,\r
+ GSTART,\r
+ SENDA,\r
+ LOADC,\r
+ SENDC,\r
+ LOADD,\r
+ SENDD,\r
+ GSTOP,\r
+ INC,\r
+ E_START,\r
+ E_ADDR,\r
+ E_CMD,\r
+ E_WD,\r
+ E_RSTART,\r
+ E_RADDR,\r
+ DONE,\r
+ FAILED,\r
+ CLRERR);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal bsm : std_logic_vector( 4 downto 0 );\r
+ signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle\r
+\r
+ signal start_x : std_logic;\r
+ signal start : std_logic; -- '0' => generate STOP, '1' => generate START\r
+ signal dostart_x : std_logic;\r
+ signal dostart : std_logic; -- trigger the GenStart module\r
+ signal dobyte_x : std_logic;\r
+ signal dobyte : std_logic; -- trigger the ByteSend module\r
+ signal i2c_done_x : std_logic;\r
+ signal i2c_done : std_logic; -- acknowledge signal to the outside world\r
+ signal running_x : std_logic;\r
+ signal running : std_logic; -- legacy\r
+\r
+ signal load_a_x : std_logic;\r
+ signal load_a : std_logic;\r
+ signal load_c_x : std_logic;\r
+ signal load_c : std_logic;\r
+ signal load_d_x : std_logic;\r
+ signal load_d : std_logic;\r
+\r
+ signal sdone : std_logic; -- acknowledge signal from GenStart module\r
+ signal sok : std_logic; -- status signal from GenStart module\r
+ signal bdone : std_logic; -- acknowledge signal from SendByte module\r
+ signal bok : std_logic; -- status signal from SendByte module\r
+ signal e_sf : std_logic; -- Start failed\r
+ signal e_anak : std_logic; -- Adress byte NAK\r
+ signal e_cnak : std_logic; -- Command byte NAK\r
+ signal e_dnak : std_logic; -- Data byte NAK\r
+ signal e_rsf : std_logic; -- Repeated Start failed\r
+ signal e_ranak : std_logic; -- Repeated Adress NAK\r
+ signal i2c_byte : std_logic_vector( 8 downto 0 );\r
+ signal i2c_dr : std_logic_vector( 8 downto 0 );\r
+\r
+ signal s_scl : std_logic;\r
+ signal r_scl : std_logic;\r
+ signal s_sda : std_logic;\r
+ signal r_sda : std_logic;\r
+ signal r_scl_gs : std_logic;\r
+ signal s_scl_gs : std_logic;\r
+ signal r_sda_gs : std_logic;\r
+ signal s_sda_gs : std_logic;\r
+ signal r_scl_sb : std_logic;\r
+ signal s_scl_sb : std_logic;\r
+ signal r_sda_sb : std_logic;\r
+ signal s_sda_sb : std_logic;\r
+\r
+ signal gs_debug : std_logic_vector(3 downto 0);\r
+\r
+ signal i2c_speed : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+ i2c_speed <= i2c_speed_in & "00";\r
+\r
+-- Read phase indicator\r
+ THE_PHASE_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ phase <= '0';\r
+ elsif( CURRENT_STATE = INC ) then\r
+ phase <= '1';\r
+ elsif( (CURRENT_STATE = DONE) or (CURRENT_STATE = SLEEP) ) then\r
+ phase <= '0';\r
+ end if;\r
+ end if;\r
+ end process THE_PHASE_PROC;\r
+\r
+-- The main state machine\r
+-- State memory process\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ start <= '0';\r
+ dostart <= '0';\r
+ dobyte <= '0';\r
+ i2c_done <= '0';\r
+ running <= '0';\r
+ load_a <= '0';\r
+ load_c <= '0';\r
+ load_d <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ start <= start_x;\r
+ dostart <= dostart_x;\r
+ dobyte <= dobyte_x;\r
+ i2c_done <= i2c_done_x;\r
+ running <= running_x;\r
+ load_a <= load_a_x;\r
+ load_c <= load_c_x;\r
+ load_d <= load_d_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process(CURRENT_STATE, i2c_go_in, sdone, sok, phase, bdone, bok, action_in)\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ start_x <= '0';\r
+ dostart_x <= '0';\r
+ dobyte_x <= '0';\r
+ i2c_done_x <= '0';\r
+ running_x <= '1';\r
+ load_a_x <= '0';\r
+ load_c_x <= '0';\r
+ load_d_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( i2c_go_in = '1' ) then\r
+ NEXT_STATE <= CLRERR;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ running_x <= '0';\r
+ end if;\r
+ when CLRERR => NEXT_STATE <= LOADA;\r
+ load_a_x <= '1';\r
+ when LOADA => NEXT_STATE <= GSTART;\r
+ start_x <= '1';\r
+ dostart_x <= '1';\r
+ when GSTART => if ( (sdone = '1') and (sok = '1') ) then\r
+ NEXT_STATE <= SENDA;\r
+ dobyte_x <= '1';\r
+ elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then\r
+ NEXT_STATE <= E_START; -- first START condition failed\r
+ elsif( (sdone = '1') and (sok = '0') and (phase = '1') ) then\r
+ NEXT_STATE <= E_RSTART; -- second START condition failed\r
+ else\r
+ NEXT_STATE <= GSTART;\r
+ start_x <= '1';\r
+ dostart_x <= '1';\r
+ end if;\r
+ when E_START => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when E_RSTART => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= LOADC; -- I2C write\r
+ load_c_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then\r
+ NEXT_STATE <= LOADC; -- I2C read, send register address\r
+ load_c_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then\r
+ NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
+ load_d_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then\r
+ NEXT_STATE <= E_ADDR; -- first address phase failed\r
+ elsif( (bdone = '1') and (bok = '0') and (phase = '1') ) then\r
+ NEXT_STATE <= E_RADDR; -- second address phase failed\r
+ else\r
+ NEXT_STATE <= SENDA;\r
+ dobyte_x <= '1';\r
+ end if;\r
+ when E_ADDR => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when E_RADDR => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when LOADC => NEXT_STATE <= SENDC;\r
+-- dobyte_x <= '1';\r
+ when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= LOADD; -- I2C write, prepare data\r
+ load_d_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C read, first phase ends\r
+ dostart_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '0') ) then\r
+ NEXT_STATE <= E_CMD; -- command phase failed\r
+ else\r
+ NEXT_STATE <= SENDC;\r
+ dobyte_x <= '1';\r
+ end if;\r
+ when E_CMD => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when LOADD => NEXT_STATE <= SENDD;\r
+ when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C write, data phase failed\r
+ dostart_x <= '1';\r
+ elsif( (bdone = '1') and (action_in = '1') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C read, data phase\r
+ dostart_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then\r
+ NEXT_STATE <= E_WD; -- I2C write, data phase failed\r
+ else\r
+ NEXT_STATE <= SENDD;\r
+ dobyte_x <= '1';\r
+ end if;\r
+ when E_WD => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= DONE;\r
+ elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ elsif( (sdone = '1') and (action_in = '1') and (phase = '0') ) then\r
+ NEXT_STATE <= INC;\r
+ else\r
+ NEXT_STATE <= GSTOP;\r
+ dostart_x <= '1';\r
+ end if;\r
+ when INC => NEXT_STATE <= LOADA;\r
+ load_a_x <= '1';\r
+ when FAILED => if( sdone = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ i2c_done_x <= '1';\r
+ running_x <= '0';\r
+ else\r
+ NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ end if;\r
+ when DONE => if( i2c_go_in = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ i2c_done_x <= '1';\r
+ running_x <= '0';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ -- Just in case...\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
+\r
+-- Output decoding\r
+ DECODE: process(CURRENT_STATE)\r
+ begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= b"00000"; -- 00\r
+ when CLRERR => bsm <= b"01100"; -- 0c\r
+ when LOADA => bsm <= b"00001"; -- 01\r
+ when GSTART => bsm <= b"00010"; -- 02\r
+ when SENDA => bsm <= b"00011"; -- 03\r
+ when LOADC => bsm <= b"00100"; -- 04\r
+ when SENDC => bsm <= b"00101"; -- 05\r
+ when LOADD => bsm <= b"00110"; -- 06\r
+ when SENDD => bsm <= b"00111"; -- 07\r
+ when GSTOP => bsm <= b"01000"; -- 08\r
+ when INC => bsm <= b"01001"; -- 09\r
+ when FAILED => bsm <= b"01010"; -- 0a\r
+ when DONE => bsm <= b"01011"; -- 0b\r
+ when E_START => bsm <= b"10000"; -- 10\r
+ when E_RSTART => bsm <= b"10001"; -- 11\r
+ when E_ADDR => bsm <= b"10010"; -- 12\r
+ when E_RADDR => bsm <= b"10011"; -- 13\r
+ when E_CMD => bsm <= b"10100"; -- 14\r
+ when E_WD => bsm <= b"10101"; -- 15\r
+ when others => bsm <= b"11111"; -- 1f\r
+ end case;\r
+ end process DECODE;\r
+\r
+-- We need to load different data sets\r
+--LOAD_DATA_PROC: process( clk_in, reset_in, CURRENT_STATE, action_in, phase)\r
+ LOAD_DATA_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ i2c_byte <= (others => '1');\r
+ elsif( (CURRENT_STATE = LOADA) and (phase = '0') ) then\r
+ i2c_byte <= i2c_adr_in(6 downto 0) & '0' & '1'; -- send write address, receive ACK\r
+ elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then\r
+ i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK\r
+ elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then\r
+ i2c_byte <= i2c_cmd_in(7 downto 1) & '0' & '1'; -- send command byte (WRITE), receive ACK\r
+ elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then\r
+ i2c_byte <= i2c_cmd_in(7 downto 1) & '1' & '1'; -- send command byte (READ), receive ACK\r
+ elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then\r
+ i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK\r
+ elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then\r
+ i2c_byte <= x"ff" & '1'; -- send 0xff byte, send NACK\r
+ end if;\r
+ end if;\r
+ end process LOAD_DATA_PROC;\r
+\r
+-- The SendByte module\r
+ THE_I2C_SENDB: I2C_SENDB\r
+ port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ DOBYTE_IN => dobyte,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ I2C_BYTE_IN => i2c_byte,\r
+ I2C_BACK_OUT => i2c_dr,\r
+ SDA_IN => sda_in,\r
+ R_SDA_OUT => r_sda_sb,\r
+ S_SDA_OUT => s_sda_sb,\r
+-- SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_sb,\r
+ S_SCL_OUT => s_scl_sb,\r
+ BDONE_OUT => bdone,\r
+ BOK_OUT => bok,\r
+ BSM_OUT => open\r
+ );\r
+\r
+-- The GenStart module\r
+ THE_I2C_GSTART: I2C_GSTART\r
+ port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => start,\r
+ DOSTART_IN => dostart,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ SDONE_OUT => sdone,\r
+ SOK_OUT => sok,\r
+ SDA_IN => sda_in,\r
+ SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_gs,\r
+ S_SCL_OUT => s_scl_gs,\r
+ R_SDA_OUT => r_sda_gs,\r
+ S_SDA_OUT => s_sda_gs,\r
+ BSM_OUT => gs_debug --open\r
+ );\r
+\r
+ r_scl <= r_scl_gs or r_scl_sb;\r
+ s_scl <= s_scl_gs or s_scl_sb;\r
+ r_sda <= r_sda_gs or r_sda_sb;\r
+ s_sda <= s_sda_gs or s_sda_sb;\r
+\r
+-- Output flipflops for SCL and SDA lines\r
+ THE_SCL_SDA_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ scl_out <= '1';\r
+ sda_out <= '1';\r
+ elsif( (r_scl = '1') and (s_scl = '0') ) then\r
+ scl_out <= '0';\r
+ elsif( (r_scl = '0') and (s_scl = '1') ) then\r
+ scl_out <= '1';\r
+ elsif( (r_sda = '1') and (s_sda = '0') ) then\r
+ sda_out <= '0';\r
+ elsif( (r_sda = '0') and (s_sda = '1') ) then\r
+ sda_out <= '1';\r
+ end if;\r
+ end if;\r
+ end process THE_SCL_SDA_PROC;\r
+\r
+-- Error bits\r
+ THE_ERR_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
+ elsif( CURRENT_STATE = CLRERR ) then\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
+ elsif( CURRENT_STATE = E_START ) then\r
+ e_sf <= '1';\r
+ elsif( CURRENT_STATE = E_RSTART ) then\r
+ e_rsf <= '1';\r
+ elsif( CURRENT_STATE = E_ADDR ) then\r
+ e_anak <= '1';\r
+ elsif( CURRENT_STATE = E_RADDR ) then\r
+ e_ranak <= '1';\r
+ elsif( CURRENT_STATE = E_CMD ) then\r
+ e_cnak <= '1';\r
+ elsif( CURRENT_STATE = E_WD ) then\r
+ e_dnak <= '1';\r
+ end if;\r
+ end if;\r
+ end process THE_ERR_REG_PROC;\r
+\r
+ status_out(7) <= running;\r
+ status_out(6) <= i2c_done;\r
+ status_out(5) <= e_ranak;\r
+ status_out(4) <= e_rsf;\r
+ status_out(3) <= e_dnak;\r
+ status_out(2) <= e_cnak;\r
+ status_out(1) <= e_anak;\r
+ status_out(0) <= e_sf;\r
+\r
+-- Outputs\r
+ i2c_dr_out <= i2c_dr(8 downto 1);\r
+ i2c_busy_out <= running;\r
+\r
+-- Debug stuff\r
+ stat(31 downto 28) <= (others => '0');\r
+ stat(27) <= s_sda;\r
+ stat(26) <= r_sda;\r
+ stat(25) <= s_scl;\r
+ stat(24) <= r_scl;\r
+ stat(23) <= s_sda_sb;\r
+ stat(22) <= r_sda_sb;\r
+ stat(21) <= s_scl_sb;\r
+ stat(20) <= r_scl_sb;\r
+ stat(19) <= s_sda_gs;\r
+ stat(18) <= r_sda_gs;\r
+ stat(17) <= s_scl_gs;\r
+ stat(16) <= r_scl_gs;\r
+ stat(15 downto 12) <= gs_debug;\r
+ stat(11) <= bok;\r
+ stat(10) <= bdone;\r
+ stat(9) <= dobyte;\r
+ stat(8) <= sok;\r
+ stat(7) <= dobyte;\r
+ stat(6) <= s_sda_sb;\r
+ stat(5) <= r_sda_sb;\r
+ stat(4 downto 0) <= bsm;\r
+\r
+\r
+end Behavioral;\r
+++ /dev/null
------------------------------------------------------------------------------
---
---One nXyter FEB
---
------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity nXyter_FEE_BOARD is
-
- port (
- CLK : in std_logic_vector; -- Clock
- RESET : in std_logic_vector; -- RESET
-
- -- ADC
- ADC_FCLK_IN : in std_logic;
- ADC_DCLK_IN : in std_logic;
-
- SC_CLK32_IN : in std_logic;
-
- ADC_A_IN : in std_logic;
- ADC_B_IN : in std_logic;
- ADC_NX_IN : in std_logic;
- ADC_D_IN : in std_logic;
-
- -- ADC SPI
- CBS_OUT : out std_logic;
- SDIO_MUX_OUT : out std_logic;
- SCLK_OUT : out std_logic;
-
- -- nXyter
- NX_CLK128_IN : in std_logic;
- NX_IN : in std_logic_vector (7 downto 0);
- RESET_OUT : out std_logic;
- CLK256A_OUT : out std_logic;
- TESTPULSE_OUT : out std_logic;
-
- -- I2C
- SDA_MUX_OUT : out std_logic;
- SCI_OUT : out std_logic;
- I2C_RESET_OUT : out std_logic
- REG_RESET : out std_logic
-
-end nXyter_FEE_BOARD;
-
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--One nXyter FEB
+--
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.adcmv3_components.all;
+
+entity nXyter_FEE_board is
+
+ port (
+ CLK_IN : in std_logic_vector;
+ RESET_IN : in std_logic_vector;
+
+ -- I2C Ports
+ I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
+ I2C_SCL_OUT : out std_logic; -- nXyter I2C Clock line
+
+ I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C StateMachine
+ I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers to default
+
+ -- ADC SPI
+ SPI_SCLK_OUT : out std_logic;
+ SPI_SDIO_INOUT : in std_logic;
+ SPI_CSB_OUT : out std_logic;
+
+ -- nXyter Timestamp Ports
+ NX_CLK128_IN : in std_logic;
+ NX_IN : in std_logic_vector (7 downto 0);
+ NX_RESET_OUT : out std_logic;
+ NX_CLK256A_OUT : out std_logic;
+ NX_TESTPULSE_OUT : out std_logic;
+
+ -- ADC nXyter Pulse Hight Ports
+ ADC_FCLK_IN : in std_logic;
+ ADC_DCLK_IN : in std_logic;
+ ADC_SC_CLK32_IN : in std_logic;
+ ADC_A_IN : in std_logic;
+ ADC_B_IN : in std_logic;
+ ADC_NX_IN : in std_logic;
+ ADC_D_IN : in std_logic;
+
+ -- TRBNet RegIO Port for the slave bus
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_TIMEOUT_IN : in std_logic;
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic
+ );
+
+end nXyter_FEE_board;
+
+
+architecture Behavioral of nXyter_FEE_board is
+
+-------------------------------------------------------------------------------
+-- Signals
+-------------------------------------------------------------------------------
+
+ -- nXyter related signals
+ signal i2c_sda_o : std_logic; -- I2C SDA
+ signal i2c_sda_i : std_logic;
+ signal i2c_scl_o : std_logic; -- I2C SCL
+ signal i2c_scl_i : std_logic;
+
+ signal spi_sdi : std_logic;
+ signal spi_sdo : std_logic;
+
+
+
+begin
+
+-------------------------------------------------------------------------------
+-- Port Maps
+-------------------------------------------------------------------------------
+
+ -- slave bus signals
+ THE_SLAVE_BUS_1: slave_bus
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ REGIO_ADDR_IN => REGIO_ADDR_IN,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,
+ REGIO_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,
+ REGIO_TIMEOUT_IN => REGIO_TIMEOUT_IN,
+ REGIO_DATAREADY_OUT => REGIO_DATAREADY_OUT,
+ REGIO_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,
+ REGIO_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
+ REGIO_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
+
+ SDA_IN => i2c_sda_i,
+ SDA_OUT => i2c_sda_o,
+ SCL_IN => i2c_scl_i,
+ SCL_OUT => i2c_scl_o,
+
+ SPI_CS_OUT => SPI_CSB_OUT,
+ SPI_SCK_OUT => SPI_SCLK_OUT,
+ SPI_SDI_IN => spi_sdi,
+ SPI_SDO_OUT => spi_sdo
+ );
+
+ -----------------------------------------------------------------------------
+ -- nXyter Signals
+ -----------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- I2C Signals
+ -----------------------------------------------------------------------------
+
+ -- SDA line output
+ I2C_SDA_INOUT <= '0' when (i2c_sda_o = '0') else 'Z';
+
+ -- SDA line input (wired OR negative logic)
+ -- i2c_sda_i <= i2c_sda;
+
+ -- SCL line output
+ I2C_SCL_OUT <= '0' when (i2c_scl_o = '0') else 'Z';
+
+ -- SCL line input (wired OR negative logic)
+ -- i2c_scl_i <= i2c_scl;
+
+-------------------------------------------------------------------------------
+-- END
+-------------------------------------------------------------------------------
+
+end Behavioral;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.ALL;
+
+package nxyter_components is
+
+-------------------------------------------------------------------------------
+-- TRBNet interfaces
+-------------------------------------------------------------------------------
+
+component nXyter_FEE_board
+ port (
+ CLK_IN : in std_logic_vector;
+ RESET_IN : in std_logic_vector;
+ I2C_SDA_INOUT : inout std_logic;
+ I2C_SCL_OUT : out std_logic;
+ I2C_SM_RESET_OUT : out std_logic;
+ I2C_REG_RESET_OUT : out std_logic;
+ SPI_SCLK_OUT : out std_logic;
+ SPI_SDIO_INOUT : in std_logic;
+ SPI_CSB_OUT : out std_logic;
+ NX_CLK128_IN : in std_logic;
+ NX_IN : in std_logic_vector (7 downto 0);
+ NX_RESET_OUT : out std_logic;
+ NX_CLK256A_OUT : out std_logic;
+ NX_TESTPULSE_OUT : out std_logic;
+ ADC_FCLK_IN : in std_logic;
+ ADC_DCLK_IN : in std_logic;
+ ADC_SC_CLK32_IN : in std_logic;
+ ADC_A_IN : in std_logic;
+ ADC_B_IN : in std_logic;
+ ADC_NX_IN : in std_logic;
+ ADC_D_IN : in std_logic;
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_TIMEOUT_IN : in std_logic;
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic);
+end component;
+
+
+
+
+
+component Gray_Decoder
+ generic (
+ WIDTH : integer);
+ port (
+ GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0);
+ BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0));
+end component;
+
+end package;
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slave_bus is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ \r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slave_bus is\r
+\r
+-- Signals\r
+ signal slv_read : std_logic_vector(18-1 downto 0);\r
+ signal slv_write : std_logic_vector(18-1 downto 0);\r
+ signal slv_busy : std_logic_vector(18-1 downto 0);\r
+ signal slv_ack : std_logic_vector(18-1 downto 0);\r
+ signal slv_addr : std_logic_vector(18*16-1 downto 0);\r
+ signal slv_data_rd : std_logic_vector(18*32-1 downto 0);\r
+ signal slv_data_wr : std_logic_vector(18*32-1 downto 0);\r
+\r
+-- SPI controller BRAM lines\r
+ signal spi_bram_addr : std_logic_vector(7 downto 0);\r
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_we : std_logic;\r
+\r
+ signal spi_cs : std_logic;\r
+ signal spi_sck : std_logic;\r
+ signal spi_sdi : std_logic;\r
+ signal spi_sdo : std_logic;\r
+ signal spi_debug : std_logic_vector(31 downto 0);\r
+\r
+ signal ctrl_lvl : std_logic_vector(31 downto 0);\r
+ signal ctrl_trg : std_logic_vector(31 downto 0);\r
+ signal ctrl_pll : std_logic_vector(15 downto 0);\r
+\r
+ signal debug : std_logic_vector(63 downto 0);\r
+ signal onewire_debug : std_logic_vector(63 downto 0);\r
+ \r
+ -- do not know at the moment, have no backplanes, needed by Slave-Bus\r
+ signal bp_module_qq : std_logic_vector(3 downto 0);\r
+\r
+ -- Pedestal and threshold stuff\r
+ type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+\r
+ signal buf_addr : std_logic_vector(6 downto 0);\r
+ signal thr_addr : std_logic_vector(6 downto 0);\r
+ signal thr_data : reg_18bit_t;\r
+ signal ped_data : reg_18bit_t;\r
+\r
+begin\r
+\r
+-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
+ THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
+ generic map(\r
+ PORT_NUMBER => 3,\r
+ PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
+ 1 => x"a800", -- threshold memories\r
+ 2 => x"8040", -- I2C master\r
+ -- 3 => x"c000", -- 1Wire master + memory\r
+ -- 4 => x"d000", -- SPI master\r
+ -- 5 => x"d100", -- SPI data memory\r
+ -- 6 => x"d010", -- ADC0 SPI\r
+ -- 7 => x"d020", -- ADC1 SPI\r
+ -- 8 => x"b000", -- APV control / status\r
+ -- 9 => x"b010", -- ADC level settings\r
+ -- 10 => x"b020", -- trigger settings\r
+ -- 11 => x"b030", -- PLL settings\r
+ -- 12 => x"f000", -- ADC 0 snooper\r
+ -- 13 => x"f800", -- ADC 1 snooper\r
+ -- 14 => x"8000", -- test register (busy)\r
+ -- 15 => x"7100", -- data buffer status registers\r
+ -- 16 => x"7200", -- LVL1 release status register\r
+ -- 17 => x"7202", -- IPU handler status register\r
+ others => x"0000"),\r
+ PORT_ADDR_MASK => ( 0 => 16, -- pedestal memories\r
+ 1 => 16, -- threshold memories\r
+ 2 => 0, -- I2C master\r
+ -- 3 => 6, -- 1Wire master + memory\r
+ -- 4 => 1, -- SPI master\r
+ -- 5 => 6, -- SPI data memory\r
+ -- 6 => 0, -- ADC0 SPI\r
+ -- 7 => 0, -- ADC1 SPI\r
+ -- 8 => 4, -- APV control / status\r
+ -- 9 => 0, -- ADC level settings\r
+ -- 10 => 0, -- trigger settings\r
+ -- 11 => 0, -- PLL settings\r
+ -- 12 => 10, -- ADC 0 snooper\r
+ -- 13 => 10, -- ADC 1 snooper\r
+ -- 14 => 0, -- test register (normal)\r
+ -- 15 => 4, -- FIFO status registers\r
+ -- 16 => 0, -- LVL1 release status register\r
+ -- 17 => 0, -- IPU handler status register\r
+ others => 0)\r
+ )\r
+ port map(\r
+ CLK => CLK_IN,\r
+ RESET => RESET_IN,\r
+ DAT_ADDR_IN => REGIO_ADDR_IN,\r
+ DAT_DATA_IN => REGIO_DATA_IN,\r
+ DAT_DATA_OUT => REGIO_DATA_OUT,\r
+ DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,\r
+ DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,\r
+ DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,\r
+ DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,\r
+ DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,\r
+ DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,\r
+ DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,\r
+ -- pedestal memories\r
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),\r
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_DATAREADY_IN(0) => slv_ack(0),\r
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
+ BUS_UNKNOWN_ADDR_IN(0) => '0',\r
+ -- threshold memories\r
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),\r
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_DATAREADY_IN(1) => slv_ack(1),\r
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ -- I2C master\r
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),\r
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_DATAREADY_IN(2) => slv_ack(2),\r
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
+ BUS_UNKNOWN_ADDR_IN(2) => '0',\r
+\r
+ -- OneWire master\r
+ --BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
+ --BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
+ --BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
+ --BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),\r
+ --BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
+ --BUS_TIMEOUT_OUT(3) => open,\r
+ --BUS_DATAREADY_IN(3) => slv_ack(3),\r
+ --BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
+ --BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
+ --BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+ ---- SPI control registers\r
+ --BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
+ --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
+ --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
+ --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),\r
+ --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
+ --BUS_TIMEOUT_OUT(4) => open,\r
+ --BUS_DATAREADY_IN(4) => slv_ack(4),\r
+ --BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
+ --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
+ --BUS_UNKNOWN_ADDR_IN(4) => '0',\r
+ ---- SPI data memory\r
+ --BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
+ --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
+ --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
+ --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),\r
+ --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
+ --BUS_TIMEOUT_OUT(5) => open,\r
+ --BUS_DATAREADY_IN(5) => slv_ack(5),\r
+ --BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
+ --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
+ --BUS_UNKNOWN_ADDR_IN(5) => '0',\r
+ ---- ADC 0 SPI control registers\r
+ --BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
+ --BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
+ --BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
+ --BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),\r
+ --BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
+ --BUS_TIMEOUT_OUT(6) => open,\r
+ --BUS_DATAREADY_IN(6) => slv_ack(6),\r
+ --BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
+ --BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
+ --BUS_UNKNOWN_ADDR_IN(6) => '0',\r
+ ---- ADC 1 SPI control registers\r
+ --BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
+ --BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
+ --BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
+ --BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),\r
+ --BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
+ --BUS_TIMEOUT_OUT(7) => open,\r
+ --BUS_DATAREADY_IN(7) => slv_ack(7),\r
+ --BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
+ --BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
+ --BUS_UNKNOWN_ADDR_IN(7) => '0',\r
+ ---- APV control / status registers\r
+ --BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
+ --BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
+ --BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
+ --BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32),\r
+ --BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
+ --BUS_TIMEOUT_OUT(8) => open,\r
+ --BUS_DATAREADY_IN(8) => slv_ack(8),\r
+ --BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
+ --BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
+ --BUS_UNKNOWN_ADDR_IN(8) => '0',\r
+ ---- ADC / PLL / trigger ctrl register\r
+ --BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
+ --BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
+ --BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
+ --BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32),\r
+ --BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
+ --BUS_TIMEOUT_OUT(11 downto 9) => open,\r
+ --BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ --BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ --BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
+ --BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
+ ---- ADC0 snooper\r
+ --BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
+ --BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
+ --BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
+ --BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32),\r
+ --BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
+ --BUS_TIMEOUT_OUT(12) => open,\r
+ --BUS_DATAREADY_IN(12) => slv_ack(12),\r
+ --BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
+ --BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
+ --BUS_UNKNOWN_ADDR_IN(12) => '0',\r
+ ---- ADC1 snooper\r
+ --BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
+ --BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
+ --BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
+ --BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32),\r
+ --BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
+ --BUS_TIMEOUT_OUT(13) => open,\r
+ --BUS_DATAREADY_IN(13) => slv_ack(13),\r
+ --BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
+ --BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
+ --BUS_UNKNOWN_ADDR_IN(13) => '0',\r
+ ---- Test register\r
+ --BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
+ --BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
+ --BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
+ --BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32),\r
+ --BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
+ --BUS_TIMEOUT_OUT(14) => open,\r
+ --BUS_DATAREADY_IN(14) => slv_ack(14),\r
+ --BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
+ --BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
+ --BUS_UNKNOWN_ADDR_IN(14) => '0',\r
+ ---- data buffer status registers\r
+ --BUS_READ_ENABLE_OUT(15) => slv_read(15),\r
+ --BUS_WRITE_ENABLE_OUT(15) => slv_write(15),\r
+ --BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32),\r
+ --BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32),\r
+ --BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16),\r
+ --BUS_TIMEOUT_OUT(15) => open,\r
+ --BUS_DATAREADY_IN(15) => slv_ack(15),\r
+ --BUS_WRITE_ACK_IN(15) => slv_ack(15),\r
+ --BUS_NO_MORE_DATA_IN(15) => slv_busy(15),\r
+ --BUS_UNKNOWN_ADDR_IN(15) => '0',\r
+ ---- LVL1 release status register\r
+ --BUS_READ_ENABLE_OUT(16) => slv_read(16),\r
+ --BUS_WRITE_ENABLE_OUT(16) => slv_write(16),\r
+ --BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32),\r
+ --BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32),\r
+ --BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16),\r
+ --BUS_TIMEOUT_OUT(16) => open,\r
+ --BUS_DATAREADY_IN(16) => slv_ack(16),\r
+ --BUS_WRITE_ACK_IN(16) => slv_ack(16),\r
+ --BUS_NO_MORE_DATA_IN(16) => slv_busy(16),\r
+ --BUS_UNKNOWN_ADDR_IN(16) => '0',\r
+ ---- IPU handler status register\r
+ --BUS_READ_ENABLE_OUT(17) => slv_read(17),\r
+ --BUS_WRITE_ENABLE_OUT(17) => slv_write(17),\r
+ --BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32),\r
+ --BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32),\r
+ --BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16),\r
+ --BUS_TIMEOUT_OUT(17) => open,\r
+ --BUS_DATAREADY_IN(17) => slv_ack(17),\r
+ --BUS_WRITE_ACK_IN(17) => slv_ack(17),\r
+ --BUS_NO_MORE_DATA_IN(17) => slv_busy(17),\r
+ --BUS_UNKNOWN_ADDR_IN(17) => '0',\r
+ ---- debug\r
+ --STAT_DEBUG => stat\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+\r
+------------------------------------------------------------------------------------\r
+-- pedestal memories (16x128 = 2048, 18bit)\r
+------------------------------------------------------------------------------------\r
+ THE_PED_MEM: slv_ped_thr_mem\r
+ port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
+ SLV_READ_IN => slv_read(0),\r
+ SLV_WRITE_IN => slv_write(0),\r
+ SLV_ACK_OUT => slv_ack(0),\r
+ SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
+ SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => CLK_IN,\r
+ MEM_ADDR_IN => buf_addr,\r
+ MEM_0_D_OUT => ped_data(0),\r
+ MEM_1_D_OUT => ped_data(1),\r
+ MEM_2_D_OUT => ped_data(2),\r
+ MEM_3_D_OUT => ped_data(3),\r
+ MEM_4_D_OUT => ped_data(4),\r
+ MEM_5_D_OUT => ped_data(5),\r
+ MEM_6_D_OUT => ped_data(6),\r
+ MEM_7_D_OUT => ped_data(7),\r
+ MEM_8_D_OUT => ped_data(8),\r
+ MEM_9_D_OUT => ped_data(9),\r
+ MEM_10_D_OUT => ped_data(10),\r
+ MEM_11_D_OUT => ped_data(11),\r
+ MEM_12_D_OUT => ped_data(12),\r
+ MEM_13_D_OUT => ped_data(13),\r
+ MEM_14_D_OUT => ped_data(14),\r
+ MEM_15_D_OUT => ped_data(15),\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+ slv_busy(0) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- threshold memories (16x128 = 2048, 18bit)\r
+------------------------------------------------------------------------------------\r
+ THE_THR_MEM: slv_ped_thr_mem\r
+ port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
+ SLV_READ_IN => slv_read(1),\r
+ SLV_WRITE_IN => slv_write(1),\r
+ SLV_ACK_OUT => slv_ack(1),\r
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => CLK_IN,\r
+ MEM_ADDR_IN => thr_addr,\r
+ MEM_0_D_OUT => thr_data(0),\r
+ MEM_1_D_OUT => thr_data(1),\r
+ MEM_2_D_OUT => thr_data(2),\r
+ MEM_3_D_OUT => thr_data(3),\r
+ MEM_4_D_OUT => thr_data(4),\r
+ MEM_5_D_OUT => thr_data(5),\r
+ MEM_6_D_OUT => thr_data(6),\r
+ MEM_7_D_OUT => thr_data(7),\r
+ MEM_8_D_OUT => thr_data(8),\r
+ MEM_9_D_OUT => thr_data(9),\r
+ MEM_10_D_OUT => thr_data(10),\r
+ MEM_11_D_OUT => thr_data(11),\r
+ MEM_12_D_OUT => thr_data(12),\r
+ MEM_13_D_OUT => thr_data(13),\r
+ MEM_14_D_OUT => thr_data(14),\r
+ MEM_15_D_OUT => thr_data(15),\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+ slv_busy(1) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- I2C master block for accessing APVs\r
+------------------------------------------------------------------------------------\r
+ THE_I2C_MASTER: i2c_master\r
+ port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(2),\r
+ SLV_WRITE_IN => slv_write(2),\r
+ SLV_BUSY_OUT => slv_busy(2),\r
+ SLV_ACK_OUT => slv_ack(2),\r
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
+ -- I2C connections\r
+ SDA_IN => SDA_IN,\r
+ SDA_OUT => SDA_OUT,\r
+ SCL_IN => SCL_IN,\r
+ SCL_OUT => SCL_OUT,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+-- ------------------------------------------------------------------------------------\r
+-- -- SPI master\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_SPI_MASTER: spi_master\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- BUS_READ_IN => slv_read(4),\r
+-- BUS_WRITE_IN => slv_write(4),\r
+-- BUS_BUSY_OUT => slv_busy(4),\r
+-- BUS_ACK_OUT => slv_ack(4),\r
+-- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),\r
+-- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),\r
+-- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),\r
+-- -- SPI connections\r
+-- SPI_CS_OUT => spi_cs,\r
+-- SPI_SDI_IN => spi_sdi,\r
+-- SPI_SDO_OUT => spi_sdo,\r
+-- SPI_SCK_OUT => spi_sck,\r
+-- -- BRAM for read/write data\r
+-- BRAM_A_OUT => spi_bram_addr,\r
+-- BRAM_WR_D_IN => spi_bram_wr_d,\r
+-- BRAM_RD_D_OUT => spi_bram_rd_d,\r
+-- BRAM_WE_OUT => spi_bram_we,\r
+-- -- Status lines\r
+-- STAT => spi_debug --open\r
+-- );\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- data memory for SPI accesses\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_SPI_MEMORY: spi_databus_memory\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
+-- BUS_READ_IN => slv_read(5),\r
+-- BUS_WRITE_IN => slv_write(5),\r
+-- BUS_ACK_OUT => slv_ack(5),\r
+-- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),\r
+-- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),\r
+-- -- state machine connections\r
+-- BRAM_ADDR_IN => spi_bram_addr,\r
+-- BRAM_WR_D_OUT => spi_bram_wr_d,\r
+-- BRAM_RD_D_IN => spi_bram_rd_d,\r
+-- BRAM_WE_IN => spi_bram_we,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- slv_busy(5) <= '0';\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- ADC0 SPI master\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_SPI_ADC0_MASTER: spi_adc_master\r
+-- generic map(\r
+-- RESET_VALUE_CTRL => x"60"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(6),\r
+-- SLV_WRITE_IN => slv_write(6),\r
+-- SLV_BUSY_OUT => slv_busy(6),\r
+-- SLV_ACK_OUT => slv_ack(6),\r
+-- SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
+-- SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
+-- -- SPI connections\r
+-- SPI_CS_OUT => SPI_ADC0_CS_OUT,\r
+-- SPI_SDO_OUT => SPI_ADC0_SDO_OUT,\r
+-- SPI_SCK_OUT => SPI_ADC0_SCK_OUT,\r
+-- -- ADC connections\r
+-- ADC_LOCKED_IN => ADC0_PLL_LOCKED_IN,\r
+-- ADC_PD_OUT => ADC0_PD_OUT,\r
+-- ADC_RST_OUT => ADC0_RST_OUT,\r
+-- ADC_DEL_OUT => ADC0_DEL_OUT,\r
+-- -- APV connections\r
+-- APV_RST_OUT => APV0_RST_OUT,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- ADC1 SPI master\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_SPI_ADC1_MASTER: spi_adc_master\r
+-- generic map(\r
+-- RESET_VALUE_CTRL => x"60"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(7),\r
+-- SLV_WRITE_IN => slv_write(7),\r
+-- SLV_BUSY_OUT => slv_busy(7),\r
+-- SLV_ACK_OUT => slv_ack(7),\r
+-- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
+-- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
+-- -- SPI connections\r
+-- SPI_CS_OUT => SPI_ADC1_CS_OUT,\r
+-- SPI_SDO_OUT => SPI_ADC1_SDO_OUT,\r
+-- SPI_SCK_OUT => SPI_ADC1_SCK_OUT,\r
+-- -- ADC connections\r
+-- ADC_LOCKED_IN => ADC1_PLL_LOCKED_IN,\r
+-- ADC_PD_OUT => ADC1_PD_OUT,\r
+-- ADC_RST_OUT => ADC1_RST_OUT,\r
+-- ADC_DEL_OUT => ADC1_DEL_OUT,\r
+-- -- APV connections\r
+-- APV_RST_OUT => APV1_RST_OUT,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- APV control / status registers\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_SLV_REGISTER_BANK: slv_register_bank\r
+-- generic map(\r
+-- RESET_VALUE => x"0001"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
+-- SLV_READ_IN => slv_read(8),\r
+-- SLV_WRITE_IN => slv_write(8),\r
+-- SLV_ACK_OUT => slv_ack(8),\r
+-- SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
+-- SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
+-- -- I/O to the backend\r
+-- BACKPLANE_IN => BACKPLANE_IN,\r
+-- CTRL_0_OUT => CTRL_0_OUT,\r
+-- CTRL_1_OUT => CTRL_1_OUT,\r
+-- CTRL_2_OUT => CTRL_2_OUT,\r
+-- CTRL_3_OUT => CTRL_3_OUT,\r
+-- CTRL_4_OUT => CTRL_4_OUT,\r
+-- CTRL_5_OUT => CTRL_5_OUT,\r
+-- CTRL_6_OUT => CTRL_6_OUT,\r
+-- CTRL_7_OUT => CTRL_7_OUT,\r
+-- CTRL_8_OUT => CTRL_8_OUT,\r
+-- CTRL_9_OUT => CTRL_9_OUT,\r
+-- CTRL_10_OUT => CTRL_10_OUT,\r
+-- CTRL_11_OUT => CTRL_11_OUT,\r
+-- CTRL_12_OUT => CTRL_12_OUT,\r
+-- CTRL_13_OUT => CTRL_13_OUT,\r
+-- CTRL_14_OUT => CTRL_14_OUT,\r
+-- CTRL_15_OUT => CTRL_15_OUT,\r
+-- STAT_0_IN => STAT_0_IN,\r
+-- STAT_1_IN => STAT_1_IN,\r
+-- STAT_2_IN => STAT_2_IN,\r
+-- STAT_3_IN => STAT_3_IN,\r
+-- STAT_4_IN => STAT_4_IN,\r
+-- STAT_5_IN => STAT_5_IN,\r
+-- STAT_6_IN => STAT_6_IN,\r
+-- STAT_7_IN => STAT_7_IN,\r
+-- STAT_8_IN => STAT_8_IN,\r
+-- STAT_9_IN => STAT_9_IN,\r
+-- STAT_10_IN => STAT_10_IN,\r
+-- STAT_11_IN => STAT_11_IN,\r
+-- STAT_12_IN => STAT_12_IN,\r
+-- STAT_13_IN => STAT_13_IN,\r
+-- STAT_14_IN => STAT_14_IN,\r
+-- STAT_15_IN => STAT_15_IN,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- slv_busy(8) <= '0';\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- Data buffer status registers\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_FIFO_STATUS_BANK: slv_status_bank\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_ADDR_IN => slv_addr(15*16+3 downto 15*16),\r
+-- SLV_READ_IN => slv_read(15),\r
+-- SLV_WRITE_IN => slv_write(15),\r
+-- SLV_ACK_OUT => slv_ack(15),\r
+-- SLV_DATA_OUT => slv_data_rd(15*32+31 downto 15*32),\r
+-- -- I/O to the backend\r
+-- STAT_0_IN => FIFO_STATUS_0_IN,\r
+-- STAT_1_IN => FIFO_STATUS_1_IN,\r
+-- STAT_2_IN => FIFO_STATUS_2_IN,\r
+-- STAT_3_IN => FIFO_STATUS_3_IN,\r
+-- STAT_4_IN => FIFO_STATUS_4_IN,\r
+-- STAT_5_IN => FIFO_STATUS_5_IN,\r
+-- STAT_6_IN => FIFO_STATUS_6_IN,\r
+-- STAT_7_IN => FIFO_STATUS_7_IN,\r
+-- STAT_8_IN => FIFO_STATUS_8_IN,\r
+-- STAT_9_IN => FIFO_STATUS_9_IN,\r
+-- STAT_10_IN => FIFO_STATUS_10_IN,\r
+-- STAT_11_IN => FIFO_STATUS_11_IN,\r
+-- STAT_12_IN => FIFO_STATUS_12_IN,\r
+-- STAT_13_IN => FIFO_STATUS_13_IN,\r
+-- STAT_14_IN => FIFO_STATUS_14_IN,\r
+-- STAT_15_IN => FIFO_STATUS_15_IN\r
+-- );\r
+-- slv_busy(15) <= '0';\r
+-- \r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- LVL1 release status\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_LVL1_RELEASE_STATUS: slv_status\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(16),\r
+-- SLV_WRITE_IN => slv_write(16),\r
+-- SLV_ACK_OUT => slv_ack(16),\r
+-- SLV_DATA_OUT => slv_data_rd(16*32+31 downto 16*32),\r
+-- -- I/O to the backend\r
+-- STATUS_IN => RELEASE_STATUS_IN\r
+-- );\r
+-- slv_busy(16) <= '0';\r
+-- \r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- IPU handler status\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_IPU_HANDLER_STATUS: slv_status\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(17),\r
+-- SLV_WRITE_IN => slv_write(17),\r
+-- SLV_ACK_OUT => slv_ack(17),\r
+-- SLV_DATA_OUT => slv_data_rd(17*32+31 downto 17*32),\r
+-- -- I/O to the backend\r
+-- STATUS_IN => IPU_STATUS_IN\r
+-- );\r
+-- slv_busy(17) <= '0';\r
+-- \r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- ADC level register\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_ADC_LVL_REG: slv_register\r
+-- generic map(\r
+-- RESET_VALUE => x"d0_20_88_78"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN, -- general reset\r
+-- BUSY_IN => '0',\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(9),\r
+-- SLV_WRITE_IN => slv_write(9),\r
+-- SLV_BUSY_OUT => slv_busy(9),\r
+-- SLV_ACK_OUT => slv_ack(9),\r
+-- SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),\r
+-- SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN => ctrl_lvl,\r
+-- REG_DATA_OUT => ctrl_lvl,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- trigger control register\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_TRG_CTRL_REG: slv_register\r
+-- generic map(\r
+-- RESET_VALUE => x"10_10_10_10"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN, -- general reset\r
+-- BUSY_IN => '0',\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(10),\r
+-- SLV_WRITE_IN => slv_write(10),\r
+-- SLV_BUSY_OUT => slv_busy(10),\r
+-- SLV_ACK_OUT => slv_ack(10),\r
+-- SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32),\r
+-- SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN => ctrl_trg,\r
+-- REG_DATA_OUT => ctrl_trg,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- PLL control register\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_PLL_CTRL_REG: slv_half_register\r
+-- generic map(\r
+-- RESET_VALUE => x"00_02"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN, -- general reset\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(11),\r
+-- SLV_WRITE_IN => slv_write(11),\r
+-- SLV_ACK_OUT => slv_ack(11),\r
+-- SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
+-- SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
+-- -- I/O to the backend\r
+-- STATUS_REG_IN => STATUS_PLL_IN,\r
+-- CTRL_REG_OUT => ctrl_pll,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- slv_busy(11) <= '0';\r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- ADC0 snooper\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_ADC0_SNOOPER: slv_adc_snoop\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
+-- SLV_READ_IN => slv_read(12),\r
+-- SLV_WRITE_IN => slv_write(12),\r
+-- SLV_ACK_OUT => slv_ack(12),\r
+-- SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
+-- SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
+-- -- I/O to the backend\r
+-- ADC_SEL_OUT => ADC0_SEL_OUT,\r
+-- ADC_CLK_IN => ADC0_CLK_IN,\r
+-- ADC_DATA_IN => ADC0_DATA_IN,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- slv_busy(12) <= '0';\r
+-- \r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- ADC1 snooper\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_ADC1_SNOOPER: slv_adc_snoop\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- -- Slave bus\r
+-- SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
+-- SLV_READ_IN => slv_read(13),\r
+-- SLV_WRITE_IN => slv_write(13),\r
+-- SLV_ACK_OUT => slv_ack(13),\r
+-- SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
+-- SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
+-- -- I/O to the backend\r
+-- ADC_SEL_OUT => ADC1_SEL_OUT,\r
+-- ADC_CLK_IN => ADC1_CLK_IN,\r
+-- ADC_DATA_IN => ADC1_DATA_IN,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- slv_busy(13) <= '0';\r
+-- \r
+-- \r
+-- ------------------------------------------------------------------------------------\r
+-- -- test register (normal)\r
+-- ------------------------------------------------------------------------------------\r
+-- THE_GOOD_TEST_REG: slv_register\r
+-- generic map(\r
+-- RESET_VALUE => x"dead_beef"\r
+-- )\r
+-- port map(\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN, -- general reset\r
+-- BUSY_IN => '0',\r
+-- -- Slave bus\r
+-- SLV_READ_IN => slv_read(14),\r
+-- SLV_WRITE_IN => slv_write(14),\r
+-- SLV_BUSY_OUT => slv_busy(14),\r
+-- SLV_ACK_OUT => slv_ack(14),\r
+-- SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
+-- SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN => TEST_REG_IN, --x"5a3c_87e1",\r
+-- REG_DATA_OUT => TEST_REG_OUT,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+-- \r
+-- \r
+\r
+\r
+-- unusable pins\r
+ debug(63 downto 43) <= (others => '0');\r
+-- connected pins\r
+ debug(42 downto 0) <= (others => '0');\r
+\r
+-- input signals\r
+ spi_sdi <= SPI_SDI_IN;\r
+\r
+-- Output signals\r
+ SPI_CS_OUT <= spi_cs;\r
+ SPI_SCK_OUT <= spi_sck;\r
+ SPI_SDO_OUT <= spi_sdo;\r
+\r
+ -- CTRL_LVL_OUT <= ctrl_lvl;\r
+ -- CTRL_TRG_OUT <= ctrl_trg;\r
+ -- CTRL_PLL_OUT <= ctrl_pll;\r
+\r
+ -- DEBUG_OUT <= debug;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_ped_thr_mem is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_ped_thr_mem is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ RD_RDY,\r
+ RD_DEL0,\r
+ RD_DEL1,\r
+ WR_DEL0,\r
+ WR_DEL1,\r
+ WR_RDY,\r
+ RD_ACK,\r
+ WR_ACK,\r
+ DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- statemachine signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal block_addr : std_logic_vector(3 downto 0);\r
+\r
+ type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal ped_data : ped_data_t;\r
+ signal mem_data : ped_data_t;\r
+\r
+ signal mem_wr_x : std_logic_vector(15 downto 0);\r
+ signal mem_wr : std_logic_vector(15 downto 0);\r
+ signal mem_sel : std_logic_vector(15 downto 0);\r
+\r
+ signal rdback_data : std_logic_vector(17 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- Mapping of backplanes --\r
+---------------------------------------------------------\r
+ THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
+ port map (\r
+ ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
+ Q => block_addr\r
+ );\r
+\r
+ THE_MEM_SEL_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ case block_addr is\r
+ when x"0" => mem_sel <= b"0000_0000_0000_0001";\r
+ rdback_data <= mem_data(0);\r
+ when x"1" => mem_sel <= b"0000_0000_0000_0010";\r
+ rdback_data <= mem_data(1);\r
+ when x"2" => mem_sel <= b"0000_0000_0000_0100";\r
+ rdback_data <= mem_data(2);\r
+ when x"3" => mem_sel <= b"0000_0000_0000_1000";\r
+ rdback_data <= mem_data(3);\r
+ when x"4" => mem_sel <= b"0000_0000_0001_0000";\r
+ rdback_data <= mem_data(4);\r
+ when x"5" => mem_sel <= b"0000_0000_0010_0000";\r
+ rdback_data <= mem_data(5);\r
+ when x"6" => mem_sel <= b"0000_0000_0100_0000";\r
+ rdback_data <= mem_data(6);\r
+ when x"7" => mem_sel <= b"0000_0000_1000_0000";\r
+ rdback_data <= mem_data(7);\r
+ when x"8" => mem_sel <= b"0000_0001_0000_0000";\r
+ rdback_data <= mem_data(8);\r
+ when x"9" => mem_sel <= b"0000_0010_0000_0000";\r
+ rdback_data <= mem_data(9);\r
+ when x"a" => mem_sel <= b"0000_0100_0000_0000";\r
+ rdback_data <= mem_data(10);\r
+ when x"b" => mem_sel <= b"0000_1000_0000_0000";\r
+ rdback_data <= mem_data(11);\r
+ when x"c" => mem_sel <= b"0001_0000_0000_0000";\r
+ rdback_data <= mem_data(12);\r
+ when x"d" => mem_sel <= b"0010_0000_0000_0000";\r
+ rdback_data <= mem_data(13);\r
+ when x"e" => mem_sel <= b"0100_0000_0000_0000";\r
+ rdback_data <= mem_data(14);\r
+ when x"f" => mem_sel <= b"1000_0000_0000_0000";\r
+ rdback_data <= mem_data(15);\r
+ when others => mem_sel <= b"0000_0000_0000_0000"; -- never used\r
+ rdback_data <= (others => '0');\r
+ end case;\r
+ end if;\r
+ end process THE_MEM_SEL_PROC;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- block memories --\r
+---------------------------------------------------------\r
+ GEN_PED_MEM: for i in 0 to 15 generate\r
+ -- Port A: SLV_BUS\r
+ -- Port B: state machine\r
+ THE_PED_MEM: ped_thr_true\r
+ port map(\r
+ DATAINA => slv_data_in(17 downto 0),\r
+ DATAINB => b"00_0000_0000_0000_0000",\r
+ ADDRESSA => slv_addr_in(6 downto 0),\r
+ ADDRESSB => mem_addr_in,\r
+ CLOCKA => clk_in,\r
+ CLOCKB => mem_clk_in,\r
+ CLOCKENA => '1',\r
+ CLOCKENB => '1',\r
+ WRA => mem_wr(i), -- BUGBUGBUG\r
+ WRB => '0', -- state machine never writes!\r
+ RESETA => reset_in,\r
+ RESETB => reset_in,\r
+ QA => mem_data(i),\r
+ QB => ped_data(i)\r
+ );\r
+ -- Write signals\r
+ mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0';\r
+ end generate GEN_PED_MEM;\r
+\r
+-- Synchronize\r
+ THE_SYNC_PROC: process(clk_in)\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ mem_wr <= mem_wr_x;\r
+ end if;\r
+ end process THE_SYNC_PROC;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+ slv_ack_out <= slv_ack;\r
+ slv_data_out <= b"0000_0000_0000_00" & rdback_data;\r
+\r
+ mem_0_d_out <= ped_data(0);\r
+ mem_1_d_out <= ped_data(1);\r
+ mem_2_d_out <= ped_data(2);\r
+ mem_3_d_out <= ped_data(3);\r
+ mem_4_d_out <= ped_data(4);\r
+ mem_5_d_out <= ped_data(5);\r
+ mem_6_d_out <= ped_data(6);\r
+ mem_7_d_out <= ped_data(7);\r
+ mem_8_d_out <= ped_data(8);\r
+ mem_9_d_out <= ped_data(9);\r
+ mem_10_d_out <= ped_data(10);\r
+ mem_11_d_out <= ped_data(11);\r
+ mem_12_d_out <= ped_data(12);\r
+ mem_13_d_out <= ped_data(13);\r
+ mem_14_d_out <= ped_data(14);\r
+ mem_15_d_out <= ped_data(15);\r
+\r
+ stat(31 downto 20) <= (others => '0');\r
+ stat(19 downto 16) <= block_addr;\r
+ stat(15 downto 0) <= mem_sel;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_register is\r
+ generic(\r
+ RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_register is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,\r
+ RD_BSY,\r
+ WR_BSY,\r
+ RD_RDY,\r
+ WR_RDY,\r
+ RD_ACK,\r
+ WR_ACK,\r
+ DONE\r
+ );\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+ signal reg_busy : std_logic;\r
+\r
+begin\r
+\r
+-- Fake\r
+ reg_busy <= busy_in;\r
+ stat <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+ PROC_STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_STATE_MEM;\r
+\r
+-- Transition matrix\r
+ PROC_TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy)\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+\r
+ case CURRENT_STATE is\r
+\r
+ when SLEEP =>\r
+ if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1'; \r
+ elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1'; \r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+\r
+ when RD_RDY =>\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+\r
+ when WR_RDY =>\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+\r
+ when RD_ACK =>\r
+ if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+\r
+ when WR_ACK =>\r
+ if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+\r
+ when RD_BSY =>\r
+ if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+\r
+ when WR_BSY =>\r
+ if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+\r
+ when DONE =>\r
+ NEXT_STATE <= SLEEP;\r
+\r
+ when others =>\r
+ NEXT_STATE <= SLEEP;\r
+\r
+ end case;\r
+ end process PROC_TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+ PROC_WRITE_REG: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_in <= RESET_VALUE;\r
+ elsif( store_wr = '1' ) then\r
+ reg_slv_data_in <= slv_data_in;\r
+ end if;\r
+ end if;\r
+ end process PROC_WRITE_REG;\r
+\r
+-- register read\r
+ PROC_READ_REG: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= reg_data_in;\r
+ end if;\r
+ end if;\r
+ end process PROC_READ_REG;\r
+\r
+-- output signals\r
+ slv_ack_out <= slv_ack;\r
+ slv_busy_out <= slv_busy;\r
+ slv_data_out <= reg_slv_data_out;\r
+\r
+---------------------------------------------------------\r
+-- signals to backend --\r
+---------------------------------------------------------\r
+\r
+ reg_data_out <= reg_slv_data_in;\r
+\r
+end Behavioral;\r
jspc29 / trb3.git / commitdiff