really has a fixed latency.
signal rx_rm_rst_n, tx_rm_rst_n :std_logic;
- signal dummy_output_i : std_logic_vector(8 downto 0);
-
signal gear_to_rm_rst_i : std_logic;
signal gear_to_rm_n_rst_i : std_logic;
end process;
-- STAT_OP REGISTER
-STAT_OP(8 downto 0) <= rx_data_i when CTRL_OP(8) = '0' else dummy_output_i;
+STAT_OP(8 downto 0) <= rx_data_i;
STAT_OP(9) <= clk_rx_full;
STAT_OP(10) <= clk_125_i;
STAT_OP(14) <= rx_serdes_rst;
STAT_OP(15) <= rx_pcs_rst;
-dummy_output_i(3 downto 0) <= wa_position(3 downto 0);
-
-dummy_output_i(4) <= rx_rst_fsm_ready_i;
-dummy_output_i(5) <= tx_pll_lol;
-dummy_output_i(6) <= tx_pcs_rst;
-dummy_output_i(7) <= rx_serdes_ready_for_gear_i;
-dummy_output_i(8) <= serdes_rx_ready_i;
-
-
--- STAT_OP(0) <= clk_125_i;
--- STAT_OP(1) <= rst;
--- STAT_OP(2) <= rx_serdes_rst;
--- STAT_OP(3) <= rx_pcs_rst;
---
--- STAT_OP(4) <= tx_pcs_rst;
--- STAT_OP(5) <= rst_qd;
--- STAT_OP(6) <= tx_pll_lol;
--- STAT_OP(7) <= rx_cdr_lol;
---
--- STAT_OP(8) <= rx_los_low;
--- STAT_OP(9) <= rx_rst_fsm_ready_i;
--- STAT_OP(10) <= proper_byte_align_i;
--- STAT_OP(11) <= gear_to_serder_rst_i;
---
--- STAT_OP(12) <= serdes_rx_ready_i;
--- STAT_OP(13) <= wa_position(0);
--- STAT_OP(14) <= wa_position(1);
--- STAT_OP(15) <= wa_position(2);
-
-
--- STAT_OP(3) <= rx_valid_char_i;
--- STAT_OP(4) <= rx_see_ready0_i;
--- STAT_OP(5) <= rx_saw_ready1_i;
--- STAT_OP(6) <= rx_almost_ready_i;
--- STAT_OP(7) <= rx_ready_i;
--- STAT_OP(8) <= rx_reset_from_rm_i;
--- STAT_OP(9) <= tx_almost_ready_i;
--- STAT_OP(10) <= tx_ready_i;
--- STAT_OP(11) <= serdes_tx_ready_i;
--- STAT_OP(12) <= proper_byte_align_i;
--- STAT_OP(13) <= proper_word_align_i;
end architecture;
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="cbmnet_sfp1" module="cbmnet_sfp1" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 08 22 22:50:53.430" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="cbmnet_sfp1" module="cbmnet_sfp1" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 13:50:56.873" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="cbmnet_sfp1.lpc" type="lpc" modified="2013 08 22 22:50:46.000"/>
- <File name="cbmnet_sfp1.pp" type="pp" modified="2013 08 22 22:50:46.000"/>
- <File name="cbmnet_sfp1.sym" type="sym" modified="2013 08 22 22:50:46.000"/>
- <File name="cbmnet_sfp1.tft" type="tft" modified="2013 08 22 19:41:06.000"/>
- <File name="cbmnet_sfp1.txt" type="pcs_module" modified="2013 08 22 22:50:46.000"/>
- <File name="cbmnet_sfp1.vhd" type="top_level_vhdl" modified="2013 08 22 19:41:06.000"/>
+ <File name="cbmnet_sfp1.lpc" type="lpc" modified="2013 10 02 13:50:31.000"/>
+ <File name="cbmnet_sfp1.pp" type="pp" modified="2013 10 02 13:50:31.000"/>
+ <File name="cbmnet_sfp1.sym" type="sym" modified="2013 10 02 13:50:31.000"/>
+ <File name="cbmnet_sfp1.tft" type="tft" modified="2013 10 02 13:50:31.000"/>
+ <File name="cbmnet_sfp1.txt" type="pcs_module" modified="2013 10 02 13:50:31.000"/>
+ <File name="cbmnet_sfp1.vhd" type="top_level_vhdl" modified="2013 10 02 13:50:31.000"/>
</Package>
</DiamondModule>
ModuleName=cbmnet_sfp1
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=08/22/2013
-Time=22:50:46
+Date=10/02/2013
+Time=13:50:31
[Parameters]
Verilog=0
_rxrefclk_rate1=125.0
_rxrefclk_rate2=125.0
_rxrefclk_rate3=125.0
-_rx_data_width0=16
+_rx_data_width0=8
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
-_rx_ficlk_rate0=125.0
+_rx_ficlk_rate0=250.0
_rx_ficlk_rate1=250.0
_rx_ficlk_rate2=250.0
_rx_ficlk_rate3=250.0
#define _ch0_rx_datarange "MEDHIGH"
#define _ch0_rx_data_rate "FULL"
#define _ch0_rxrefclk_rate "125.0"
-#define _ch0_rx_data_width "16"
-#define _ch0_rx_fifo "ENABLED"
-#define _ch0_rx_ficlk_rate 125.0
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "DISABLED"
+#define _ch0_rx_ficlk_rate 250.0
#define _ch0_tdrv "0"
#define _ch0_tx_pre "DISABLED"
#define _ch0_rterm_tx "50"
#define _sci_int_port "DISABLED"
#define _refck2core "DISABLED"
#define _circuit_name cbmnet_sfp1
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
#include <pcs/pcsd_cfg.txt>
--- /dev/null
+
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: Lattice Semiconductor Corporation
+ MODULE: cbmnet_sfp1
+ DESIGN: cbmnet_sfp1
+ FILENAME: cbmnet_sfp1.readme
+ PROJECT: Unknown
+ VERSION: 2.0
+ This file is auto generated by the ispLEVER
+
+
+NOTE: This readme file has been provided to instantiate the interface
+netlist. Since this template contains synthesis attributes for precision that
+are crucial to the design flow, we recommend that you use this
+template in your FPGA design.
+entity chip is
+port (
+
+-- Add your FPGA design top level I/Os here
+
+
+-- ASIC side pins for PCSD. These pins must exist for the
+-- PCS core.
+ refclkp : in std_logic;
+ refclkn : in std_logic;
+ hdinp_ch0 : in std_logic;
+ hdinn_ch0 : in std_logic;
+ hdinp_ch1 : in std_logic;
+ hdinn_ch1 : in std_logic;
+ hdinp_ch2 : in std_logic;
+ hdinn_ch2 : in std_logic;
+ hdinp_ch3 : in std_logic;
+ hdinn_ch3 : in std_logic;
+
+ hdoutp_ch0 : out std_logic;
+ hdoutn_ch0 : out std_logic;
+ hdoutp_ch1 : out std_logic;
+ hdoutn_ch1 : out std_logic;
+ hdoutp_ch2 : out std_logic;
+ hdoutn_ch2 : out std_logic;
+ hdoutp_ch3 : out std_logic;
+ hdoutn_ch3 : out std_logic;
+
+
+);
+end chip;
+
+architecture chip_arch of chip is
+
+-- This defines all the high-speed ports. You may have to remove
+-- some of them depending on your design.
+attribute nopad : string;
+attribute nopad of
+ refclkp, refclkn,
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
+
+ COMPONENT cbmnet_sfp1
+ PORT(
+ hdinp_ch0 : IN std_logic;
+ hdinn_ch0 : IN std_logic;
+ sci_sel_ch0 : IN std_logic;
+ txiclk_ch0 : IN std_logic;
+ fpga_rxrefclk_ch0 : IN std_logic;
+ txdata_ch0 : IN std_logic_vector(15 downto 0);
+ tx_k_ch0 : IN std_logic_vector(1 downto 0);
+ tx_force_disp_ch0 : IN std_logic_vector(1 downto 0);
+ tx_disp_sel_ch0 : IN std_logic_vector(1 downto 0);
+ rx_serdes_rst_ch0_c : IN std_logic;
+ sb_felb_ch0_c : IN std_logic;
+ sb_felb_rst_ch0_c : IN std_logic;
+ tx_pcs_rst_ch0_c : IN std_logic;
+ tx_pwrup_ch0_c : IN std_logic;
+ rx_pcs_rst_ch0_c : IN std_logic;
+ rx_pwrup_ch0_c : IN std_logic;
+ tx_div2_mode_ch0_c : IN std_logic;
+ rx_div2_mode_ch0_c : IN std_logic;
+ sci_wrdata : IN std_logic_vector(7 downto 0);
+ sci_addr : IN std_logic_vector(5 downto 0);
+ sci_sel_quad : IN std_logic;
+ sci_rd : IN std_logic;
+ sci_wrn : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_serdes_rst_c : IN std_logic;
+ rst_qd_c : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ hdoutp_ch0 : OUT std_logic;
+ hdoutn_ch0 : OUT std_logic;
+ rx_full_clk_ch0 : OUT std_logic;
+ rx_half_clk_ch0 : OUT std_logic;
+ tx_full_clk_ch0 : OUT std_logic;
+ tx_half_clk_ch0 : OUT std_logic;
+ rxdata_ch0 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch0 : OUT std_logic;
+ rx_disp_err_ch0 : OUT std_logic;
+ rx_cv_err_ch0 : OUT std_logic;
+ rx_los_low_ch0_s : OUT std_logic;
+ lsm_status_ch0_s : OUT std_logic;
+ rx_cdr_lol_ch0_s : OUT std_logic;
+ sci_rddata : OUT std_logic_vector(7 downto 0);
+ tx_pll_lol_qd_s : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+ uut: cbmnet_sfp1 PORT MAP(
+ hdinp_ch0 => hdinp_ch0,
+ hdinn_ch0 => hdinn_ch0,
+ hdoutp_ch0 => hdoutp_ch0,
+ hdoutn_ch0 => hdoutn_ch0,
+ sci_sel_ch0 => sci_sel_ch0,
+ txiclk_ch0 => txiclk_ch0,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ tx_full_clk_ch0 => tx_full_clk_ch0,
+ tx_half_clk_ch0 => tx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
+ txdata_ch0 => txdata_ch0,
+ tx_k_ch0 => tx_k_ch0,
+ tx_force_disp_ch0 => tx_force_disp_ch0,
+ tx_disp_sel_ch0 => tx_disp_sel_ch0,
+ rxdata_ch0 => rxdata_ch0,
+ rx_k_ch0 => rx_k_ch0,
+ rx_disp_err_ch0 => rx_disp_err_ch0,
+ rx_cv_err_ch0 => rx_cv_err_ch0,
+ rx_serdes_rst_ch0_c => rx_serdes_rst_ch0_c,
+ sb_felb_ch0_c => sb_felb_ch0_c,
+ sb_felb_rst_ch0_c => sb_felb_rst_ch0_c,
+ tx_pcs_rst_ch0_c => tx_pcs_rst_ch0_c,
+ tx_pwrup_ch0_c => tx_pwrup_ch0_c,
+ rx_pcs_rst_ch0_c => rx_pcs_rst_ch0_c,
+ rx_pwrup_ch0_c => rx_pwrup_ch0_c,
+ rx_los_low_ch0_s => rx_los_low_ch0_s,
+ lsm_status_ch0_s => lsm_status_ch0_s,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
+ tx_div2_mode_ch0_c => tx_div2_mode_ch0_c,
+ rx_div2_mode_ch0_c => rx_div2_mode_ch0_c,
+ sci_wrdata => sci_wrdata,
+ sci_addr => sci_addr,
+ sci_rddata => sci_rddata,
+ sci_sel_quad => sci_sel_quad,
+ sci_rd => sci_rd,
+ sci_wrn => sci_wrn,
+ fpga_txrefclk => fpga_txrefclk,
+ tx_serdes_rst_c => tx_serdes_rst_c,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_s,
+ rst_qd_c => rst_qd_c,
+ serdes_rst_qd_c => serdes_rst_qd_c
+ );
+
+
+
+
CH0_RX_DATA_RATE "FULL"
CH0_TX_DATA_RATE "FULL"
CH0_TX_DATA_WIDTH "16"
-CH0_RX_DATA_WIDTH "16"
+CH0_RX_DATA_WIDTH "8"
CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "ENABLED"
+CH0_RX_FIFO "DISABLED"
CH0_TDRV "0"
#CH0_TX_FICLK_RATE 125.0
#CH0_RXREFCLK_RATE "125.0"
-#CH0_RX_FICLK_RATE 125.0
+#CH0_RX_FICLK_RATE 250.0
CH0_TX_PRE "DISABLED"
CH0_RTERM_TX "50"
CH0_RX_EQ "DISABLED"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
tx_k_ch0 : in std_logic_vector (1 downto 0);
tx_force_disp_ch0 : in std_logic_vector (1 downto 0);
tx_disp_sel_ch0 : in std_logic_vector (1 downto 0);
- rxdata_ch0 : out std_logic_vector (15 downto 0);
- rx_k_ch0 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch0 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch0 : out std_logic_vector (1 downto 0);
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
rx_serdes_rst_ch0_c : in std_logic;
sb_felb_ch0_c : in std_logic;
sb_felb_rst_ch0_c : in std_logic;
sci_sel_quad : in std_logic;
sci_rd : in std_logic;
sci_wrn : in std_logic;
- sci_int : out std_logic;
fpga_txrefclk : in std_logic;
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_RXI_CLK_0 => fpsc_vlo,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
FF_RX_D_0_5 => rxdata_ch0(5),
FF_RX_D_0_6 => rxdata_ch0(6),
FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0(0),
- FF_RX_D_0_9 => rx_disp_err_ch0(0),
- FF_RX_D_0_10 => rx_cv_err_ch0(0),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => rxdata_ch0(8),
- FF_RX_D_0_13 => rxdata_ch0(9),
- FF_RX_D_0_14 => rxdata_ch0(10),
- FF_RX_D_0_15 => rxdata_ch0(11),
- FF_RX_D_0_16 => rxdata_ch0(12),
- FF_RX_D_0_17 => rxdata_ch0(13),
- FF_RX_D_0_18 => rxdata_ch0(14),
- FF_RX_D_0_19 => rxdata_ch0(15),
- FF_RX_D_0_20 => rx_k_ch0(1),
- FF_RX_D_0_21 => rx_disp_err_ch0(1),
- FF_RX_D_0_22 => rx_cv_err_ch0(1),
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
FF_RX_D_0_23 => open,
FFC_RRST_0 => rx_serdes_rst_ch0_c,
SCIRD => sci_rd,
SCIWSTN => sci_wrn,
CYAWSTN => fpsc_vlo,
- SCIINT => sci_int,
+ SCIINT => open,
FFC_CK_CORE_TX => fpga_txrefclk,
FFC_MACRO_RST => serdes_rst_qd_c,
FFC_QUAD_RST => rst_qd_c,
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
-add_file -vhdl -lib work "./code/cbmnet_pkg.vhd"
+add_file -vhdl -lib work "./code/cbmnet_interface_pkg.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_pkg.vhd"
add_file -vhdl -lib work "./cores/cbmnet_sfp1.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "./code/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
+add_file -vhdl -lib work "./code/cbmnet_phy_gear.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd"
add_file -vhdl -lib work "./trb3_periph_cbmnet.vhd"
-- CBMNet signals
constant NUM_LANES : integer := 1;
- signal cbm_clk : std_logic; -- Main clock
signal cbm_res_n : std_logic; -- Active low reset; can be changed by define
signal cbm_link_active : std_logic; -- link is active and can send and receive data
signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0');
signal phy_debug_i : std_logic_vector (127 downto 0) := (others => '0');
+
+ signal dlm_counter : unsigned(31 downto 0);
begin
clk_125_i <= CLK_GPLL_LEFT;
TX_SLAVE => 1
)
port map (
- clk => cbm_clk,
+ -- Clk & Reset
+ clk => rclk_125_i,
res_n => cbm_res_n,
+
+ -- Phy
+ data_from_link => cbm_data_from_link,
+ data2link => cbm_data2link,
+ link_activeovr => '0',
+ link_readyovr => '0',
+ SERDES_ready => cbm_SERDES_ready,
+
+ -- CBMNet Interface
link_active => cbm_link_active,
ctrl2send_stop => cbm_ctrl2send_stop,
ctrl2send_start => cbm_ctrl2send_start,
ctrl_rec => cbm_ctrl_rec,
ctrl_rec_start => cbm_ctrl_rec_start,
ctrl_rec_end => cbm_ctrl_rec_end,
- ctrl_rec_stop => cbm_ctrl_rec_stop,
- data_from_link => cbm_data_from_link,
- data2link => cbm_data2link,
- link_activeovr => cbm_link_activeovr,
- link_readyovr => cbm_link_readyovr,
- SERDES_ready => cbm_SERDES_ready
+ ctrl_rec_stop => cbm_ctrl_rec_stop
+
);
+ cbm_res_n <= not rreset_i;
TEST_LINE(7 downto 0) <= phy_stat_debug(7 downto 0);
TEST_LINE(8) <= cbm_SERDES_ready;
TEST_LINE(11) <= rreset_i;
TEST_LINE(15 downto 12) <= (others => '0');
- GEN_FEE_TEST_LOGIC: if CBM_FEE_MODE = c_YES generate
- TEST_LINE(10) <= cbm_dlm_rec_va;
- end generate;
-
-
GEN_MST_TEST_LOGIC: if CBM_FEE_MODE = c_NO generate
process is
constant counter_max : integer := 1250000;
end if;
end if;
end process;
-
- TEST_LINE(10) <= cbm_dlm2send_va;
end generate;
+
+ PROC_DLM_COUNTER: process is begin
+ wait until rising_edge(rclk_125_i);
+
+ TEST_LINE(10) <= '0';
+ if rreset_i = '1' then
+ dlm_counter <= TO_UNSIGNED(0,32);
+
+ elsif cbm_dlm2send_va='1' or cbm_dlm_rec_va='1' then
+ TEST_LINE(10) <= '1';
+ dlm_counter <= dlm_counter + TO_UNSIGNED(1, 32);
+ end if;
+ end process;
+
+
PROC_REGIO_DEBUG: process is
variable address : integer range 0 to 255;
begin
when 9 => debug_data_out <= phy_debug_i(31+32*1 downto 32*1);
when 10 => debug_data_out <= phy_debug_i(31+32*2 downto 32*2);
when 11 => debug_data_out <= phy_debug_i(31+32*3 downto 32*3);
+ when 12 => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter);
when others => debug_ack <= '0';
end case;
jspc29 / trb3.git / commitdiff