pixelcontrol interlude

diff --git a/mupix/Mupix8/tb/MupixShiftReg.vhd b/mupix/Mupix8/tb/MupixShiftReg.vhd
index 6d4ace1f33e21a7cf6e00429cd4ab17664a4817b..b0e4426a41203609d1cd82e8b7360673b2ddb866 100644 (file)
--- a/mupix/Mupix8/tb/MupixShiftReg.vhd
+++ b/mupix/Mupix8/tb/MupixShiftReg.vhd
@@ -7,6 +7,7 @@ use IEEE.numeric_std.all;
 
 entity MupixShiftReg is
        generic(
+           delay : time := 1 ns;
                pixeldac_shift_length : integer := 64
        );
        port(
@@ -26,18 +27,18 @@ begin
        process(clk1)
        begin   
                if clk1'event and clk1 = '1' then
-                       input_register <= sin after 10 ns;
+                       input_register <= sin after delay;
                end if;
        end process;    
                
     process(clk2)
     begin
        if clk2'event and clk2 = '1' then
-               pixeldac_shift_reg <= pixeldac_shift_reg(pixeldac_shift_length - 2 downto 0) & input_register after 10 ns;
+               pixeldac_shift_reg <= pixeldac_shift_reg(pixeldac_shift_length - 2 downto 0) & input_register after delay;
        end if;
     end process;       
        
-       sout <= pixeldac_shift_reg(pixeldac_shift_length - 1) after 10 ns;
+       sout <= pixeldac_shift_reg(pixeldac_shift_length - 1) after delay;
        
 end architecture RTL;
 

diff --git a/mupix/Mupix8/tb/PixCtrlTest.vhd b/mupix/Mupix8/tb/PixCtrlTest.vhd
index d97f944e1f921847c1f482db9ba669a238a419cf..b36e54ad49b6c1066b4a072b171655076b6be728 100644 (file)
--- a/mupix/Mupix8/tb/PixCtrlTest.vhd
+++ b/mupix/Mupix8/tb/PixCtrlTest.vhd
@@ -105,10 +105,11 @@ begin
        begin
                wait for 100 ns;
                --test control through trb slow control
---             TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000011",x"0083");
---             TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000013",x"0083");
---             TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000014",x"0083");
---             TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000",x"0083");
+               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000011",x"0083");
+               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000013",x"0083");
+               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000014",x"0083");
+               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000",x"0083");
+               wait for 300 ns;
                --test programming with data from FIFO via FPGA state machine
                TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083");
                TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA",x"0080");