} FlashType;
-static const char FlashTypeStr[][32] =
+static const char FlashTypeStr[16][32] =
{
"INVALID",
- "RICH_ADCM_V1", "RICH_ADCM_V2", "RICH_ADCM_V3",
- "MDC_HUB_V2_FPGA1234", "MDC_HUB_V2_FPGA5",
- "MDC_OEP_V2", "MDC_OEP_V3",
- "SHOWER_ADDON_V2_FPGA1", "SHOWER_ADDON_V2_FPGA2", "SHOWER_ADDON_V2_FPGA3",
- "CTS_FPGA1", "CTS_FPGA2"
+ "RICH_ADCM_V1",
+ "RICH_ADCM_V2",
+ "RICH_ADCM_V3",
+ "MDC_HUB_V2_FPGA1234",
+ "MDC_HUB_V2_FPGA5",
+ "MDC_OEP_V2",
+ "MDC_OEP_V3",
+ "SHOWER_ADDON_V2_FPGA1",
+ "SHOWER_ADDON_V2_FPGA2",
+ "SHOWER_ADDON_V2_FPGA3",
+ "CTS_FPGA1",
+ "CTS_FPGA2"
};
static FlashType flashType = FLASH_INVALID;
static uint32_t manId = 0;
-static const char trbflash_version[] = "$Revision: 2.18 $";
+static const char trbflash_version[] = "$Revision: 2.19 $";
static uint32_t mdcFlashSelect = 1;
if ((status = trb_register_write(trb_address, SetupReg,
(uint32_t)(value << 24))) == -1) {
fprintf(logFile, "Error > writeSetupRegister: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if (trb_term.status_channel != 0) {
fprintf(logFile,
"Error > writeSetupRegister: invalid Status returned %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if ((status = trb_register_read(trb_address, CtrlReg,
trbBuffer, TRB_BUFFER_SIZE)) == -1) {
fprintf(logFile, "Error > readCtrlRegister: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if ((status = trb_register_write(trb_address, CtrlReg,
value)) == -1) {
fprintf(logFile, "Error > writeCtrlRegister: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
trb_register_read(trb_address, BlockRam, trbBuffer,
TRB_BUFFER_SIZE)) == -1) {
fprintf(logFile, "Error > checkStatus: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if (trb_register_write(trb_address, BlockRam, (uint32_t)value) == -1) {
fprintf(logFile, "Error > writeStatusRegister: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if (sendCommand(trb_address, 0x01 << 24, 0) == -1) {
if ((status =
trb_register_read(trb_address, HardwareId, trbBuffer,
TRB_BUFFER_SIZE)) == -1) {
- fprintf(logFile, "Error > initTransfer: read HardwareIds TRBNet %s\n",
- trb_strerror(trb_errno));
+ fprintf(logFile, "Error > initTransfer, read HardwareIds: TRBNet %s\n",
+ trb_strerrorf());
return -1;
}
if ((status =
trb_register_read(trb_address, BlockRam, trbBuffer,
TRB_BUFFER_SIZE)) == -1) {
- fprintf(logFile, "Error > initTransfer: read ManIds TRBNet %s\n",
- trb_strerror(trb_errno));
+ fprintf(logFile, "Error > initTransfer, read ManIds: TRBNet %s\n",
+ trb_strerrorf());
return -1;
}
trbBuffer, TRB_BUFFER_SIZE))
== -1) {
fprintf(logFile, "Error > readPage: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
trbBuffer, size))
== -1) {
fprintf(logFile, "Error > writePage: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}
if (trb_register_write(trb_address, MDCFlashRomSelect,
(uint32_t)number) == -1) {
fprintf(logFile, "\nError > selcetMdcFlashRom: TRBNet %s\n",
- trb_strerror(trb_errno));
+ trb_strerrorf());
return -1;
}