added intermediate pinout for Trb3 read-out without new CB

diff --git a/electronics/electronics2013.pdf b/electronics/electronics2013.pdf
index 6027653e4956d48af9a3c4f922d61f2bd2686a1e..9a4d82f04e8279287980ce5d194be6d7a348f121 100644 (file)
Binary files a/electronics/electronics2013.pdf and b/electronics/electronics2013.pdf differ

diff --git a/electronics/electronics2013.tex b/electronics/electronics2013.tex
index 9eaeb8b9fd127602ef822fcea6d75c420b13e6fe..cc2783445855147c336d2658934a0504af224fac 100644 (file)
--- a/electronics/electronics2013.tex
+++ b/electronics/electronics2013.tex
@@ -270,59 +270,59 @@ to 2 and 4. In total, this yields 15 differential outputs.
 An additional ground cable is required between the power supplies for the CB and the stack of TRBs.
 
 
-
-\begin{table}[ht]
-\small
- \centering
-\begin{tabular}{c|c|c|c|cc|c|c}
- & \multicolumn{2}{c|}{\textbf{single}} & \multicolumn{3}{c|}{\textbf{differ.}} &
-\multicolumn{2}{c}{\textbf{Groups}}\\
-\textbf{Pair} & \textbf{I} & \textbf{O} & \textbf{I} & \multicolumn{2}{c|}{\textbf{O}} & \textbf{Con
-1} & \textbf{Con 2}\\
-\hline
-1  & X & X & X & -- & X  & 0   & 0   \\
-2  & X & X & X & -- & X  & 0   & 0   \\
-3  & X & X & X &  X & -- & 0   & 0 C \\
-4  & X & X & X & -- & -- & 0 C & 0   \\
-5  & X & X & X &  X & X  & 0   & 0   \\
-6  & X & - & X &  X & -- & 0   & 0   \\
-7  & X & X & X & -- & -- & 1   & 1   \\
-8  & X & X & X &  X & X  & 1   & 1   \\
-9  & X & X & X & -- & X  & 1   & 1   \\
-10 & X & X & X & -- & -- & 1 C & 1 C \\
-11 & X & X & X &  X & X  & 1   & 1   \\
-12 & X & X & X &  X & -- & 1   & 1   \\
-13 & X & X & X & -- & X  & 2   & 2   \\
-14 & X & X & X &  X & -- & 2   & 2   \\
-15 & X & X & X & -- & X  & 2   & 2   \\
-16 & X & X & X & -- & -- & 2 C & 2 C \\
-17 & X & X & X & -- & -- & 3   & 3   \\
-18 & X & X & X &  X & X  & 3   & 3   \\
-19 & X & X & X &  X & -- & 3   & 3   \\
-20 & X & X & X & -- & -- & 3 C & 3 C \\
-21 & X & X & X & -- & -- & 3   & 3   \\
-22 & X & X & X &  X & X  & 3   & 3   \\
-23 & X & X & X & -- & -- & 4   & 4   \\
-24 & X & X & X &  X & X  & 4   & 4   \\
-25 & X & X & X & -- & X  & 4   & 4   \\
-26 & X & X & X & -- & -- & 4 C & 4 C \\
-27 & X & X & X &  X & -- & 4   & 4   \\
-28 & X & X & X &  X & X  & 4   & 4   \\
-29 & X & X & X & -- & -- & 5   & 5   \\
-30 & X & X & X &  X & X  & 5   & 5   \\
-31 & X & X & X &  X & X  & 5   & 5   \\
-32 & X & X & X & -- & -- & 5 C & 5 C \\
-33 & - & - & - & -- & -- & GND & GND  \\
-34 & X & X & X & -- & -- & 6 C & 2   \\
-35 & X & X & X &  X & X  & 6   & 2   \\
-36 & X & X & X &  X & X  & 6   & 5   \\
-37 & X & X & X &  X & X  & 6   & 5   \\
-38 & - & - & - & -- & -- & F5 & F5 \\
-39 & X & - & X & -- & -- & Spare & Spare \\
-40 & - & - & - & -- & -- & F5 & F5 \\
-\end{tabular}
-\caption{Pin-out of ADA AddOn and cable between FPGA and CB.}
-\end{table}
+% 
+% \begin{table}[ht]
+% \small
+%  \centering
+% \begin{tabular}{c|c|c|c|cc|c|c}
+%  & \multicolumn{2}{c|}{\textbf{single}} & \multicolumn{3}{c|}{\textbf{differ.}} &
+% \multicolumn{2}{c}{\textbf{Groups}}\\
+% \textbf{Pair} & \textbf{I} & \textbf{O} & \textbf{I} & \multicolumn{2}{c|}{\textbf{O}} & \textbf{Con
+% 1} & \textbf{Con 2}\\
+% \hline
+% 1  & X & X & X & -- & X  & 0   & 0   \\
+% 2  & X & X & X & -- & X  & 0   & 0   \\
+% 3  & X & X & X &  X & -- & 0   & 0 C \\
+% 4  & X & X & X & -- & -- & 0 C & 0   \\
+% 5  & X & X & X &  X & X  & 0   & 0   \\
+% 6  & X & - & X &  X & -- & 0   & 0   \\
+% 7  & X & X & X & -- & -- & 1   & 1   \\
+% 8  & X & X & X &  X & X  & 1   & 1   \\
+% 9  & X & X & X & -- & X  & 1   & 1   \\
+% 10 & X & X & X & -- & -- & 1 C & 1 C \\
+% 11 & X & X & X &  X & X  & 1   & 1   \\
+% 12 & X & X & X &  X & -- & 1   & 1   \\
+% 13 & X & X & X & -- & X  & 2   & 2   \\
+% 14 & X & X & X &  X & -- & 2   & 2   \\
+% 15 & X & X & X & -- & X  & 2   & 2   \\
+% 16 & X & X & X & -- & -- & 2 C & 2 C \\
+% 17 & X & X & X & -- & -- & 3   & 3   \\
+% 18 & X & X & X &  X & X  & 3   & 3   \\
+% 19 & X & X & X &  X & -- & 3   & 3   \\
+% 20 & X & X & X & -- & -- & 3 C & 3 C \\
+% 21 & X & X & X & -- & -- & 3   & 3   \\
+% 22 & X & X & X &  X & X  & 3   & 3   \\
+% 23 & X & X & X & -- & -- & 4   & 4   \\
+% 24 & X & X & X &  X & X  & 4   & 4   \\
+% 25 & X & X & X & -- & X  & 4   & 4   \\
+% 26 & X & X & X & -- & -- & 4 C & 4 C \\
+% 27 & X & X & X &  X & -- & 4   & 4   \\
+% 28 & X & X & X &  X & X  & 4   & 4   \\
+% 29 & X & X & X & -- & -- & 5   & 5   \\
+% 30 & X & X & X &  X & X  & 5   & 5   \\
+% 31 & X & X & X &  X & X  & 5   & 5   \\
+% 32 & X & X & X & -- & -- & 5 C & 5 C \\
+% 33 & - & - & - & -- & -- & GND & GND  \\
+% 34 & X & X & X & -- & -- & 6 C & 2   \\
+% 35 & X & X & X &  X & X  & 6   & 2   \\
+% 36 & X & X & X &  X & X  & 6   & 5   \\
+% 37 & X & X & X &  X & X  & 6   & 5   \\
+% 38 & - & - & - & -- & -- & F5 & F5 \\
+% 39 & X & - & X & -- & -- & Spare & Spare \\
+% 40 & - & - & - & -- & -- & F5 & F5 \\
+% \end{tabular}
+% \caption{Pin-out of ADA AddOn and cable between FPGA and CB.}
+% \end{table}
 
 
 \begin{table}[ht]
@@ -363,5 +363,7 @@ connects to C1/C3, second board to C2/C4.}
 \end{table}
 
 
+\input{intermediatetrb3}
+
 \end{document}
 

diff --git a/electronics/intermediatetrb3.tex b/electronics/intermediatetrb3.tex
new file mode 100644 (file)
index 0000000..61412f3
--- /dev/null
+++ b/electronics/intermediatetrb3.tex
@@ -0,0 +1,102 @@
+\subsection{Intermediate Pin-out for TRB3}
+
+
+
+\begin{table}[ht]
+ \centering
+\begin{tabular}{c|c|c|c|c|l}
+ \textbf{Wire} & \textbf{IO} & \textbf{Group}  & \textbf{RJ45} & \textbf{Pair} &
+\textbf{Name}\\
+\hline
+INP0  & -- & 0   &  &  &  \\
+INP1  & -- & 0   &  &  &  \\
+INP2  &  X & 0   & 1 & 7/8 & MapsClkOut \\
+INP3  & -- & 0C  &  &  &  \\
+INP4  &  X & 0   & 1 & 5/6 & MapsStartOut \\
+INP5  &  X & 0   & 1 & 3/4 & MapsResetOut \\
+INP6  & -- & 1   &  &  &  \\
+INP7  &  X & 1   & 2 & 1/2 & JtagTckOut \\
+INP8  & -- & 1   & 3 & 1/2 & JtagTdoIn \\
+INP9  & -- & 1C  &  &  &  \\
+INP10 &  X & 1   & 2 & 5/6 & JtagTmsOut \\
+INP11 &  X & 1   & 2 & 3/4 & JtagTdiOut \\
+INP12 & -- & 2   & 4 &  & Sensor0Marker\\
+INP13 &  X & 2   & 4 &  & Sensor0Data0 \\
+INP14 & -- & 2   & 4 &  & Sensor0Data1 \\
+INP15 & -- & 2C  & 4 &  & Sensor0Clock \\
+INP16 & -- & 3   & 5 &  & Sensor1Marker\\
+INP17 &  X & 3   & 5 &  & Sensor1Data0 \\
+INP18 &  X & 3   & 5 &  & Sensor1Data1  \\
+INP19 & -- & 3C  & 5 &  & Sensor1Clock  \\
+INP20 & -- & 3   &  &  &  \\
+INP21 &  X & 3   & 6 &  & JtagSwitch0 \\
+INP22 & -- & 4   &  &  &  \\
+INP23 &  X & 4   & 6 &  & JtagSwitch1 \\
+INP24 & -- & 4   &  &  &  \\
+INP25 & -- & 4C  &  &  &  \\
+INP26 &  X & 4   &  &  &  \\
+INP27 &  X & 4   &  &  &  \\
+INP28 & -- & 5   &  &  &  \\
+INP29 &  X & 5   &  &  &  \\
+INP30 &  X & 5   &  &  &  \\
+INP31 & -- & 5C  &  &  &  \\
+
+\end{tabular}
+\caption{Intermediate Pin-out concept based on Ada-AddOn and patch panel }
+\end{table}
+
+
+% 
+% 
+% LOCATE COMP  "INP_0"    SITE "P1";     #"DQLL_0"    DQLL0_0   #1
+% # LOCATE COMP  "INN_0"    SITE "P2";     #"DQLL_1"    DQLL0_1   #3
+% LOCATE COMP  "INP_1"    SITE "T2";     #"DQLL_2"    DQLL0_2   #5
+% # LOCATE COMP  "INN_1"    SITE "U3";     #"DQLL_3"    DQLL0_3   #7
+% LOCATE COMP  "INP_2"    SITE "R1";     #"DQLL_4"    DQLL0_4   #9
+% # LOCATE COMP  "INN_2"    SITE "R2";     #"DQLL_5"    DQLL0_5   #11
+% LOCATE COMP  "INP_3"    SITE "N3";     #"DQLL_6"    DQSLL0_T  #13
+% # LOCATE COMP  "INN_3"    SITE "P3";     #"DQLL_7"    DQSLL0_C  #15
+% LOCATE COMP  "INP_4"    SITE "P5";     #"DQLL_8"    DQLL0_6   #17
+% # LOCATE COMP  "INN_4"    SITE "P6";     #"DQLL_9"    DQLL0_7   #19
+% LOCATE COMP  "INP_5"   SITE "N5";      #"DQLL_10"   DQLL0_8   #21
+% # LOCATE COMP  "INN_5"   SITE "N6";     #"DQLL_11"   DQLL0_9   #23
+% 
+% LOCATE COMP  "INP_22"   SITE "V1";     #"DQLL_12"   DQLL1_0   #26
+% # LOCATE COMP  "INN_22"   SITE "U2";     #"DQLL_13"   DQLL1_1   #28
+% LOCATE COMP  "INP_23"   SITE "T1";     #"DQLL_14"   DQLL1_2   #30
+% # LOCATE COMP  "INN_23"   SITE "U1";     #"DQLL_15"   DQLL1_3   #32
+% LOCATE COMP  "INP_24"   SITE "P4";     #"DQLL_16"   DQLL1_4   #34
+% # LOCATE COMP  "INN_24"   SITE "R3";     #"DQLL_17"   DQLL1_5   #36
+% LOCATE COMP  "INP_25"   SITE "T3";     #"DQLL_18"   DQSLL1_T  #38
+% # LOCATE COMP  "INN_25"   SITE "R4";     #"DQLL_19"   DQSLL1_C  #40
+% LOCATE COMP  "INP_26"   SITE "R5";     #"DQLL_20"   DQLL1_6   #42
+% # LOCATE COMP  "INN_26"   SITE "R6";     #"DQLL_21"   DQLL1_7   #44
+% LOCATE COMP  "INP_27"   SITE "T7";     #"DQLL_22"   DQLL1_8   #46
+% # LOCATE COMP  "INN_27"   SITE "T8";     #"DQLL_23"   DQLL1_9   #48
+% 
+% LOCATE COMP  "INP_6"   SITE "AC2";    #"DQLL_24"   DQLL2_0   #25
+% # LOCATE COMP  "INN_6"   SITE "AC3";    #"DQLL_25"   DQLL2_1   #27
+% LOCATE COMP  "INP_7"   SITE "AB1";    #"DQLL_26"   DQLL2_2   #29
+% # LOCATE COMP  "INN_7"   SITE "AC1";    #"DQLL_27"   DQLL2_3   #31
+% LOCATE COMP  "INP_8"   SITE "AA1";    #"DQLL_28"   DQLL2_4   #33
+% # LOCATE COMP  "INN_8"   SITE "AA2";    #"DQLL_29"   DQLL2_5   #35
+% LOCATE COMP  "INP_9"   SITE "W7";     #"DQLL_30"   DQLL2_T   #37  #should be DQSLL2
+% # LOCATE COMP  "INN_9"   SITE "W6";     #"DQLL_31"   DQLL2_C   #39  #should be DQSLL2
+% LOCATE COMP  "INP_10"   SITE "Y5";     #"DQLL_32"   DQLL2_6   #41
+% # LOCATE COMP  "INN_10"   SITE "AA5";    #"DQLL_33"   DQLL2_7   #43
+% LOCATE COMP  "INP_11"   SITE "V6";     #"DQLL_34"   DQLL2_8   #45
+% # LOCATE COMP  "INN_11"   SITE "V7";     #"DQLL_35"   DQLL2_9   #47
+% 
+% LOCATE COMP  "INP_16"   SITE "AD1";    #"DQLL_36"   DQLL3_0   #2
+% # LOCATE COMP  "INN_16"   SITE "AD2";    #"DQLL_37"   DQLL3_1   #4
+% LOCATE COMP  "INP_17"   SITE "AB5";    #"DQLL_38"   DQLL3_2   #6
+% # LOCATE COMP  "INN_17"   SITE "AB6";    #"DQLL_39"   DQLL3_3   #8
+% LOCATE COMP  "INP_18"   SITE "AB3";    #"DQLL_40"   DQLL3_4   #10
+% # LOCATE COMP  "INN_18"   SITE "AB4";    #"DQLL_41"   DQLL3_5   #12
+% LOCATE COMP  "INP_19"   SITE "Y6";     #"DQLL_42"   DQLL3_T   #14  #should be DQSLL3
+% # LOCATE COMP  "INN_19"   SITE "Y7";     #"DQLL_43"   DQLL3_C   #16  #should be DQSLL3
+% LOCATE COMP  "INP_20"   SITE "AA3";    #"DQLL_44"   DQLL3_6   #18
+% # LOCATE COMP  "INN_20"   SITE "AA4";    #"DQLL_45"   DQLL3_7   #20
+% LOCATE COMP  "INP_21"   SITE "W8";     #"DQLL_46"   DQLL3_8   #22
+% # LOCATE COMP  "INN_21"   SITE "W9";     #"DQLL_47"   DQLL3_9   #24
+% 
\ No newline at end of file

diff --git a/electronics/powermeasurements.pdf b/electronics/powermeasurements.pdf
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