]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadaq <hadaq>
Tue, 29 Jun 2010 08:57:05 +0000 (08:57 +0000)
committerhadaq <hadaq>
Tue, 29 Jun 2010 08:57:05 +0000 (08:57 +0000)
lattice/scm/lattice_ecp2m_fifo_16bit_dualport.lpc [new file with mode: 0755]
lattice/scm/lattice_ecp2m_fifo_16bit_dualport.vhd [new file with mode: 0755]

diff --git a/lattice/scm/lattice_ecp2m_fifo_16bit_dualport.lpc b/lattice/scm/lattice_ecp2m_fifo_16bit_dualport.lpc
new file mode 100755 (executable)
index 0000000..8ea4e9e
--- /dev/null
@@ -0,0 +1,48 @@
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO_DC\r
+CoreRevision=5.4\r
+ModuleName=lattice_ecp2m_fifo_16bit_dualport\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:56:28\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+RDepth=512\r
+RWidth=36\r
+WDepth=512\r
+WWidth=36\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Single Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+Reset=Async\r
+RDataCount=0\r
+WDataCount=0\r
+EnECC=0\r
diff --git a/lattice/scm/lattice_ecp2m_fifo_16bit_dualport.vhd b/lattice/scm/lattice_ecp2m_fifo_16bit_dualport.vhd
new file mode 100755 (executable)
index 0000000..4b0e447
--- /dev/null
@@ -0,0 +1,181 @@
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module  Version: 5.4
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n lattice_ecp2m_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 36 -rwidth 36 -no_enable -pe -1 -pf -1 -e 
+
+-- Tue Jun 29 10:56:28 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_ecp2m_fifo_16bit_dualport is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end lattice_ecp2m_fifo_16bit_dualport;
+
+architecture Structure of lattice_ecp2m_fifo_16bit_dualport is
+
+    -- internal signal declarations
+    signal scuba_vlo: std_logic;
+    signal partial_full: std_logic;
+    signal partial_empty: std_logic;
+    signal scuba_vhi: std_logic;
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b011111111000001";
+    attribute FULLPOINTER of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b011111111100001";
+    attribute AFPOINTER1 of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b111111110100001";
+    attribute AFPOINTER of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b111111111000001";
+    attribute AEPOINTER1 of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b000000000011111";
+    attribute AEPOINTER of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b111111111111111";
+    attribute RESETMODE of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "ASYNC";
+    attribute REGMODE of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "NOREG";
+    attribute CSDECODE_R of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b11";
+    attribute CSDECODE_W of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "0b11";
+    attribute DATA_WIDTH_R of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "36";
+    attribute DATA_WIDTH_W of lattice_ecp2m_fifo_16bit_dualport_0_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    lattice_ecp2m_fifo_16bit_dualport_0_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "111111110100001", AFPOINTER=> "111111111000001", 
+        AEPOINTER1=> "000000000011111", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, 
+            WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), 
+            DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), 
+            DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), 
+            DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), 
+            DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), 
+            DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), 
+            DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), 
+            DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>partial_empty, 
+            AFF=>partial_full, FF=>Full_int);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_ecp2m_fifo_16bit_dualport is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on