added flash ctrl, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
new file mode 100644 (file)
index 0000000..9ec5a76
--- /dev/null
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -0,0 +1,228 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library machxo3lf;\r
+use machxo3lf.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+\r
+entity generic_flash_ctrl is\r
+  port(\r
+    CLK   : in  std_logic;\r
+    RESET : in  std_logic;\r
+\r
+    -- SPI in host direction\r
+    SPI_DATA_IN   : in  std_logic_vector(15 downto 0);\r
+    SPI_DATA_OUT  : out std_logic_vector(15 downto 0);\r
+    SPI_ADDR_IN   : in  std_logic_vector(7 downto 0);\r
+    SPI_WRITE_IN  : in  std_logic;\r
+    SPI_READ_IN   : in  std_logic;\r
+    SPI_READY_OUT : out std_logic;\r
+        \r
+    -- SPI in local direction\r
+    LOC_DATA_OUT  : out std_logic_vector(15 downto 0);\r
+    LOC_DATA_IN   : in  std_logic_vector(15 downto 0);\r
+    LOC_ADDR_OUT  : out std_logic_vector(7 downto 0);\r
+    LOC_WRITE_OUT : out std_logic;\r
+    LOC_READ_OUT  : out std_logic;\r
+    LOC_READY_IN  : in  std_logic\r
+    \r
+    );\r
+end entity;\r
+\r
+architecture arch of generic_flash_ctrl is\r
+\r
+  component UFM_WB\r
+    port(\r
+      clk_i : in std_logic;\r
+      rst_n : in std_logic;\r
+      cmd       : in std_logic_vector(2 downto 0);\r
+      ufm_page  : in std_logic_vector(12 downto 0);\r
+      GO        : in std_logic;\r
+      BUSY      : out std_logic;\r
+      ERR       : out std_logic;\r
+      mem_clk   : out std_logic;\r
+      mem_we    : out std_logic;\r
+      mem_ce    : out std_logic;\r
+      mem_addr  : out std_logic_vector(3 downto 0);\r
+      mem_wr_data : out std_logic_vector(7 downto 0);\r
+      mem_rd_data : in  std_logic_vector(7 downto 0)\r
+      );\r
+  end component;\r
+\r
+  --component flashram\r
+  --  port (\r
+  --    DataInA: in  std_logic_vector(7 downto 0);\r
+  --    DataInB: in  std_logic_vector(7 downto 0);\r
+  --    AddressA: in  std_logic_vector(3 downto 0);\r
+  --    AddressB: in  std_logic_vector(3 downto 0);\r
+  --    ClockA: in  std_logic;\r
+  --    ClockB: in  std_logic;\r
+  --    ClockEnA: in  std_logic;\r
+  --    ClockEnB: in  std_logic;\r
+  --    WrA: in  std_logic;\r
+  --    WrB: in  std_logic;\r
+  --    ResetA: in  std_logic;\r
+  --    ResetB: in  std_logic;\r
+  --    QA: out  std_logic_vector(7 downto 0);\r
+  --    QB: out  std_logic_vector(7 downto 0)\r
+  --    );\r
+  --end component;\r
+\r
+  signal reg_SPI_DATA_OUT  : std_logic_vector(15 downto 0);\r
+  signal reg_SPI_READY_OUT : std_logic;\r
+  signal reg_LOC_DATA_OUT  : std_logic_vector(15 downto 0);\r
+  signal reg_LOC_ADDR_OUT  : std_logic_vector(7 downto 0);\r
+  signal reg_LOC_WRITE_OUT : std_logic;\r
+  signal reg_LOC_READ_OUT  : std_logic;\r
+  \r
+  signal flashram_addr_i : std_logic_vector(3 downto 0);\r
+  signal flashram_cen_i  : std_logic;\r
+  signal flashram_reset  : std_logic;\r
+  signal flashram_write_i: std_logic;\r
+  signal flashram_data_i : std_logic_vector(7 downto 0);\r
+  signal flashram_data_o : std_logic_vector(7 downto 0);\r
+\r
+  signal flash_command : std_logic_vector(2 downto 0);\r
+  signal flash_page    : std_logic_vector(12 downto 0);\r
+  signal flash_go      : std_logic;\r
+  signal flash_busy    : std_logic;\r
+  signal flash_err     : std_logic;\r
+  \r
+  signal ram_write_i : std_logic;\r
+  signal ram_data_i  : std_logic_vector(7 downto 0);\r
+  signal ram_data_o  : std_logic_vector(7 downto 0);\r
+  signal ram_addr_i  : std_logic_vector(3 downto 0);\r
+\r
+  signal enable_cfg_flash : std_logic;\r
+  signal testreg : std_logic_vector(15 downto 0);\r
+\r
+  signal out_delay : std_logic_vector(1 downto 0);\r
+  \r
+  \r
+begin\r
+  \r
+  THE_FLASH_RAM : entity work.flashram\r
+    port map(\r
+      DataInA   => ram_data_i,\r
+      DataInB   => flashram_data_i,\r
+      AddressA  => ram_addr_i,\r
+      AddressB  => flashram_addr_i,\r
+      ClockA    => CLK,\r
+      ClockB    => CLK,\r
+      ClockEnA  => '1',\r
+      ClockEnB  => flashram_cen_i,\r
+      WrA       => ram_write_i,\r
+      WrB       => flashram_write_i,\r
+      ResetA    => RESET,\r
+      ResetB    => RESET,\r
+      QA        => ram_data_o,\r
+      QB        => flashram_data_o\r
+      );\r
+\r
+  THE_FLASH : UFM_WB\r
+    port map(\r
+      clk_i     => CLK,\r
+      rst_n     => not RESET,\r
+      cmd       => flash_command,\r
+      ufm_page  => flash_page,\r
+      GO        => flash_go,\r
+      BUSY      => flash_busy,\r
+      ERR       => flash_err,\r
+      mem_clk    => open,\r
+      mem_we      => flashram_write_i,\r
+      mem_ce      => flashram_cen_i,\r
+      mem_addr    => flashram_addr_i,\r
+      mem_wr_data => flashram_data_i,\r
+      mem_rd_data => flashram_data_o\r
+      );\r
+\r
+\r
+  --ram_data_i <= LOC_DATA_IN(7 downto 0);\r
+  --ram_addr_i <= SPI_ADDR_IN(3 downto 0);\r
+\r
+  LOC_DATA_OUT  <= reg_LOC_DATA_OUT;\r
+  LOC_ADDR_OUT  <= reg_LOC_ADDR_OUT;\r
+  LOC_WRITE_OUT <= reg_LOC_WRITE_OUT;\r
+  LOC_READ_OUT  <= reg_LOC_READ_OUT;\r
+  SPI_DATA_OUT  <= reg_SPI_DATA_OUT;\r
+  SPI_READY_OUT <= reg_SPI_READY_OUT;\r
+  \r
+  \r
+PROC_SELECTOR : process begin\r
+  wait until rising_edge(CLK);\r
+\r
+  reg_LOC_DATA_OUT  <= SPI_DATA_IN;\r
+  reg_LOC_ADDR_OUT  <= SPI_ADDR_IN;\r
+  reg_LOC_WRITE_OUT <= SPI_WRITE_IN;\r
+  reg_LOC_READ_OUT  <= SPI_READ_IN;\r
+  reg_SPI_DATA_OUT  <= LOC_DATA_IN;\r
+  reg_SPI_READY_OUT <= LOC_READY_IN;\r
+\r
+  ram_write_i <= '0';\r
+  ram_data_i <= x"00";\r
+  ram_addr_i <= x"0";\r
+  flash_go <= '0';\r
+\r
+  if (SPI_WRITE_IN = '1') then\r
+    if (SPI_ADDR_IN(7 downto 4) = x"4") then\r
+      reg_LOC_WRITE_OUT <= '0';\r
+      ram_write_i <= '1';\r
+      ram_data_i  <= SPI_DATA_IN(7 downto 0);\r
+      ram_addr_i  <= SPI_ADDR_IN(3 downto 0);\r
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then\r
+      reg_LOC_WRITE_OUT <= '0';\r
+      enable_cfg_flash <= SPI_DATA_IN(0);\r
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5f") then\r
+      reg_LOC_WRITE_OUT <= '0';\r
+      testreg <= SPI_DATA_IN; \r
+    elsif (SPI_ADDR_IN(7 downto 0) = x"50") then\r
+      reg_LOC_WRITE_OUT <= '0';\r
+      flash_command <= SPI_DATA_IN(15 downto 13);\r
+      if(enable_cfg_flash = '1') then\r
+        flash_page <= SPI_DATA_IN(12 downto 0);\r
+      else\r
+        flash_page <= "111" & SPI_DATA_IN(9 downto 0);\r
+      end if;\r
+      flash_go <= '1';      \r
+    end if;\r
+  end if;\r
+\r
+  if (out_delay = "01") then\r
+    reg_LOC_READ_OUT  <= '0';\r
+    reg_SPI_READY_OUT <= '0';\r
+    out_delay <= "10";\r
+  elsif (out_delay = "10") then\r
+    reg_LOC_READ_OUT  <= '0';\r
+    reg_SPI_READY_OUT <= '1';\r
+    reg_SPI_DATA_OUT  <= flash_busy & flash_err & "000000" & ram_data_o;\r
+    out_delay <= "00";\r
+  else\r
+    out_delay <= "00";\r
+  end if;\r
+  \r
+  if (SPI_READ_IN = '1') then\r
+    if (SPI_ADDR_IN(7 downto 4) = x"4") then\r
+      out_delay <= "01";\r
+      reg_LOC_READ_OUT  <= '0';\r
+      reg_SPI_READY_OUT <= '0';\r
+      ram_addr_i <= SPI_ADDR_IN(3 downto 0);\r
+      --reg_SPI_READY_OUT <= '1';\r
+     -- reg_SPI_DATA_OUT  <= flash_busy & flash_err & "00" & ram_addr_i & ram_data_o;\r
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5f") then\r
+      reg_LOC_READ_OUT  <= '0';\r
+      reg_SPI_READY_OUT <= '1';\r
+      reg_SPI_DATA_OUT  <= testreg;\r
+    end if;\r
+  end if;\r
+  \r
+end process;\r
+\r
+        \r
+end architecture;\r
+\r
+       \r
+       \r
+\r