make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long;
end process;
-
+ pll_calibration : entity work.pll_in125_out33
+ port map (
+ CLK => CLK_SUPPL_PCLK,
+ CLKOP => clk_cal,
+ LOCK => open);
---------------------------------------------------------------------------
-- PCSA
CLK_READOUT => clk_sys, -- Clock for the readout
REFERENCE_TIME => cts_trigger_out, -- Reference time input
HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => CLK_SUPPL_PCLK, -- Hits for calibrating the TDC
+ HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
-- Trigger signals from handler
BUSRDO_RX => cts_rdo_rx,
BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR),
DEBUG_OUT => debug_clock_reset
);
--- pll_calibration : entity work.pll_in125_out33
--- port map (
--- CLK => CLK_SUPPL_PCLK,
--- CLKOP => clk_cal,
--- LOCK => open);
+ pll_calibration : entity work.pll_in125_out33
+ port map (
+ CLK => CLK_SUPPL_PCLK,
+ CLKOP => clk_cal,
+ LOCK => open);
-- GSR_N <= reset_i;
CLK_READOUT => clk_sys, -- Clock for the readout
REFERENCE_TIME => TRIG_LEFT, -- Reference time input
HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => CLK_SUPPL_PCLK, -- Hits for calibrating the TDC
+ HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
-- Trigger signals from handler
BUSRDO_RX => readout_rx,
BUSRDO_TX => readout_tx(0),