--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - fine time + (if 0x3ff full chain)
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F575";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82";
+
+ constant INCLUDE_UART : integer := c_NO; --300 slices
+ constant INCLUDE_SPI : integer := c_NO; --300 slices
+ constant INCLUDE_LCD : integer := c_NO; --800 slices
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
+ constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 32;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=mimosis_inp
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/03/2019
+Time=14:45:56
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Receive
+trioddr=0
+io_type=LVDS
+width=8
+freq_in=160
+bandwidth=2560
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Receive
+trioddr2=0
+io_type2=LVDS
+freq_in2=160
+gear=2:1
+aligned2=Centered
+width2=8
+DataLane=By Lane
+EnECLK=0
+Interface=GDDRX1_RX.SCLK.Centered
+Delay=Dynamic User Defined
+DelVal=1
+EnInEdge=
+NumEdge=BOTH
+EnDynamic=0
+GenPll=0
+Freq=
+AFreq=
+Reference=0
+IOBUF=
+ReceiverSync=0
+EnDynamicAlign=
+DynamicAlign=
+MIPIFilter=0
+enClkIBuf=0
+ClkIBuf=LVDS
+
+[Command]
+cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane
--- /dev/null
+<!DOCTYPE mimosis_inp>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>DDR_GENERIC</spirit:name>
+ <spirit:version>6.0</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./mimosis_inp.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./mimosis_inp.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-05-31.19:33:04</lattice:date>
+ <lattice:modified>2019-06-03.14:45:58</lattice:modified>
+ <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DDR_GENERIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">6.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">06/03/2019</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">mimosis_inp</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">14:45:56</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>AFreq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DataLane</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">By Lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DelVal</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Delay</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic User Defined</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamic</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECLK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnInEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Freq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>GenPll</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Interface</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">GDDRX1_RX.SCLK.Centered</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>MIPIFilter</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>NumEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BOTH</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ReceiverSync</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reference</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Centered</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>bandwidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2560</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>enClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>gear</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2:1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>pre-configuration</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>mimosis_inp</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc
+
+-- Mon Jun 3 14:45:58 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity mimosis_inp is
+ port (
+ clkin: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ data_cflag: out std_logic_vector(7 downto 0);
+ data_direction: in std_logic_vector(7 downto 0);
+ data_loadn: in std_logic_vector(7 downto 0);
+ data_move: in std_logic_vector(7 downto 0);
+ datain: in std_logic_vector(7 downto 0);
+ q: out std_logic_vector(15 downto 0));
+end mimosis_inp;
+
+architecture Structure of mimosis_inp is
+
+ -- internal signal declarations
+ signal buf_clkin: std_logic;
+ signal qb7: std_logic;
+ signal qa7: std_logic;
+ signal qb6: std_logic;
+ signal qa6: std_logic;
+ signal qb5: std_logic;
+ signal qa5: std_logic;
+ signal qb4: std_logic;
+ signal qa4: std_logic;
+ signal qb3: std_logic;
+ signal qa3: std_logic;
+ signal qb2: std_logic;
+ signal qa2: std_logic;
+ signal qb1: std_logic;
+ signal qa1: std_logic;
+ signal qb0: std_logic;
+ signal qa0: std_logic;
+ signal sclk_t: std_logic;
+ signal dataini_t7: std_logic;
+ signal dataini_t6: std_logic;
+ signal dataini_t5: std_logic;
+ signal dataini_t4: std_logic;
+ signal dataini_t3: std_logic;
+ signal dataini_t2: std_logic;
+ signal dataini_t1: std_logic;
+ signal dataini_t0: std_logic;
+ signal buf_dataini7: std_logic;
+ signal buf_dataini6: std_logic;
+ signal buf_dataini5: std_logic;
+ signal buf_dataini4: std_logic;
+ signal buf_dataini3: std_logic;
+ signal buf_dataini2: std_logic;
+ signal buf_dataini1: std_logic;
+ signal buf_dataini0: std_logic;
+
+ attribute IO_TYPE : string;
+-- attribute IO_TYPE of Inst3_IB : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB7 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB6 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB5 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB4 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB3 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB2 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB1 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB0 : label is "LVDS";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+-- Inst3_IB: IB
+-- port map (I=>clkin, O=>buf_clkin);
+buf_clkin <= clkin;
+
+ Inst2_IDDRX1F7: IDDRX1F
+ port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7,
+ Q1=>qb7);
+
+ Inst2_IDDRX1F6: IDDRX1F
+ port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6,
+ Q1=>qb6);
+
+ Inst2_IDDRX1F5: IDDRX1F
+ port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5,
+ Q1=>qb5);
+
+ Inst2_IDDRX1F4: IDDRX1F
+ port map (D=>dataini_t4, SCLK=>sclk_t, RST=>reset, Q0=>qa4,
+ Q1=>qb4);
+
+ Inst2_IDDRX1F3: IDDRX1F
+ port map (D=>dataini_t3, SCLK=>sclk_t, RST=>reset, Q0=>qa3,
+ Q1=>qb3);
+
+ Inst2_IDDRX1F2: IDDRX1F
+ port map (D=>dataini_t2, SCLK=>sclk_t, RST=>reset, Q0=>qa2,
+ Q1=>qb2);
+
+ Inst2_IDDRX1F1: IDDRX1F
+ port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1,
+ Q1=>qb1);
+
+ Inst2_IDDRX1F0: IDDRX1F
+ port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0,
+ Q1=>qb0);
+
+ udel_dataini7: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini7, LOADN=>data_loadn(7),
+ MOVE=>data_move(7), DIRECTION=>data_direction(7),
+ Z=>dataini_t7, CFLAG=>data_cflag(7));
+
+ udel_dataini6: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini6, LOADN=>data_loadn(6),
+ MOVE=>data_move(6), DIRECTION=>data_direction(6),
+ Z=>dataini_t6, CFLAG=>data_cflag(6));
+
+ udel_dataini5: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini5, LOADN=>data_loadn(5),
+ MOVE=>data_move(5), DIRECTION=>data_direction(5),
+ Z=>dataini_t5, CFLAG=>data_cflag(5));
+
+ udel_dataini4: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini4, LOADN=>data_loadn(4),
+ MOVE=>data_move(4), DIRECTION=>data_direction(4),
+ Z=>dataini_t4, CFLAG=>data_cflag(4));
+
+ udel_dataini3: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini3, LOADN=>data_loadn(3),
+ MOVE=>data_move(3), DIRECTION=>data_direction(3),
+ Z=>dataini_t3, CFLAG=>data_cflag(3));
+
+ udel_dataini2: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini2, LOADN=>data_loadn(2),
+ MOVE=>data_move(2), DIRECTION=>data_direction(2),
+ Z=>dataini_t2, CFLAG=>data_cflag(2));
+
+ udel_dataini1: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini1, LOADN=>data_loadn(1),
+ MOVE=>data_move(1), DIRECTION=>data_direction(1),
+ Z=>dataini_t1, CFLAG=>data_cflag(1));
+
+ udel_dataini0: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini0, LOADN=>data_loadn(0),
+ MOVE=>data_move(0), DIRECTION=>data_direction(0),
+ Z=>dataini_t0, CFLAG=>data_cflag(0));
+
+ Inst1_IB7: IB
+ port map (I=>datain(7), O=>buf_dataini7);
+
+ Inst1_IB6: IB
+ port map (I=>datain(6), O=>buf_dataini6);
+
+ Inst1_IB5: IB
+ port map (I=>datain(5), O=>buf_dataini5);
+
+ Inst1_IB4: IB
+ port map (I=>datain(4), O=>buf_dataini4);
+
+ Inst1_IB3: IB
+ port map (I=>datain(3), O=>buf_dataini3);
+
+ Inst1_IB2: IB
+ port map (I=>datain(2), O=>buf_dataini2);
+
+ Inst1_IB1: IB
+ port map (I=>datain(1), O=>buf_dataini1);
+
+ Inst1_IB0: IB
+ port map (I=>datain(0), O=>buf_dataini0);
+
+ sclk <= sclk_t;
+ q(15) <= qb7;
+ q(14) <= qa7;
+ q(13) <= qb6;
+ q(12) <= qa6;
+ q(11) <= qb5;
+ q(10) <= qa5;
+ q(9) <= qb4;
+ q(8) <= qa4;
+ q(7) <= qb3;
+ q(6) <= qa3;
+ q(5) <= qb2;
+ q(4) <= qa2;
+ q(3) <= qb1;
+ q(2) <= qa1;
+ q(1) <= qb0;
+ q(0) <= qa0;
+ sclk_t <= buf_clkin;
+end Structure;
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_200_160
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/04/2019
+Time=11:21:53
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=5
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=160
+CLKOP_TOL=0.0
+CLKOP_DIV=4
+CLKOP_ACTUAL_FREQ=160.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=DISABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=1
+CLKOS_ACTUAL_FREQ=
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=4
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=640.000
+PLL_BW=4.655
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1
--- /dev/null
+<!DOCTYPE pll_200_160>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>PLL</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./pll_200_160.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./pll_200_160.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-06-04.11:21:55</lattice:date>
+ <lattice:modified>2019-06-04.11:21:55</lattice:modified>
+ <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">06/04/2019</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">pll_200_160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">11:21:53</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160.000000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_BW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4.655</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>REFERENCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VCO_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">640.000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>pll_200_160</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /d/jspc22/trb/git/trb5sc/mimosis/project/pll_200_160/pll_200_160.fdc
+
+-- Tue Jun 4 11:21:55 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_200_160 is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic);
+end pll_200_160;
+
+architecture Structure of pll_200_160 is
+
+ -- internal signal declarations
+ signal REFCLK: std_logic;
+ signal LOCK: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "12";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLL
+ generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
+ CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
+ CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
+ OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
+ CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
+ CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
+ port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
+ STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
+ ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
+ ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
+ CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
+ REFCLK=>REFCLK, CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=testout
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/05/2019
+Time=14:55:39
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Transmit
+trioddr=0
+io_type=LVDS
+width=8
+freq_in=160
+bandwidth=2560
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Transmit
+trioddr2=0
+io_type2=LVDS
+freq_in2=160
+gear=2:1
+aligned2=Edge-to-Edge
+width2=8
+DataLane=By Lane
+EnECLK=0
+Interface=GDDRX1_TX.SCLK.Aligned
+Delay=Dynamic User Defined
+DelVal=1
+EnInEdge=
+NumEdge=BOTH
+EnDynamic=0
+GenPll=0
+Freq=
+AFreq=
+Reference=0
+IOBUF=
+ReceiverSync=0
+EnDynamicAlign=
+DynamicAlign=
+MIPIFilter=0
+enClkIBuf=0
+ClkIBuf=LVDS
+
+[Command]
+cmd_line= -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane
--- /dev/null
+<!DOCTYPE testout>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>DDR_GENERIC</spirit:name>
+ <spirit:version>6.0</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./testout.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./testout.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-06-05.14:55:41</lattice:date>
+ <lattice:modified>2019-06-05.14:55:41</lattice:modified>
+ <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DDR_GENERIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">6.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">06/05/2019</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">testout</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">14:55:39</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>AFreq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DataLane</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">By Lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DelVal</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Delay</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic User Defined</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamic</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECLK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnInEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Freq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>GenPll</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Interface</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">GDDRX1_TX.SCLK.Aligned</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>MIPIFilter</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>NumEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BOTH</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ReceiverSync</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reference</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>bandwidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2560</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>enClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>gear</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2:1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Transmit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Transmit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>pre-configuration</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>testout</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/testout/testout.fdc
+
+-- Wed Jun 5 14:55:41 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity testout is
+ port (
+ clkout: out std_logic;
+ refclk: in std_logic;
+ reset: in std_logic;
+ data: in std_logic_vector(15 downto 0);
+ data_cflag: out std_logic_vector(7 downto 0);
+ data_direction: in std_logic_vector(7 downto 0);
+ data_loadn: in std_logic_vector(7 downto 0);
+ data_move: in std_logic_vector(7 downto 0);
+ dout: out std_logic_vector(7 downto 0));
+end testout;
+
+architecture Structure of testout is
+
+ -- internal signal declarations
+ signal db7: std_logic;
+ signal da7: std_logic;
+ signal db6: std_logic;
+ signal da6: std_logic;
+ signal db5: std_logic;
+ signal da5: std_logic;
+ signal db4: std_logic;
+ signal da4: std_logic;
+ signal db3: std_logic;
+ signal da3: std_logic;
+ signal db2: std_logic;
+ signal da2: std_logic;
+ signal db1: std_logic;
+ signal da1: std_logic;
+ signal db0: std_logic;
+ signal da0: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal sclk_t: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal buf_clkout: std_logic;
+ signal douto_t7: std_logic;
+ signal buf_douto7: std_logic;
+ signal douto_t6: std_logic;
+ signal buf_douto6: std_logic;
+ signal douto_t5: std_logic;
+ signal buf_douto5: std_logic;
+ signal douto_t4: std_logic;
+ signal buf_douto4: std_logic;
+ signal douto_t3: std_logic;
+ signal buf_douto3: std_logic;
+ signal douto_t2: std_logic;
+ signal buf_douto2: std_logic;
+ signal douto_t1: std_logic;
+ signal buf_douto1: std_logic;
+ signal douto_t0: std_logic;
+ signal buf_douto0: std_logic;
+
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst2_OB : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst4_ODDRX1F7: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da7, D1=>db7,
+ Q=>buf_douto7);
+
+ Inst4_ODDRX1F6: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da6, D1=>db6,
+ Q=>buf_douto6);
+
+ Inst4_ODDRX1F5: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da5, D1=>db5,
+ Q=>buf_douto5);
+
+ Inst4_ODDRX1F4: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da4, D1=>db4,
+ Q=>buf_douto4);
+
+ Inst4_ODDRX1F3: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da3, D1=>db3,
+ Q=>buf_douto3);
+
+ Inst4_ODDRX1F2: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da2, D1=>db2,
+ Q=>buf_douto2);
+
+ Inst4_ODDRX1F1: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da1, D1=>db1,
+ Q=>buf_douto1);
+
+ Inst4_ODDRX1F0: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0,
+ Q=>buf_douto0);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst3_ODDRX1F: ODDRX1F
+ port map (SCLK=>clkos, RST=>reset, D0=>scuba_vhi, D1=>scuba_vlo,
+ Q=>buf_clkout);
+
+ Inst2_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst1_OB7: OB
+ port map (I=>douto_t7, O=>dout(7));
+
+ Inst1_OB6: OB
+ port map (I=>douto_t6, O=>dout(6));
+
+ Inst1_OB5: OB
+ port map (I=>douto_t5, O=>dout(5));
+
+ Inst1_OB4: OB
+ port map (I=>douto_t4, O=>dout(4));
+
+ Inst1_OB3: OB
+ port map (I=>douto_t3, O=>dout(3));
+
+ Inst1_OB2: OB
+ port map (I=>douto_t2, O=>dout(2));
+
+ Inst1_OB1: OB
+ port map (I=>douto_t1, O=>dout(1));
+
+ Inst1_OB0: OB
+ port map (I=>douto_t0, O=>dout(0));
+
+ udel_douto7: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto7, LOADN=>data_loadn(7),
+ MOVE=>data_move(7), DIRECTION=>data_direction(7),
+ Z=>douto_t7, CFLAG=>data_cflag(7));
+
+ udel_douto6: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto6, LOADN=>data_loadn(6),
+ MOVE=>data_move(6), DIRECTION=>data_direction(6),
+ Z=>douto_t6, CFLAG=>data_cflag(6));
+
+ udel_douto5: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto5, LOADN=>data_loadn(5),
+ MOVE=>data_move(5), DIRECTION=>data_direction(5),
+ Z=>douto_t5, CFLAG=>data_cflag(5));
+
+ udel_douto4: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto4, LOADN=>data_loadn(4),
+ MOVE=>data_move(4), DIRECTION=>data_direction(4),
+ Z=>douto_t4, CFLAG=>data_cflag(4));
+
+ udel_douto3: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto3, LOADN=>data_loadn(3),
+ MOVE=>data_move(3), DIRECTION=>data_direction(3),
+ Z=>douto_t3, CFLAG=>data_cflag(3));
+
+ udel_douto2: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto2, LOADN=>data_loadn(2),
+ MOVE=>data_move(2), DIRECTION=>data_direction(2),
+ Z=>douto_t2, CFLAG=>data_cflag(2));
+
+ udel_douto1: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto1, LOADN=>data_loadn(1),
+ MOVE=>data_move(1), DIRECTION=>data_direction(1),
+ Z=>douto_t1, CFLAG=>data_cflag(1));
+
+ udel_douto0: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto0, LOADN=>data_loadn(0),
+ MOVE=>data_move(0), DIRECTION=>data_direction(0),
+ Z=>douto_t0, CFLAG=>data_cflag(0));
+
+ db7 <= data(15);
+ da7 <= data(14);
+ db6 <= data(13);
+ da6 <= data(12);
+ db5 <= data(11);
+ da5 <= data(10);
+ db4 <= data(9);
+ da4 <= data(8);
+ db3 <= data(7);
+ da3 <= data(6);
+ db2 <= data(5);
+ da2 <= data(4);
+ db1 <= data(3);
+ da1 <= data(2);
+ db0 <= data(1);
+ da0 <= data(0);
+ sclk_t <= clkop;
+ clkos <= refclk;
+ clkop <= refclk;
+end Structure;
--- /dev/null
+-w
+#-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 10
+-t 2
+-c 2
+-e 2
+-i 10
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
--- /dev/null
+BLOCK NET "bustdc_tx*";
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_mimosis"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_mimosis.edf"
+set_option log_file "workdir/trb5sc_project.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+
+#channel 1, SFP
+add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
+add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+##########################################
+
+add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "./cores/mimosis_inp.vhd"
+add_file -vhdl -lib work "./cores/testout.vhd"
+add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd"
+
+add_file -vhdl -lib work "./trb5sc_mimosis.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb5sc_mimosis is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+ \r
+ TRIG_IN_BACKPL : in std_logic; --Reference Time\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3\r
+ BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1\r
+ \r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+ \r
+ --AddOn\r
+-- FE_GPIO : inout std_logic_vector(11 downto 0);\r
+-- FE_CLK : out std_logic_vector( 2 downto 1);\r
+-- FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ INP : inout std_logic_vector(63 downto 0);\r
+ MOSI : in std_logic;\r
+ \r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+ \r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1);\r
+ HDR_IO : inout std_logic_vector(15 downto 0)\r
+ );\r
+\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+\r
+end entity;\r
+\r
+architecture arch of trb5sc_mimosis is\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160 : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+ \r
+ \r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true; \r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+ \r
+\r
+ signal readout_rx : READOUT_RX;\r
+ signal readout_tx : readout_tx_array_t(0 to 0);\r
+\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0); \r
+ \r
+ \r
+ \r
+ signal clk_rx : std_logic;\r
+ signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0');\r
+ signal data_i : std_logic_vector(15 downto 0);\r
+ signal inp_i : std_logic_vector(7 downto 0);\r
+ \r
+ signal out_data : std_logic_vector(15 downto 0);\r
+ signal out_i : std_logic_vector( 7 downto 0); \r
+ \r
+ type state_t is (START, LISTEN, STEP, CALC, SET1, SET2, ENDWAIT);\r
+ type state_arrt is array (0 to 7) of state_t;\r
+ \r
+ type unsigned_arr is array(0 to 7) of unsigned(6 downto 0);\r
+ signal sample_good, sample_bad : unsigned_arr := (others => (others => '0'));\r
+ signal first_good, first_bad : unsigned_arr := (others => (others => '1'));\r
+ signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0'));\r
+ \r
+ \r
+begin\r
+\r
+\r
+trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => med2int(0).stat_op(13),\r
+ SEND_RESET_IN => med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+\r
+\r
+\r
+THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160\r
+ );\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- TrbNet Uplink\r
+---------------------------------------------------------------------------\r
+\r
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ generic map(\r
+ SERDES_NUM => 0,\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
+ CLK_INTERNAL_FULL => clk_full_osc,\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Sync operation\r
+ RX_DLM => open,\r
+ RX_DLM_WORD => open,\r
+ TX_DLM => open,\r
+ TX_DLM_WORD => open,\r
+\r
+ --SFP Connection\r
+ SD_PRSNT_N_IN => sfp_prsnt_i,\r
+ SD_LOS_IN => sfp_los_i,\r
+ SD_TXDIS_OUT => sfp_txdis_i,\r
+ --Control Interface\r
+ BUS_RX => bussci_rx,\r
+ BUS_TX => bussci_tx,\r
+ -- Status and control port\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => open\r
+ );\r
+\r
+ gen_sfp_con : if SERDES_NUM = 1 generate\r
+ sfp_los_i <= SFP_LOS;\r
+ sfp_prsnt_i <= SFP_MOD_0; \r
+ SFP_TX_DIS <= sfp_txdis_i;\r
+ end generate; \r
+ gen_bpl_con : if SERDES_NUM = 0 generate\r
+ sfp_los_i <= BACK_GPIO(1);\r
+ sfp_prsnt_i <= BACK_GPIO(1); \r
+ BACK_GPIO(0) <= sfp_txdis_i;\r
+ end generate; \r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- Endpoint\r
+---------------------------------------------------------------------------\r
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
+ generic map (\r
+ ADDRESS_MASK => x"FFFF",\r
+ BROADCAST_BITMASK => x"FF",\r
+ REGIO_INIT_ENDPOINT_ID => x"0001",\r
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
+ TIMING_TRIGGER_RAW => c_YES,\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER => 1,\r
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ DATA_BUFFER_WIDTH => 32,\r
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ TRG_RELEASE_AFTER_DATA => c_YES,\r
+ HEADER_BUFFER_DEPTH => 9,\r
+ HEADER_BUFFER_FULL_THRESH => 2**9-16\r
+ )\r
+\r
+ port map(\r
+ -- Misc\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_EN => '1',\r
+\r
+ -- Media direction port\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
+\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+\r
+ --Slow Control Port\r
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
+ BUS_RX => ctrlbus_rx,\r
+ BUS_TX => ctrlbus_tx,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+\r
+ ONEWIRE_INOUT => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ --Timing registers\r
+ TIMERS_OUT => timer\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+\r
+\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 4,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+\r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => bustdc_rx,\r
+ BUS_TX(0) => bustools_tx,\r
+ BUS_TX(1) => bussci_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => bustdc_tx,\r
+\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15),\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ HEADER_IO => open, --HDR_IO(9 downto 0),\r
+ ADDITIONAL_REG => add_reg,\r
+ --LCD\r
+ LCD_DATA_IN => (others => '0'),\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor \r
+ MONITOR_INPUTS => (others => '0'),\r
+ TRIG_GEN_INPUTS => (others => '0'),\r
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+ \r
+ \r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"F0";\r
+ LED_RJ_GREEN <= "00";\r
+ LED_RJ_RED <= "11";\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK;\r
+ \r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i;\r
+ FLASH_NCS <= flash_ncs_i; \r
+\r
+ ---------------------------------------------------------------------------\r
+-- Output stage\r
+--------------------------------------------------------------------------- \r
+ THE_OUT : entity work.testout\r
+ port map(\r
+ clkout => open,\r
+ refclk => clk_160,\r
+ reset => reset_i,\r
+ data => out_data,\r
+ data_cflag => open,\r
+ data_direction => (others => '0'),\r
+ data_loadn => (others => '1'),\r
+ data_move => (others => '0'),\r
+ dout => out_i\r
+ );\r
+ \r
+ PROC_OUT : process \r
+ variable cnt : integer range 0 to 7;\r
+ begin\r
+ wait until rising_edge(clk_160);\r
+ cnt := cnt + 1;\r
+ case cnt is \r
+ when 0 => out_data <= x"ffff";\r
+ when 1 => out_data <= x"ffff";\r
+ when 2 => out_data <= x"ffff";\r
+ when 3 => out_data <= x"0000";\r
+ when 4 => out_data <= x"5555";\r
+ when 5 => out_data <= x"5555";\r
+ when 6 => out_data <= x"5555";\r
+ when 7 => out_data <= x"5555";\r
+ end case;\r
+ end process; \r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ \r
+ \r
+ THE_IN : entity work.mimosis_inp\r
+ port map (\r
+ clkin=>clk_160, \r
+ reset=>reset_i, \r
+ sclk=>clk_rx, \r
+ data_cflag(7 downto 0)=>s_cflag, \r
+ data_direction(7 downto 0)=>(others => '0'), \r
+ data_loadn(7 downto 0)=>s_loadn, \r
+ data_move(7 downto 0)=>s_move, \r
+ datain(7 downto 0)=>inp_i, \r
+ q(15 downto 0)=>data_i\r
+ );\r
+\r
+ HDR_IO <= data_i;\r
+\r
+ inp_i <= INP(14) & INP(12) & INP(10) & INP(8) & INP(6) & INP(4) & INP(2) & INP(0);\r
+ INP(30) <= out_i(7);\r
+ INP(28) <= out_i(6);\r
+ INP(26) <= out_i(5);\r
+ INP(24) <= out_i(4);\r
+ INP(22) <= out_i(3);\r
+ INP(20) <= out_i(2);\r
+ INP(18) <= out_i(1);\r
+ INP(16) <= out_i(0);\r
+\r
+-- s_move <= add_reg(7 downto 0);\r
+\r
+\r
+gen_finders : for i in 0 to 7 generate \r
+ signal timer : unsigned(14 downto 0);\r
+ signal state : state_t;\r
+ signal count : unsigned(11 downto 0);\r
+ signal pos : unsigned(6 downto 0);\r
+ signal lastsample : std_logic;\r
+ signal train : unsigned(3 downto 0);\r
+ signal last : std_logic_vector(1 downto 0);\r
+ \r
+begin \r
+ PROC_FIND : process begin\r
+ wait until rising_edge(clk_160);\r
+ s_loadn(i) <= not add_reg(i+16);\r
+\r
+ case state is\r
+ when START =>\r
+ timer <= 0;\r
+ count <= 0;\r
+ s_move(i) <= '0';\r
+ state <= LISTEN;\r
+ \r
+ when LISTEN =>\r
+ if timer(timer'left) = '1' then\r
+ state <= STEP;\r
+ if count >= 2047 and count <= 2049 then\r
+ sample_good(i) <= sample_good(i) + 1;\r
+ lastsample <= '1';\r
+ if first_good(i) > pos then\r
+ first_good(i) <= pos;\r
+ end if;\r
+ if last_bad(i) < pos and lastsample = '0' then\r
+ last_bad(i) <= pos;\r
+ end if;\r
+ \r
+ else\r
+ lastsample <= '0';\r
+ sample_bad(i) <= sample_bad(i) + 1; \r
+ if first_bad(i) > pos then\r
+ first_bad(i) <= pos;\r
+ end if;\r
+ if last_good(i) < pos and lastsample = '1' then\r
+ last_good(i) <= pos;\r
+ end if; \r
+ end if;\r
+ else \r
+ timer <= timer + 1;\r
+ end if;\r
+ \r
+ last <= data_i(i*2+1 downto i*2);\r
+ \r
+ if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and \r
+ data_i(i*2+1 downto i*2) = last then\r
+ train <= train + 1;\r
+ else\r
+ train <= x"0";\r
+ end if;\r
+ \r
+ if train = x"3" then\r
+ count <= count + 1;\r
+ end if;\r
+ \r
+ \r
+ when STEP =>\r
+ if s_cflag(i) = '0' then\r
+ s_move(i) <= '1';\r
+ pos <= pos + 1;\r
+ state <= START;\r
+ else\r
+ state <= CALC;\r
+ s_loadn(i) <= '1'; \r
+ end if; \r
+ \r
+ when CALC =>\r
+ pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";\r
+ posi(i) <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";\r
+ state <= SET1;\r
+ \r
+ when SET1 =>\r
+ state <= SET2;\r
+ s_move(i) <= '1';\r
+ \r
+ when SET2 =>\r
+ s_move(i) <= '0';\r
+ if pos = 0 then\r
+ state <= ENDWAIT;\r
+ else \r
+ state <= SET1;\r
+ pos <= pos - 1;\r
+ end if; \r
+ \r
+ when ENDWAIT =>\r
+\r
+ state <= ENDWAIT;\r
+ \r
+ end case;\r
+ \r
+ if reset_i = '1' or add_reg(0) = '1' then\r
+ state <= START;\r
+ pos <= 0;\r
+ sample_good(i) <= 0;\r
+ sample_bad(i) <= 0;\r
+ last_good(i) <= 0;\r
+ last_bad(i) <= 0;\r
+ first_good(i) <= (others => '1'); \r
+ first_bad(i) <= (others => '1'); \r
+ end if;\r
+ end process;\r
+end generate; \r
+\r
+PROC_REGS : process \r
+ variable addr : integer range 0 to 7;\r
+begin\r
+ wait until rising_edge(clk_sys);\r
+ bustdc_tx.ack <= '0';\r
+ bustdc_tx.unknown <= '0';\r
+ bustdc_tx.nack <= '0';\r
+ bustdc_tx.data <= (others => '0');\r
+ addr := to_integer(unsigned(bustdc_rx.addr(2 downto 0)));\r
+ \r
+ if bustdc_rx.read = '1' then\r
+ bustdc_tx.ack <= '1';\r
+ if bustdc_rx.addr(15 downto 4) = x"000" then\r
+ if bustdc_rx.addr(3) = '0' then\r
+ bustdc_tx.data(6 downto 0) <= std_logic_vector(sample_good(addr));\r
+ bustdc_tx.data(14 downto 8) <= std_logic_vector(sample_bad(addr));\r
+ bustdc_tx.data(16) <= s_cflag(addr);\r
+ bustdc_tx.data(30 downto 24)<= std_logic_vector(posi(addr));\r
+ else\r
+ bustdc_tx.data(6 downto 0) <= std_logic_vector(first_good(addr));\r
+ bustdc_tx.data(14 downto 8) <= std_logic_vector(last_good(addr));\r
+ bustdc_tx.data(22 downto 16) <= std_logic_vector(first_bad(addr));\r
+ bustdc_tx.data(30 downto 24) <= std_logic_vector(last_bad(addr));\r
+ end if;\r
+ else\r
+ bustdc_tx.ack <= '0';\r
+ bustdc_tx.unknown <= '1';\r
+ \r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+readout_tx(0).data_finished <= '1';\r
+readout_tx(0).data_write <= '0';\r
+readout_tx(0).busy_release <= '1'; \r
+ \r
+ \r
+end architecture;\r
+\r
+\r
+\r
jspc29 / trb5sc.git / commitdiff