-../tdc_releases/tdc_v1.5
\ No newline at end of file
+../tdc_releases/tdc_v1.5.1
\ No newline at end of file
#add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
-add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
#add_file -vhdl -lib "work" "tdc_release/FIFO_32x32_OutReg.vhd"
add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
generic map (
CHANNEL_NUMBER => 5, -- Number of TDC channels
CONTROL_REG_NR => 5,
- TDC_VERSION => "001" & x"51") -- TDC version number
+ TDC_VERSION => "0001" & x"51") -- TDC version number
port map (
RESET => reset_i,
CLK_TDC => CLK_PCLK_RIGHT, -- Clock used for the time measurement