Compiles with v1.5.1, but totally untested any further

diff --git a/cts/tdc_release b/cts/tdc_release
index 660503024f2a9a147b987afcc6738cad83f6b500..1ed173f13926013794c11b7418fd2b694324268f 120000 (symlink)
--- a/cts/tdc_release
+++ b/cts/tdc_release
@@ -1 +1 @@
-../tdc_releases/tdc_v1.5
\ No newline at end of file
+../tdc_releases/tdc_v1.5.1
\ No newline at end of file

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 598df2ca2085ed135158a4b748e78321d31fd616..e8ab136360c77c97fa4cffc855a65ce614221613 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -258,8 +258,8 @@ add_file -vhdl -lib work "source/cts.vhd"
 #add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
 add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
 add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
-add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
 add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
 add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
 #add_file -vhdl -lib "work" "tdc_release/FIFO_32x32_OutReg.vhd"
 add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 99eeb5e8c87ee5db1d32e3ebb7b3379ef36058e7..f9b1eb0513e42814d3cf5e639bceaf8abb554c25 100755 (executable)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -1283,7 +1283,7 @@ gen_TDC : if INCLUDE_TDC = c_YES generate
     generic map (
       CHANNEL_NUMBER => 5,             -- Number of TDC channels
       CONTROL_REG_NR => 5,
-      TDC_VERSION    => "001" & x"51")  -- TDC version number
+      TDC_VERSION    => "0001" & x"51")  -- TDC version number
     port map (
       RESET                 => reset_i,
       CLK_TDC               => CLK_PCLK_RIGHT,  -- Clock used for the time measurement