Reset : in std_logic;
Q : out std_logic_vector(35 downto 0);
Empty : out std_logic;
- Full : out std_logic);
- end component FIFO_36x64_OutReg;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic);
+ end component;
-
+
component FIFO_36x32_OutReg is
port (
Data : in std_logic_vector(35 downto 0);
Reset : in std_logic;
Q : out std_logic_vector(35 downto 0);
Empty : out std_logic;
- Full : out std_logic);
- end component FIFO_36x16_OutReg;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic);
+ end component;
-
+
component FIFO_DC_36x128_OutReg is
port (
Data : in std_logic_vector(35 downto 0);