CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible
--SFP
- SFP_RX_P : in std_logic_vector(6 downto 1);
- SFP_RX_N : in std_logic_vector(6 downto 1);
- SFP_TX_P : out std_logic_vector(6 downto 1);
- SFP_TX_N : out std_logic_vector(6 downto 1);
+ SFP_RX_P : in std_logic_vector(5 downto 2);
+ SFP_RX_N : in std_logic_vector(5 downto 2);
+ SFP_TX_P : out std_logic_vector(5 downto 2);
+ SFP_TX_N : out std_logic_vector(5 downto 2);
SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken
SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP
SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal
--Bit 0-3 connected to LED by default, two on each side
--Big AddOn connector
- ADDON_RESET : out std_logic; --reset signal to AddOn
+-- ADDON_RESET : out std_logic; --reset signal to AddOn
ADDON_TO_TRB_CLK : in std_logic; --Clock from AddOn, connected to PCLK input
- TRB_TO_ADDON_CLK : out std_logic; --Clock sent to AddOn
+-- TRB_TO_ADDON_CLK : out std_logic; --Clock sent to AddOn
ADO_LV : inout std_logic_vector(61 downto 0);
ADO_TTL : inout std_logic_vector(46 downto 0);
FS_PE : inout std_logic_vector(17 downto 0);
attribute syn_useioff of LED_TRIGGER_GREEN : signal is false;
attribute syn_useioff of LED_TRIGGER_RED : signal is false;
attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of FPGA1_TTL : signal is false;
- attribute syn_useioff of FPGA2_TTL : signal is false;
- attribute syn_useioff of FPGA3_TTL : signal is false;
- attribute syn_useioff of FPGA4_TTL : signal is false;
+-- attribute syn_useioff of FPGA1_TTL : signal is false;
+-- attribute syn_useioff of FPGA2_TTL : signal is false;
+-- attribute syn_useioff of FPGA3_TTL : signal is false;
+-- attribute syn_useioff of FPGA4_TTL : signal is false;
attribute syn_useioff of SFP_TXDIS : signal is false;
attribute syn_useioff of PROGRAMN : signal is false;
signal med_packet_num_in : std_logic_vector (5*3-1 downto 0);
signal med_dataready_in : std_logic_vector (5*1-1 downto 0);
signal med_read_in : std_logic_vector (5*1-1 downto 0);
+ signal med2int : med2int_array_t(0 to 10);
+ signal int2med : int2med_array_t(0 to 10);
--Hub
- signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
- signal my_address : std_logic_vector (16-1 downto 0);
- signal regio_addr_out : std_logic_vector (16-1 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (32-1 downto 0);
- signal regio_data_in : std_logic_vector (32-1 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
+ signal common_stat_reg : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+ signal my_address : std_logic_vector (16-1 downto 0);
-
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
-
- signal sci2_ack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
-
signal cts_number : std_logic_vector(15 downto 0);
signal cts_code : std_logic_vector(7 downto 0);
signal cts_information : std_logic_vector(7 downto 0);
signal fee_status_bits : std_logic_vector(31 downto 0);
signal fee_busy : std_logic;
-signal stage_stat_regs : std_logic_vector (31 downto 0);
-signal stage_ctrl_regs : std_logic_vector (31 downto 0);
-
-signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0);
-signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0);
-signal mb_stat_reg_read : std_logic;
-signal mb_stat_reg_write : std_logic;
-signal mb_stat_reg_ack : std_logic;
-signal ip_cfg_mem_clk : std_logic;
-signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
-signal ctrl_reg_addr : std_logic_vector(15 downto 0);
-
-
-
-signal gbe_unknown : std_logic;
-
--- signal select_tc : std_logic_vector(31 downto 0) := (8 => USE_EXTERNAL_CLOCK_std, others => '0');
--- signal select_tc_data_in : std_logic_vector(31 downto 0);
--- signal select_tc_write : std_logic;
--- signal select_tc_read : std_logic;
--- signal select_tc_ack : std_logic;
-
-signal trig_outputs : std_logic_vector(4 downto 0);
-signal trig_inputs : std_logic_vector(15 downto 0);
-signal trig_din : std_logic_vector(31 downto 0);
-signal trig_dout : std_logic_vector(31 downto 0);
-signal trig_write : std_logic := '0';
-signal trig_read : std_logic := '0';
-signal trig_ack : std_logic := '0';
-signal trig_nack : std_logic := '0';
-signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
-
-signal monitor_inputs_i : std_logic_vector(19 downto 0);
-signal stat_din : std_logic_vector(31 downto 0);
-signal stat_dout : std_logic_vector(31 downto 0);
-signal stat_write : std_logic := '0';
-signal stat_read : std_logic := '0';
-signal stat_ack : std_logic := '0';
-signal stat_nack : std_logic := '0';
-signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
-
-signal busuart_rx, bustc_rx : CTRLBUS_RX;
-signal busuart_tx, bustc_tx : CTRLBUS_TX;
-signal uart_tx : std_logic_vector(4 downto 0);
-signal uart_rx : std_logic_vector(4 downto 0);
+
+
+ signal ctrlbus_rx, bussci1_rx, bussci2_rx, bustools_rx,
+ bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci1_tx, bussci2_tx, bustools_tx,
+ bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
+
+ signal sed_error_i : std_logic;
+ signal bus_master_active : std_logic;
+ signal lcd_out : std_logic_vector(4 downto 0);
+ signal feature_outputs_i : std_logic_vector(15 downto 0);
+
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+ signal uart_tx, uart_rx : std_logic;
+
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
signal debug : std_logic_vector(63 downto 0);
signal reset_counter : std_logic_vector(11 downto 0);
signal link_ok : std_logic;
+ signal trig_gen_out_i : std_logic_vector(3 downto 0);
+ signal monitor_inputs_i : std_logic_vector(19 downto 0);
+ signal trig_inputs : std_logic_vector(15 downto 0);
+
signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
signal gsc_init_read, gsc_reply_read : std_logic;
signal gsc_init_dataready, gsc_reply_dataready : std_logic;
signal mc_unique_id : std_logic_vector(63 downto 0);
signal trb_reset_in : std_logic;
signal reset_via_gbe : std_logic;
-signal timer_ticks : std_logic_vector(1 downto 0);
+
signal reset_via_gbe_delayed : std_logic_vector(2 downto 0);
signal reset_i_temp : std_logic;
- signal busgbeip_rx, busgbereg_rx : CTRLBUS_RX;
- signal busgbeip_tx, busgbereg_tx : CTRLBUS_TX;
-
signal do_reboot, reboot_from_gbe : std_logic;
-
+signal debug_rx, debug_tx : std_logic;
begin
wait until rising_edge(clk_sys_i);
if reset_i = '1' then
reset_via_gbe_delayed <= "000";
- elsif timer_ticks(0) = '1' then
+ elsif timer.tick_us = '1' then
reset_via_gbe_delayed <= reset_via_gbe_delayed(1 downto 0) & reset_via_gbe;
end if;
end process;
CLK_RX_HALF_OUT => open,
CLK_RX_FULL_OUT => open,
--SFP Connection
--- SD_RXD_P_IN => SFP_RX_P(1),
--- SD_RXD_N_IN => SFP_RX_N(1),
--- SD_TXD_P_OUT => SFP_TX_P(1),
--- SD_TXD_N_OUT => SFP_TX_N(1),
--- SD_REFCLK_P_IN => open,
--- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => SFP_MOD0(1),
SD_LOS_IN => SFP_LOS(1),
SD_TXDIS_OUT => SFP_TXDIS(1),
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
+ SCI_DATA_IN => bussci1_rx.data(7 downto 0),
+ SCI_DATA_OUT => bussci1_tx.data(7 downto 0),
+ SCI_ADDR => bussci1_rx.addr(8 downto 0),
+ SCI_READ => bussci1_rx.read,
+ SCI_WRITE => bussci1_rx.write,
+ SCI_ACK => bussci1_tx.ack,
-- Status and control port
STAT_OP => med_stat_op(79 downto 64),
CTRL_OP => med_ctrl_op(79 downto 64),
gen_no_uplink : if USE_125_MHZ = c_YES generate
SFP_TXDIS(7 downto 1) <= (others => '1');
med_stat_op(66 downto 64) <= (others => '1');
- sci1_ack <= '1';
+ bussci1_tx.ack <= '1';
end generate;
SD_TXDIS_OUT(2) => FPGA3_COMM(0),
SD_TXDIS_OUT(3) => FPGA4_COMM(0),
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
+ SCI_DATA_IN => bussci2_rx.data(7 downto 0),
+ SCI_DATA_OUT => bussci2_tx.data(7 downto 0),
+ SCI_ADDR => bussci2_rx.addr(8 downto 0),
+ SCI_READ => bussci2_rx.read,
+ SCI_WRITE => bussci2_rx.write,
+ SCI_ACK => bussci2_tx.ack,
-- Status and control port
STAT_OP => med_stat_op(63 downto 0),
CTRL_OP => med_ctrl_op(63 downto 0),
CTRL_DEBUG => (others => '0')
);
+ gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
+ med2int(i).data <= med_data_in(i*16+15 downto i*16);
+ med2int(i).packet_num <= med_packet_num_in(i*3+2 downto i*3) ;
+ med2int(i).dataready <= med_dataready_in(i);
+ med2int(i).tx_read <= med_read_in(i);
+ med2int(i).stat_op <= med_stat_op(i*16+15 downto i*16);
+
+ med_data_out(i*16+15 downto i*16) <= int2med(i).data;
+ med_packet_num_out(i*3+2 downto i*3) <= int2med(i).packet_num;
+ med_dataready_out(i) <= int2med(i).dataready;
+ med_ctrl_op(i*16+15 downto i*16) <= int2med(i).ctrl_op;
+ end generate;
----------------------------------------------------------------------------
--- The TrbNet Hub
----------------------------------------------------------------------------
-gen_normal_hub : if USE_ETHERNET = c_NO generate
-
- THE_HUB : trb_net16_hub_base
- generic map (
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => IS_UPLINK,
- MII_IS_DOWNLINK => IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
- INT_NUMBER => INTERNAL_NUM,
- INT_CHANNELS => INTERNAL_CHANNELS,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- HUB_USED_CHANNELS => USED_CHANNELS,
- INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
- INIT_ADDRESS => INIT_ADDRESS,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+
+gen_ethernet_hub : if USE_ETHERNET = c_YES generate
+
+ THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
+ generic map(
+ HUB_USED_CHANNELS => (1,1,0,1),
+ INIT_ADDRESS => INIT_ADDRESS,
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => IS_UPLINK,
+ MII_IS_DOWNLINK => IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
+ USE_ONEWIRE => c_YES,
+ HARDWARE_VERSION => HARDWARE_INFO,
+ INCLUDED_FEATURES => INCLUDED_FEATURES,
+ INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
)
- port map (
- CLK => clk_sys_i,
- RESET => reset_i,
- CLK_EN => '1',
+ port map(
+ CLK => clk_sys_i,
+ RESET => reset_i,
+ CLK_EN => '1',
--Media interfacces
- MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(5*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(5*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(5*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(5*1-1 downto 0) => med_read_out,
- MED_STAT_OP(5*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op,
-
- COMMON_STAT_REGS => common_stat_regs,
- COMMON_CTRL_REGS => common_ctrl_regs,
- MY_ADDRESS_OUT => my_address,
- TIMER_TICKS_OUT => timer_ticks,
-
- --REGIO INTERFACE
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
-
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
+ MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1),
+ MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1),
- reset_via_gbe <= '0';
- gbe_unknown <= '1';
-end generate;
-
-gen_ethernet_hub : if USE_ETHERNET = c_YES generate
-
+ --Event information coming from CTSCTS_READOUT_TYPE_OUT
+ CTS_NUMBER_OUT => cts_number,
+ CTS_CODE_OUT => cts_code,
+ CTS_INFORMATION_OUT => cts_information,
+ CTS_READOUT_TYPE_OUT => cts_readout_type,
+ CTS_START_READOUT_OUT => cts_start_readout,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN => cts_data,
+ CTS_DATAREADY_IN => cts_dataready,
+ CTS_READOUT_FINISHED_IN => cts_readout_finished,
+ CTS_READ_OUT => cts_read,
+ CTS_LENGTH_IN => cts_length,
+ CTS_STATUS_BITS_IN => cts_status_bits,
+ -- Data from Frontends
+ FEE_DATA_OUT => fee_data,
+ FEE_DATAREADY_OUT => fee_dataready,
+ FEE_READ_IN => fee_read,
+ FEE_STATUS_BITS_OUT => fee_status_bits,
+ FEE_BUSY_OUT => fee_busy,
+ MY_ADDRESS_IN => my_address,
+ COMMON_STAT_REGS => common_stat_reg, --open,
+ COMMON_CTRL_REGS => common_ctrl_reg, --open,
+ ONEWIRE => TEMPSENS,
+ MY_ADDRESS_OUT => my_address,
+ UNIQUE_ID_OUT => mc_unique_id,
+ EXTERNAL_SEND_RESET => reset_via_gbe,
+
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ TIMER => timer,
+
+ --Gbe Sctrl Input
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+
+ --status and control ports
+ HUB_STAT_CHANNEL => open,
+ HUB_STAT_GEN => open,
+ MPLEX_CTRL => (others => '0'),
+ MPLEX_STAT => open,
+ STAT_REGS => open,
+ STAT_CTRL_REGS => open,
+
+ --Fixed status and control ports
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+-- external_reset_i <= reset_via_gbe; -- or med2int(INTERFACE_NUM-1).stat_op(15);
- THE_HUB: trb_net16_hub_streaming_port_sctrl
- generic map(
- HUB_USED_CHANNELS => USED_CHANNELS,
- INIT_ADDRESS => INIT_ADDRESS,
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => IS_UPLINK,
- MII_IS_DOWNLINK => IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
- USE_ONEWIRE => c_YES,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- INIT_ENDPOINT_ID => x"0005",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(5*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(5*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(5*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(5*1-1 downto 0) => med_read_out,
- MED_STAT_OP(5*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op,
-
- --Event information coming from CTSCTS_READOUT_TYPE_OUT
- CTS_NUMBER_OUT => cts_number,
- CTS_CODE_OUT => cts_code,
- CTS_INFORMATION_OUT => cts_information,
- CTS_READOUT_TYPE_OUT => cts_readout_type,
- CTS_START_READOUT_OUT => cts_start_readout,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN => cts_data,
- CTS_DATAREADY_IN => cts_dataready,
- CTS_READOUT_FINISHED_IN => cts_readout_finished,
- CTS_READ_OUT => cts_read,
- CTS_LENGTH_IN => cts_length,
- CTS_STATUS_BITS_IN => cts_status_bits,
- -- Data from Frontends
- FEE_DATA_OUT => fee_data,
- FEE_DATAREADY_OUT => fee_dataready,
- FEE_READ_IN => fee_read,
- FEE_STATUS_BITS_OUT => fee_status_bits,
- FEE_BUSY_OUT => fee_busy,
- MY_ADDRESS_IN => my_address,
- COMMON_STAT_REGS => common_stat_regs, --open,
- COMMON_CTRL_REGS => common_ctrl_regs, --open,
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_IN => open,
- MY_ADDRESS_OUT => my_address,
- TIMER_TICKS_OUT => timer_ticks,
- UNIQUE_ID_OUT => mc_unique_id,
- EXTERNAL_SEND_RESET => reset_via_gbe,
-
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
-
- --Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
-
- --status and control ports
- HUB_STAT_CHANNEL => open,
- HUB_STAT_GEN => open,
- MPLEX_CTRL => (others => '0'),
- MPLEX_STAT => open,
- STAT_REGS => open,
- STAT_CTRL_REGS => open,
-
- --Fixed status and control ports
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
---------------------------------------------------------------------
-- The GbE machine for blasting out data from TRBnet
DEBUG_OUT => open
);
- gbe_unknown <= '0';
end generate;
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 9,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", 3 => x"b000", 4 => x"b200", 5 => x"d300", 6 => x"cf00", 7 => x"cf80", 8 => x"d600", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 8, 3 => 9, 4 => 9, 5 => 0, 6 => 7, 7 => 7, 8 => 2, others => 0)
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
-
- -- third one - IP config memory
- BUS_ADDR_OUT(1*16+7 downto 1*16) => busgbeip_rx.addr(7 downto 0),
- BUS_DATA_OUT(1*32+31 downto 1*32) => busgbeip_rx.data,
- BUS_READ_ENABLE_OUT(1) => busgbeip_rx.read,
- BUS_WRITE_ENABLE_OUT(1) => busgbeip_rx.write,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => busgbeip_tx.data,
- BUS_DATAREADY_IN(1) => busgbeip_tx.ack,
- BUS_WRITE_ACK_IN(1) => busgbeip_tx.ack,
- BUS_NO_MORE_DATA_IN(1) => busgbeip_tx.nack,
- BUS_UNKNOWN_ADDR_IN(1) => busgbeip_tx.unknown,
-
- -- gbe setup
- BUS_ADDR_OUT(2*16+7 downto 2*16) => busgbereg_rx.addr(7 downto 0),
- BUS_DATA_OUT(2*32+31 downto 2*32) => busgbereg_rx.data,
- BUS_READ_ENABLE_OUT(2) => busgbereg_rx.read,
- BUS_WRITE_ENABLE_OUT(2) => busgbereg_rx.write,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => busgbereg_tx.data,
- BUS_DATAREADY_IN(2) => busgbereg_tx.ack,
- BUS_WRITE_ACK_IN(2) => busgbereg_tx.ack,
- BUS_NO_MORE_DATA_IN(2) => busgbereg_tx.nack,
- BUS_UNKNOWN_ADDR_IN(2) => busgbereg_tx.unknown,
-
- --SCI first Media Interface
- BUS_READ_ENABLE_OUT(3) => sci1_read,
- BUS_WRITE_ENABLE_OUT(3) => sci1_write,
- BUS_DATA_OUT(3*32+7 downto 3*32) => sci1_data_in,
- BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
- BUS_ADDR_OUT(3*16+8 downto 3*16) => sci1_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+7 downto 3*32) => sci1_data_out,
- BUS_DATAREADY_IN(3) => sci1_ack,
- BUS_WRITE_ACK_IN(3) => sci1_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
- --SCI second Media Interface
- BUS_READ_ENABLE_OUT(4) => sci2_read,
- BUS_WRITE_ENABLE_OUT(4) => sci2_write,
- BUS_DATA_OUT(4*32+7 downto 4*32) => sci2_data_in,
- BUS_DATA_OUT(4*32+31 downto 4*32+8) => open,
- BUS_ADDR_OUT(4*16+8 downto 4*16) => sci2_addr,
- BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
- BUS_TIMEOUT_OUT(4) => open,
- BUS_DATA_IN(4*32+7 downto 4*32) => sci2_data_out,
- BUS_DATAREADY_IN(4) => sci2_ack,
- BUS_WRITE_ACK_IN(4) => sci2_ack,
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_UNKNOWN_ADDR_IN(4) => '0',
-
- -- Trigger and Clock Manager Settings
- BUS_ADDR_OUT(6*16-1 downto 5*16) => bustc_rx.addr,
- BUS_DATA_OUT(6*32-1 downto 5*32) => bustc_rx.data,
- BUS_READ_ENABLE_OUT(5) => bustc_rx.read,
- BUS_WRITE_ENABLE_OUT(5) => bustc_rx.write,
- BUS_TIMEOUT_OUT(5) => open,
- BUS_DATA_IN(6*32-1 downto 5*32) => bustc_tx.data,
- BUS_DATAREADY_IN(5) => bustc_tx.ack,
- BUS_WRITE_ACK_IN(5) => bustc_tx.ack,
- BUS_NO_MORE_DATA_IN(5) => bustc_tx.nack,
- BUS_UNKNOWN_ADDR_IN(5) => bustc_tx.unknown,
-
- --Trigger logic registers
- BUS_READ_ENABLE_OUT(6) => trig_read,
- BUS_WRITE_ENABLE_OUT(6) => trig_write,
- BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din,
- BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr,
- BUS_TIMEOUT_OUT(6) => open,
- BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout,
- BUS_DATAREADY_IN(6) => trig_ack,
- BUS_WRITE_ACK_IN(6) => trig_ack,
- BUS_NO_MORE_DATA_IN(6) => '0',
- BUS_UNKNOWN_ADDR_IN(6) => trig_nack,
-
- --Input statistics
- BUS_READ_ENABLE_OUT(7) => stat_read,
- BUS_WRITE_ENABLE_OUT(7) => stat_write,
- BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din,
- BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr,
- BUS_TIMEOUT_OUT(7) => open,
- BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout,
- BUS_DATAREADY_IN(7) => stat_ack,
- BUS_WRITE_ACK_IN(7) => stat_ack,
- BUS_NO_MORE_DATA_IN(7) => '0',
- BUS_UNKNOWN_ADDR_IN(7) => stat_nack,
-
- --Uart
- BUS_READ_ENABLE_OUT(8) => busuart_rx.read,
- BUS_WRITE_ENABLE_OUT(8) => busuart_rx.write,
- BUS_DATA_OUT(8*32+31 downto 8*32) => busuart_rx.data,
- BUS_ADDR_OUT(8*16+15 downto 8*16) => busuart_rx.addr,
- BUS_TIMEOUT_OUT(8) => open,
- BUS_DATA_IN(8*32+31 downto 8*32) => busuart_tx.data,
- BUS_DATAREADY_IN(8) => busuart_tx.ack,
- BUS_WRITE_ACK_IN(8) => busuart_tx.ack,
- BUS_NO_MORE_DATA_IN(8) => busuart_tx.nack,
- BUS_UNKNOWN_ADDR_IN(8) => busuart_tx.unknown,
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-
-THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
- port map(
- CLK_IN => clk_sys_i,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => do_reboot, --common_ctrl_regs(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-do_reboot <= common_ctrl_regs(15) or reboot_from_gbe;
---------------------------------------------------------------------------
--- Trigger logic
+-- Bus Handler
---------------------------------------------------------------------------
-gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
- THE_TRIG_LOGIC : input_to_trigger_logic
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- INPUTS => PHYSICAL_INPUTS,
- OUTPUTS => 5
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"8100", 5 => x"8300", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 8, 5 => 8, others => 0),
+ PORT_MASK_ENABLE => 1
)
port map(
- CLK => clk_sys_i,
+ CLK => clk_sys_i,
+ RESET => reset_i,
+
+ REGIO_RX => handlerbus_rx,
+ REGIO_TX => ctrlbus_tx,
- INPUT => trig_inputs,
- OUTPUT => trig_outputs,
-
- DATA_IN => trig_din,
- DATA_OUT => trig_dout,
- WRITE_IN => trig_write,
- READ_IN => trig_read,
- ACK_OUT => trig_ack,
- NACK_OUT => trig_nack,
- ADDR_IN => trig_addr
- );
-
- TRIGGER_OUT2 <= trig_outputs(0);
- trig_inputs <= FPGA4_COMM(10 downto 7) & FPGA3_COMM(10 downto 7) & FPGA2_COMM(10 downto 7) & FPGA1_COMM(10 downto 7);
-end generate;
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustc_rx, --Clock switch
+ BUS_RX(2) => bussci1_rx, --SCI Serdes
+ BUS_RX(3) => bussci2_rx,
+ BUS_RX(4) => busgbeip_rx,
+ BUS_RX(5) => busgbereg_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustc_tx,
+ BUS_TX(2) => bussci1_tx,
+ BUS_TX(3) => bussci2_tx,
+ BUS_TX(4) => busgbeip_tx,
+ BUS_TX(5) => busgbereg_tx,
+ STAT_DEBUG => open
+ );
+
+ handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
-gen_no_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
- TRIGGER_OUT2 <= TRIGGER_RIGHT;
-end generate;
---------------------------------------------------------------------------
--- Input Statistics
+-- Control Tools
---------------------------------------------------------------------------
-gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
-
- THE_STAT_LOGIC : entity work.input_statistics
- generic map(
- INPUTS => 20,
- SINGLE_FIFO_ONLY => c_YES
- )
+ THE_TOOLS : entity work.trb3_tools
port map(
- CLK => clk_sys_i,
-
- INPUT => monitor_inputs_i(19 downto 0),
-
- DATA_IN => stat_din,
- DATA_OUT => stat_dout,
- WRITE_IN => stat_write,
- READ_IN => stat_read,
- ACK_OUT => stat_ack,
- NACK_OUT => stat_nack,
- ADDR_IN => stat_addr
+ CLK => clk_sys_i,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_DOUT,
+ FLASH_OUT => FLASH_DIN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ SPI_CLR_OUT => open,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ UART_RX_IN => uart_rx,
+ UART_TX_OUT => uart_tx,
+ DEBUG_RX_IN => debug_rx,
+ DEBUG_TX_OUT => debug_tx,
+
+ --Trigger & Monitor
+ MONITOR_INPUTS(19 downto 0) => monitor_inputs_i(19 downto 0),
+ TRIG_GEN_INPUTS => trig_inputs,
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ LCD_OUT => lcd_out,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
);
-end generate;
+
+ trig_inputs <= FPGA4_COMM(10 downto 7) & FPGA3_COMM(10 downto 7) & FPGA2_COMM(10 downto 7) & FPGA1_COMM(10 downto 7);
monitor_inputs_i(15 downto 0) <= trig_inputs;
-monitor_inputs_i(19 downto 16) <= trig_outputs(3 downto 0);
-
-gen_uart : if INCLUDE_UART = 1 generate
- THE_UART : entity work.uart
- generic map(
- OUTPUTS => 5
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
- UART_RX => uart_rx,
- UART_TX => uart_tx,
- BUS_RX => busuart_rx,
- BUS_TX => busuart_tx
- );
+monitor_inputs_i(19 downto 16) <= trig_gen_out_i(3 downto 0);
- uart_rx(0) <= CLKRJ(0);
- uart_rx(1) <= FPGA1_TTL(0);
- uart_rx(2) <= FPGA2_TTL(0);
- uart_rx(3) <= FPGA3_TTL(0);
- uart_rx(4) <= FPGA4_TTL(0);
+
+-- feature_outputs_i(0) <= uart_rx;
+-- feature_outputs_i(1) <= uart_tx;
+-- feature_outputs_i(2) <= spi_cs(1);
+-- feature_outputs_i(3) <= spi_mosi(1);
+-- feature_outputs_i(4) <= spi_clk(1);
+-- -- spi_miso(1) <= TEST_LINE(5);
+-- feature_outputs_i(7) <= lcd_out(4); --lcd_cs
+-- feature_outputs_i(8) <= lcd_out(0); --lcd_rst
+-- feature_outputs_i(9) <= lcd_out(3); --lcd_dc
+-- feature_outputs_i(10) <= lcd_out(2); --lcd_mosi
+-- feature_outputs_i(11) <= lcd_out(1); --lcd_sck
+-- --12 is LCD MISO, but not used
+-- feature_outputs_i(14) <= debug_rx;
+-- feature_outputs_i(15) <= debug_tx;
+
- CLKRJ(2) <= uart_tx(0);
- FPGA1_TTL(1) <= uart_tx(1);
- FPGA2_TTL(1) <= uart_tx(2);
- FPGA3_TTL(1) <= uart_tx(3);
- FPGA4_TTL(1) <= uart_tx(4);
+gen_no_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
+ TRIGGER_OUT2 <= TRIGGER_RIGHT;
+end generate;
+gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ TRIGGER_OUT2 <= trig_gen_out_i(0);
end generate;
-
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
---------------------------------------------------------------------------
-- Big AddOn Connector
---------------------------------------------------------------------------
- ADDON_RESET <= '1';
- TRB_TO_ADDON_CLK <= '0';
+-- ADDON_RESET <= '1';
+-- TRB_TO_ADDON_CLK <= '0';
ADO_LV <= (others => 'Z');
ADO_TTL <= (others => 'Z');
FS_PE <= (others => 'Z');
LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
- LED_GREEN <= debug(0);
- LED_ORANGE <= debug(1);
- LED_RED <= debug(2);
+-- LED_GREEN <= debug(0);
+-- LED_ORANGE <= debug(1);
+-- LED_RED <= debug(2);
LED_YELLOW <= link_ok; --debug(3);
-- Test Connector
---------------------------------------------------------------------------
- TEST_LINE(7 downto 0) <= med_data_in(7 downto 0);
- TEST_LINE(8) <= med_dataready_in(0);
- TEST_LINE(9) <= med_dataready_out(0);
+-- TEST_LINE(7 downto 0) <= med_data_in(7 downto 0);
+-- TEST_LINE(8) <= med_dataready_in(0);
+-- TEST_LINE(9) <= med_dataready_out(0);
- TEST_LINE(31 downto 10) <= (others => '0');
+ TEST_LINE(31 downto 0) <= (others => '0');
-- CLK_TEST_OUT <= clk_med_i & '0' & clk_sys_i;
- CLKRJ(1) <= 'Z';
- CLKRJ(3) <= 'Z';
+ CLKRJ(3 downto 0) <= "ZZZZ";
jspc29 / trb3.git / commitdiff