end if;
end process;
- fifo_reset <= reset or quad_rst;
+ fifo_reset <= reset or quad_rst or not rx_allow;
--RX Control (25)
---------------------
else
rx_data_reg(7 downto 0) <= buf_rx_data(7 downto 0);
if( rx_allow = '1' ) then
- if( (rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then
+ if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then
rx_fifo_write_en <= '1';
else
rx_fifo_write_en <= '0';
STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0);
STAT_DEBUG(39 downto 32) <= rx_data_reg(7 downto 0);
- STAT_DEBUG(63 downto 40) <= (others => '0');
+ STAT_DEBUG(40) <= rx_fifo_write_en;
+ STAT_DEBUG(63 downto 41) <= (others => '0');
else
rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8);
if( rx_allow(i) = '1' ) then
- if( (rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
+ if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
rx_fifo_write_en(i) <= '1';
else
rx_fifo_write_en(i) <= '0';
STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
STAT_DEBUG(i*64+39 downto i*64+32) <= rx_data_reg(i*8+7 downto i*8);
- STAT_DEBUG(i*64+63 downto i*64+40) <= (others => '0');
+ STAT_DEBUG(i*64+40) <= rx_fifo_write_en(i);
+ STAT_DEBUG(i*64+63 downto i*64+41) <= (others => '0');
end generate;