IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14";
-IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+#LOCATE COMP "SUPPL" SITE "C14";
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
#################################################################
. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
-exec ./compile_munich21.pl
+./compile_munich21.pl
+
+grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup"
+
+echo "Script DONE!"
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bus_async_trans is
+ generic (
+ BUS_WIDTH : integer range 2 to 32 := 8;
+ NUM_FF : integer range 2 to 4 := 2
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SIGNAL_A_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(BUS_WIDTH - 1 downto 0)
+ );
+
+end entity;
+
+architecture Behavioral of bus_async_trans is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "BUS_ASYNC_TRANS";
+
+ type buffer_t is array(0 to NUM_FF - 1) of
+ std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal signal_ff : buffer_t;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Clock CLK_IN Domain
+ -----------------------------------------------------------------------------
+
+ PROC_SYNC_SIGNAL: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ signal_ff(NUM_FF - 1) <= SIGNAL_A_IN;
+ if( RESET_IN = '1' ) then
+ for i in NUM_FF - 2 downto 0 loop
+ signal_ff(i) <= (others => '0');
+ end loop;
+ else
+ for i in NUM_FF - 2 downto 0 loop
+ signal_ff(i) <= signal_ff(i + 1);
+ end loop;
+ end if;
+ end if;
+ end process PROC_SYNC_SIGNAL;
+
+ -- Output Signals
+ SIGNAL_OUT <= signal_ff(0);
+
+end Behavioral;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+
+entity fifo_44_data_delay_my is
+ port (
+ Data : in std_logic_vector(43 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmEmptyThresh : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(43 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture Behavioral of fifo_44_data_delay_my is
+ constant BUS_WIDTH : integer := 8;
+ constant DATA_WIDTH : integer := 44;
+ constant FULL_LEVEL : unsigned(BUS_WIDTH - 1 downto 0) := (others => '1');
+
+ signal write_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal write_enable : std_logic;
+ signal write_ctr : unsigned(BUS_WIDTH - 1 downto 0);
+ signal write_ctr_x : unsigned(BUS_WIDTH - 1 downto 0);
+ signal full_o : std_logic;
+
+ signal read_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal read_enable : std_logic;
+ signal read_enable_last : std_logic;
+ signal read_ctr : unsigned(BUS_WIDTH - 1 downto 0);
+ signal read_ctr_x : unsigned(BUS_WIDTH - 1 downto 0);
+ signal read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal empty_o : std_logic;
+ signal empty_o_x : std_logic;
+ signal almost_empty_o : std_logic;
+ signal almost_empty_o_x : std_logic;
+
+ signal Q_o : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal Q_o_x : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+
+ -----------------------------------------------------------------------------
+
+ DEBUG_OUT(0) <= Clock;
+ DEBUG_OUT(1) <= WrEn;
+ DEBUG_OUT(2) <= write_enable;
+ DEBUG_OUT(3) <= RdEn;
+ DEBUG_OUT(4) <= read_enable;
+ DEBUG_OUT(5) <= read_enable_last;
+ DEBUG_OUT(6) <= full_o;
+ DEBUG_OUT(7) <= empty_o;
+ DEBUG_OUT(15 downto 8) <= std_logic_vector(write_ctr - read_ctr);
+
+ -----------------------------------------------------------------------------
+
+ ram_fifo_delay_256x44_1: ram_fifo_delay_256x44
+ port map (
+ WrAddress => write_address,
+ RdAddress => read_address,
+ Data => write_data,
+ WE => not Reset,
+ RdClock => Clock,
+ RdClockEn => read_enable,
+ Reset => Reset,
+ WrClock => Clock,
+ WrClockEn => write_enable,
+ Q => read_data
+ );
+
+ -----------------------------------------------------------------------------
+ -- RAM Handler
+ -----------------------------------------------------------------------------
+ PROC_MEM_WRITE_TRANSFER: process(Clock)
+ begin
+ if( rising_edge(Clock) ) then
+ if( Reset = '1' ) then
+ write_ctr <= (others => '0');
+ read_ctr <= (others => '0');
+ read_enable_last <= '0';
+ Q_o <= (others => '0');
+ else
+ write_ctr <= write_ctr_x;
+ read_ctr <= read_ctr_x;
+ read_enable_last <= read_enable;
+ Q_o <= Q_o_x;
+ end if;
+ end if;
+ end process PROC_MEM_WRITE_TRANSFER;
+
+ PROC_MEM_WRITE: process(WrEn,
+ RdEn,
+ Data,
+ write_ctr,
+ read_ctr,
+ read_data,
+ read_enable_last,
+ full_o,
+ empty_o,
+ AmEmptyThresh
+ )
+ variable delta_ctr : unsigned(BUS_WIDTH - 1 downto 0);
+ variable full : std_logic;
+ variable empty : std_logic;
+ variable almost_empty : std_logic;
+
+ begin
+
+ -- Fill Level
+ delta_ctr := write_ctr - read_ctr;
+
+ -- Empty
+ if (delta_ctr = 0) then
+ empty := '1';
+ else
+ empty := '0';
+ end if;
+
+ -- Almost Empty
+ if (delta_ctr < unsigned(AmEmptyThresh)) then
+ almost_empty := '1';
+ else
+ almost_empty := '0';
+ end if;
+
+ -- Full
+ if (delta_ctr = FULL_LEVEL) then
+ full := '1';
+ else
+ full := '0';
+ end if;
+
+ full_o <= full;
+ empty_o <= empty;
+ almost_empty_o <= almost_empty;
+
+ -- FIFO Writes
+ if (WrEn = '1' and full = '0') then
+ write_address <= write_ctr;
+ write_data <= Data;
+ write_enable <= '1';
+ write_ctr_x <= write_ctr + 1;
+ else
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
+ write_ctr_x <= write_ctr;
+ end if;
+
+ -- FIFO Reads
+ if (RdEn = '1' and empty = '0') then
+ read_address <= read_ctr;
+ read_enable <= '1';
+ read_ctr_x <= read_ctr + 1;
+ else
+ read_address <= (others => '0');
+ read_enable <= '0';
+ read_ctr_x <= read_ctr;
+ end if;
+
+ if (read_enable_last = '1') then
+ Q_o_x <= read_data;
+ else
+ Q_o_x <= (others => '0');
+ end if;
+
+ end process PROC_MEM_WRITE;
+
+ -----------------------------------------------------------------------------
+ -- Output Signals
+ -----------------------------------------------------------------------------
+
+ Q <= Q_o;
+ Empty <= empty_o;
+ Full <= full_o;
+ AlmostEmpty <= almost_empty_o;
+
+end Behavioral;
end if;
end process PROC_RESET_HANDLER;
- pulse_to_level_3: pulse_to_level
+ pulse_to_level_SAMPLING_CLK_RESET: pulse_to_level
generic map (
NUM_CYCLES => 10
)
LEVEL_OUT => sampling_clk_reset
);
- pulse_to_level_4: pulse_to_level
+ pulse_to_level_ADC_RESET: pulse_to_level
generic map (
NUM_CYCLES => 5
)
LEVEL_OUT => adc_reset
);
- pulse_to_level_5: pulse_to_level
+ pulse_to_level_DATA_HANDLER_RESET: pulse_to_level
generic map (
NUM_CYCLES => 5
)
signal trigger_rate_inc : std_logic;
signal frame_rate_inc : std_logic;
+ signal pileup_rate_inc : std_logic;
+ signal overflow_rate_inc : std_logic;
-- Rate Calculation
signal nx_trigger_ctr_t : unsigned(27 downto 0);
signal nx_frame_ctr_t : unsigned(27 downto 0);
+ signal nx_pileup_ctr_t : unsigned(27 downto 0);
+ signal nx_overflow_ctr_t : unsigned(27 downto 0);
signal nx_rate_timer : unsigned(27 downto 0);
-- ADC Averages
signal clear_counters : std_logic;
signal nx_hit_rate : unsigned(27 downto 0);
signal nx_frame_rate : unsigned(27 downto 0);
-
+ signal nx_pileup_rate : unsigned(27 downto 0);
+ signal nx_overflow_rate : unsigned(27 downto 0);
signal invalid_adc : std_logic;
begin
nx_nomore_data_o <= '0';
trigger_rate_inc <= '0';
frame_rate_inc <= '0';
+ pileup_rate_inc <= '0';
+ overflow_rate_inc <= '0';
invalid_frame_ctr <= (others => '0');
overflow_ctr <= (others => '0');
data_valid_o <= '0';
trigger_rate_inc <= '0';
frame_rate_inc <= '0';
+ pileup_rate_inc <= '0';
+ overflow_rate_inc <= '0';
invalid_adc <= '0';
if (new_timestamp = '1') then
---- Check Overflow
if ((status_bits(0) = '1') and (clear_counters = '0')) then
overflow_ctr <= overflow_ctr + 1;
+ overflow_rate_inc <= '1';
end if;
---- Check Parity
-- Check PileUp
if ((status_bits(1) = '1') and (clear_counters = '0')) then
pileup_ctr <= pileup_ctr + 1;
- end if;
+ pileup_rate_inc <= '1';
+ end if;
-- Take Timestamp
timestamp_o <= nx_timestamp;
if (frame_rate_inc = '1') then
nx_frame_ctr_t <= nx_frame_ctr_t + 1;
end if;
+ if (pileup_rate_inc = '1') then
+ nx_pileup_ctr_t <= nx_trigger_ctr_t + 1;
+ end if;
+ if (overflow_rate_inc = '1') then
+ nx_overflow_ctr_t <= nx_frame_ctr_t + 1;
+ end if;
nx_rate_timer <= nx_rate_timer + 1;
else
nx_hit_rate <= nx_trigger_ctr_t;
nx_frame_rate <= nx_frame_ctr_t;
+ nx_pileup_rate <= nx_pileup_ctr_t;
+ nx_overflow_rate <= nx_overflow_ctr_t;
+
if (trigger_rate_inc = '0') then
nx_trigger_ctr_t <= (others => '0');
else
nx_trigger_ctr_t <= x"000_0001";
end if;
+
if (frame_rate_inc = '0') then
nx_frame_ctr_t <= (others => '0');
else
nx_frame_ctr_t <= x"000_0001";
end if;
+
+ if (pileup_rate_inc = '0') then
+ nx_pileup_ctr_t <= (others => '0');
+ else
+ nx_pileup_ctr_t <= x"000_0001";
+ end if;
+
+ if (overflow_rate_inc = '0') then
+ nx_overflow_ctr_t <= (others => '0');
+ else
+ nx_overflow_ctr_t <= x"000_0001";
+ end if;
+
nx_rate_timer <= (others => '0');
end if;
end if;
std_logic_vector(nx_frame_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0006" =>
slv_data_out_o(11 downto 0) <= adc_data_last;
slv_data_out_o(31 downto 12) <= (others => '0');
end entity;
architecture Behavioral of nx_fpga_timestamp is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "NX_FPGA_TIMESTAMP is";
+
signal timestamp_ctr : unsigned(11 downto 0);
signal timestamp_current_o : unsigned(11 downto 0);
signal timestamp_hold_o : std_logic_vector(11 downto 0);
trigger <= TRIGGER_IN;
- signal_async_to_pulse_2: signal_async_to_pulse
+ signal_async_to_pulse_TIMESTAMP_SYNC_IN: signal_async_to_pulse
port map (
CLK_IN => NX_MAIN_CLK_IN,
RESET_IN => RESET_IN,
architecture Behavioral of nx_setup is
+--attribute HGROUP : string;
+--attribute HGROUP of Behavioral : architecture is "SLAVE_BUS_NX_SETUP";
+
-- I2C Command Multiplexer
signal i2c_lock_0 : std_logic;
signal i2c_lock_1 : std_logic;
signal int_ack_o : std_logic;
-- TRBNet Slave Bus
+ signal slv_read : std_logic;
+ signal slv_write : std_logic;
+ signal slv_addr : std_logic_vector(15 downto 0);
+ signal slv_data : std_logic_vector(31 downto 0);
+
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal nxyter_testchannels : std_logic_vector(2 downto 0);
signal i2c_update_memory_r : std_logic;
+ -- Buffer
+ signal slv_data_out_o_b : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o_b : std_logic;
+ signal slv_unknown_addr_o_b : std_logic;
+ signal slv_ack_o_b : std_logic;
+
begin
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= I2C_COMMAND_BUSY_IN;
- DEBUG_OUT(2) <= i2c_command_busy_o;
- DEBUG_OUT(3) <= i2c_error;
- DEBUG_OUT(4) <= i2c_command_done;
- DEBUG_OUT(5) <= next_token_dac_r or
- next_token_dac_w;
- DEBUG_OUT(6) <= i2c_update_memory;
- DEBUG_OUT(7) <= i2c_lock_0_clear;
- DEBUG_OUT(8) <= i2c_lock_1_clear;
- DEBUG_OUT(9) <= i2c_lock_2_clear;
- DEBUG_OUT(10) <= i2c_lock_4_clear;
- DEBUG_OUT(11) <= i2c_online_o;
- DEBUG_OUT(12) <= i2c_lock_0;
- DEBUG_OUT(13) <= i2c_lock_1;
- DEBUG_OUT(14) <= i2c_lock_2;
- DEBUG_OUT(15) <= i2c_lock_4;
-
+-- DEBUG_OUT(1) <= I2C_COMMAND_BUSY_IN;
+-- DEBUG_OUT(2) <= i2c_command_busy_o;
+-- DEBUG_OUT(3) <= i2c_error;
+-- DEBUG_OUT(4) <= i2c_command_done;
+-- DEBUG_OUT(5) <= next_token_dac_r or
+-- next_token_dac_w;
+-- DEBUG_OUT(6) <= i2c_update_memory;
+-- DEBUG_OUT(7) <= i2c_lock_0_clear;
+-- DEBUG_OUT(8) <= i2c_lock_1_clear;
+-- DEBUG_OUT(9) <= i2c_lock_2_clear;
+-- DEBUG_OUT(10) <= i2c_lock_4_clear;
+-- DEBUG_OUT(11) <= i2c_online_o;
+-- DEBUG_OUT(12) <= i2c_lock_0;
+-- DEBUG_OUT(13) <= i2c_lock_1;
+-- DEBUG_OUT(14) <= i2c_lock_2;
+-- DEBUG_OUT(15) <= i2c_lock_4;
+
+ DEBUG_OUT(2 downto 1) <= (others => '0');
+ DEBUG_OUT(3) <= SLV_WRITE_IN;
+ DEBUG_OUT(4) <= SLV_READ_IN;
+ DEBUG_OUT(5) <= slv_no_more_data_o;
+ DEBUG_OUT(6) <= slv_unknown_addr_o;
+ DEBUG_OUT(7) <= slv_ack_o;
+ DEBUG_OUT(15 downto 8) <= slv_data_out_o(7 downto 0);
+
-----------------------------------------------------------------------------
PROC_I2C_RAM: process(CLK_IN)
variable index : integer := 0;
begin
if( rising_edge(CLK_IN) ) then
+ -- Buffer input
+ slv_read <= SLV_READ_IN;
+ slv_write <= SLV_WRITE_IN;
+ slv_addr <= SLV_ADDR_IN;
+ slv_data <= SLV_DATA_IN;
+
if( RESET_IN = '1' ) then
slv_data_out_o <= (others => '0');
slv_no_more_data_o <= '0';
nxyter_testpulse <= (others => '0');
nxyter_testchannels <= (others => '0');
else
- slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
nxyter_testpulse <= (others => '0');
nxyter_testchannels <= (others => '0');
- if (SLV_WRITE_IN = '1') then
- if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then
- index := to_integer(unsigned(SLV_ADDR_IN(5 downto 0)));
+ if (slv_write = '1') then
+ if (slv_addr >= x"0000" and slv_addr <= x"002d") then
+ index := to_integer(unsigned(slv_addr(5 downto 0)));
if (i2c_disable_memory = '0') then
ram_index_0 <= index;
- ram_data_0 <= SLV_DATA_IN(7 downto 0);
+ ram_data_0 <= slv_data(7 downto 0);
ram_write_0 <= '1';
end if;
slv_ack_o <= '1';
- elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then
+ elsif (slv_addr >= x"0100" and slv_addr <= x"0180") then
-- Write value to ram
- index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0)));
+ index := to_integer(unsigned(slv_addr(7 downto 0)));
if (index = 0) then
index := 128;
else
if (i2c_disable_memory = '0') then
dac_ram_index_0 <= index;
- dac_ram_data_0 <= SLV_DATA_IN(5 downto 0);
+ dac_ram_data_0 <= slv_data(5 downto 0);
dac_ram_write_0 <= '1';
end if;
slv_ack_o <= '1';
else
- case SLV_ADDR_IN is
+ case slv_addr is
when x"0050" =>
-- Nxyter Clock
if (i2c_disable_memory = '0') then
- nxyter_clock(0) <= SLV_DATA_IN(0);
+ nxyter_clock(0) <= slv_data(0);
nxyter_clock(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0051" =>
-- Nxyter Polarity
if (i2c_disable_memory = '0') then
- nxyter_polarity(0) <= SLV_DATA_IN(0);
+ nxyter_polarity(0) <= slv_data(0);
nxyter_polarity(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0053" =>
-- Nxyter Testpulse
if (i2c_disable_memory = '0') then
- nxyter_testpulse(0) <= SLV_DATA_IN(0);
+ nxyter_testpulse(0) <= slv_data(0);
nxyter_testpulse(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0054" =>
-- Nxyter Testtrigger
if (i2c_disable_memory = '0') then
- nxyter_testtrigger(0) <= SLV_DATA_IN(0);
+ nxyter_testtrigger(0) <= slv_data(0);
nxyter_testtrigger(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0055" =>
-- Nxyter Testtrigger
if (i2c_disable_memory = '0') then
- nxyter_testchannels(1 downto 0) <= SLV_DATA_IN(1 downto 0);
+ nxyter_testchannels(1 downto 0) <= slv_data(1 downto 0);
nxyter_testchannels(2) <= '1';
end if;
slv_ack_o <= '1';
end case;
end if;
- elsif (SLV_READ_IN = '1') then
- if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then
- index := to_integer(unsigned(SLV_ADDR_IN(5 downto 0)));
+ elsif (slv_read = '1') then
+ if (slv_addr >= x"0000" and slv_addr <= x"002d") then
+ index := to_integer(unsigned(slv_addr(5 downto 0)));
if (i2c_disable_memory = '0') then
slv_data_out_o(7 downto 0) <= i2c_ram(index);
slv_data_out_o(28 downto 8) <= (others => '0');
end if;
slv_ack_o <= '1';
- elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then
- index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0)));
+ elsif (slv_addr >= x"0100" and slv_addr <= x"0180") then
+ index := to_integer(unsigned(slv_addr(7 downto 0)));
if (index = 0) then
index := 128;
else
end if;
slv_ack_o <= '1';
- elsif (SLV_ADDR_IN >= x"0080" and SLV_ADDR_IN <= x"0083") then
- index := to_integer(unsigned(SLV_ADDR_IN(1 downto 0)));
+ elsif (slv_addr >= x"0080" and slv_addr <= x"0083") then
+ index := to_integer(unsigned(slv_addr(1 downto 0)));
if (i2c_disable_memory = '0') then
slv_data_out_o(12 downto 0) <= adc_ram(index);
slv_data_out_o(31 downto 13) <= (others => '0');
slv_ack_o <= '1';
else
- case SLV_ADDR_IN is
+ case slv_addr is
when x"0050" =>
-- Nxyter Clock
if (i2c_disable_memory = '0') then
-- Internal Read
INT_ACK_OUT <= int_ack_o;
INT_DATA_OUT <= int_data_o;
-
+
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
end entity;
architecture Behavioral of nx_timer is
-
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "NX_TIMER";
+
-- Timer
signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0);
end entity;
architecture Behavioral of nx_trigger_generator is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_GENERATOR";
- signal trigger : std_logic;
+ signal trigger_i : std_logic;
signal start_cycle : std_logic;
signal trigger_cycle_ctr : unsigned(7 downto 0);
signal wait_timer_init : unsigned(15 downto 0);
signal wait_timer_done : std_logic;
+ signal wait_timer_done_i : std_logic;
signal trigger_o : std_logic;
signal ts_reset_o : std_logic;
- signal testpulse_p : std_logic;
signal testpulse_o : std_logic;
signal extern_trigger : std_logic;
signal testpulse : std_logic;
signal testpulse_rate_t : unsigned(27 downto 0);
signal rate_timer : unsigned(27 downto 0);
+
+ -- Reg Sync
+ signal testpulse_length : unsigned(11 downto 0);
-- TRBNet Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal test_debug : std_logic;
begin
-
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= TRIGGER_IN;
- DEBUG_OUT(2) <= trigger;
+ DEBUG_OUT(1) <= '0';--TRIGGER_IN;
+ DEBUG_OUT(2) <= '0';--trigger_i;
DEBUG_OUT(3) <= start_cycle;
- DEBUG_OUT(4) <= wait_timer_done;
+ DEBUG_OUT(4) <= '0';--wait_timer_done_i;
DEBUG_OUT(5) <= ts_reset_o;
DEBUG_OUT(6) <= testpulse_o;
DEBUG_OUT(7) <= testpulse;
-----------------------------------------------------------------------------
-- Generate Trigger
-----------------------------------------------------------------------------
-
- level_to_pulse_1: level_to_pulse
- port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
- LEVEL_IN => TRIGGER_IN,
- PULSE_OUT => trigger
- );
-
+
PROC_TESTPULSE_OUT: process(NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
+ -- Relax timing by adding registers
+ trigger_i <= TRIGGER_IN;
+ wait_timer_done_i <= wait_timer_done;
+
if (RESET_IN = '1') then
trigger_o <= '0';
- testpulse_p <= '0';
testpulse_o <= '0';
ts_reset_o <= '0';
wait_timer_init <= (others => '0');
STATE <= S_IDLE;
else
trigger_o <= '0';
- testpulse_p <= '0';
testpulse_o <= '0';
ts_reset_o <= '0';
wait_timer_init <= (others => '0');
case STATE is
when S_IDLE =>
- if (trigger = '1') then
+ if (trigger_i = '1') then
extern_trigger <= '1';
- testpulse_p <= '1';
testpulse_o <= '1';
- if (reg_testpulse_length > 1) then
- wait_timer_init(11 downto 0) <= reg_testpulse_length - 1;
+ if (testpulse_length > 1) then
+ wait_timer_init(11 downto 0) <= testpulse_length - 2;
wait_timer_init(15 downto 12) <= (others => '0');
STATE <= S_WAIT_TESTPULSE_END;
else
end if;
when S_WAIT_TESTPULSE_END =>
- if (wait_timer_done = '0') then
+ if (wait_timer_done_i = '0') then
testpulse_o <= '1';
STATE <= S_WAIT_TESTPULSE_END;
else
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
RESET_A_IN => RESET_IN,
- PULSE_A_IN => testpulse_p,
+ PULSE_A_IN => testpulse_o,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
PULSE_B_OUT => testpulse
end if;
end if;
end process PROC_CAL_RATES;
-
+
+ -----------------------------------------------------------------------------
+ -- Register Transfer
+ -----------------------------------------------------------------------------
+
+ bus_async_trans_TESTPULSE_LENGTH : bus_async_trans
+ generic map (
+ BUS_WIDTH => 12,
+ NUM_FF => 2
+ )
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ RESET_IN => RESET_IN,
+ SIGNAL_A_IN => std_logic_vector(reg_testpulse_length),
+ unsigned(SIGNAL_OUT) => testpulse_length
+ );
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
end entity;
architecture Behavioral of nx_trigger_handler is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_HANDLER";
-- Timing Trigger Handler
constant NUM_FF : integer := 10;
signal timing_trigger_ff : std_logic_vector(NUM_FF - 1 downto 0);
signal timing_trigger_l : std_logic;
signal timing_trigger : std_logic;
+ signal timing_trigger_i : std_logic;
signal timing_trigger_set : std_logic;
signal timestamp_trigger : std_logic;
signal timestamp_trigger_o : std_logic;
signal TS_STATE : TS_STATES;
signal ts_wait_timer_reset : std_logic;
+ signal ts_wait_timer_reset_i : std_logic;
signal ts_wait_timer_init : unsigned(7 downto 0);
signal ts_wait_timer_done : std_logic;
-
+ signal ts_wait_timer_done_i : std_logic;
-- Trigger Handler
signal valid_trigger_o : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
signal send_testpulse_l : std_logic;
signal send_testpulse : std_logic;
-
+
type STATES is (S_IDLE,
S_CTS_TRIGGER,
S_WAIT_TRG_DATA_VALID,
signal wait_timer_init : unsigned(11 downto 0);
signal wait_timer_done : std_logic;
+ signal testpulse_delay : unsigned(11 downto 0);
+ signal testpulse_enable : std_logic;
+
-- Rate Calculation
signal accepted_trigger_rate_t : unsigned(27 downto 0);
signal rate_timer : unsigned(27 downto 0);
PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
+ timing_trigger_i <= timing_trigger;
+ ts_wait_timer_done_i <= ts_wait_timer_done;
+ ts_wait_timer_reset <= ts_wait_timer_reset_i;
if (RESET_IN = '1' or fast_clear = '1') then
invalid_timing_trigger_n <= '1';
ts_wait_timer_init <= (others => '0');
- ts_wait_timer_reset <= '1';
+ ts_wait_timer_reset_i <= '1';
send_testpulse <= '0';
timestamp_trigger <= '0';
TS_STATE <= TS_IDLE;
else
invalid_timing_trigger_n <= '0';
ts_wait_timer_init <= (others => '0');
- ts_wait_timer_reset <= '0';
+ ts_wait_timer_reset_i <= '0';
send_testpulse <= '0';
timestamp_trigger <= '0';
-
+
case TS_STATE is
when TS_IDLE =>
- if (timing_trigger = '1') then
+ if (timing_trigger_i = '1') then
if (trigger_busy = '0') then
- if (reg_testpulse_enable = '1') then
+ if (testpulse_enable = '1') then
send_testpulse <= '1';
end if;
timestamp_trigger <= '1';
if (trigger_busy = '1') then
TS_STATE <= TS_WAIT_TRIGGER_END;
else
- if (ts_wait_timer_done = '0') then
- ts_wait_timer_reset <= '1';
+ if (ts_wait_timer_done_i = '0') then
+ ts_wait_timer_reset_i <= '1';
TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
else
- ts_wait_timer_reset <= '1';
+ ts_wait_timer_reset_i <= '1';
TS_STATE <= TS_INVALID_TRIGGER;
end if;
end if;
end if;
end process PROC_TIMING_TRIGGER_COUNTER;
- signal_async_trans_1: signal_async_trans
+ signal_async_trans_TRIGGER_BUSY: signal_async_trans
port map (
CLK_IN => NX_MAIN_CLK_IN,
RESET_IN => RESET_IN,
SIGNAL_OUT => trigger_busy
);
- pulse_dtrans_3: pulse_dtrans
+ signal_async_trans_FAST_CLEAR: signal_async_trans
generic map (
- CLK_RATIO => 2
+ NUM_FF => 3
)
port map (
- CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_IN,
- PULSE_A_IN => fast_clear_o,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => fast_clear
+ CLK_IN => NX_MAIN_CLK_IN,
+ RESET_IN => RESET_IN,
+ SIGNAL_A_IN => fast_clear_o,
+ SIGNAL_OUT => fast_clear
);
- pulse_dtrans_2: pulse_dtrans
+ pulse_dtrans_INVALID_TIMING_TRIGGER: pulse_dtrans
generic map (
CLK_RATIO => 4
)
when S_CTS_TRIGGER =>
valid_trigger_o <= '1';
timing_trigger_o <= '1';
- if (reg_testpulse_enable = '1') then
+ if (testpulse_enable = '1') then
send_testpulse_l <= '1';
end if;
STATE <= S_WAIT_TRG_DATA_VALID;
PROC_EVENT_DATA_MULTIPLEXER: process(TRIGGER_TYPE)
begin
case TRIGGER_TYPE is
- when T_UNDEF | T_IGNORE | T_INTERNAL =>
+ when T_UNDEF | T_IGNORE | T_INTERNAL | T_TIMING =>
fee_data_o <= (others => '0');
fee_data_write_o <= '0';
- when T_TIMING =>
- fee_data_o <= FEE_DATA_0_IN;
- fee_data_write_o <= FEE_DATA_WRITE_0_IN;
+ --when T_TIMING =>
+ -- fee_data_o <= FEE_DATA_0_IN;
+ -- fee_data_write_o <= FEE_DATA_WRITE_0_IN;
when T_SETUP =>
fee_data_o <= FEE_DATA_1_IN;
TIMER_START_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
+
+ signal_async_trans_TESTPULSE_ENABLE: signal_async_trans
+ generic map (
+ NUM_FF => 2
+ )
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ RESET_IN => RESET_IN,
+ SIGNAL_A_IN => reg_testpulse_enable,
+ SIGNAL_OUT => testpulse_enable
+ );
+ bus_async_trans_TESTPULSE_DELAY: bus_async_trans
+ generic map (
+ BUS_WIDTH => 12,
+ NUM_FF => 2
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SIGNAL_A_IN => reg_testpulse_delay,
+ SIGNAL_OUT => testpulse_delay
+ );
+
PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
when T_IDLE =>
if (send_testpulse = '1') then
- if (reg_testpulse_delay > 0) then
- wait_timer_init <= reg_testpulse_delay;
+ if (testpulse_delay > 0) then
+ wait_timer_init <= testpulse_delay;
T_STATE <= T_WAIT_TIMER;
else
T_STATE <= T_SET_TESTPULSE;
slv_ack_o <= '1';
when x"0001" =>
- reg_testpulse_delay <=
- unsigned(SLV_DATA_IN(11 downto 0));
- slv_ack_o <= '1';
+ if (unsigned(SLV_DATA_IN(11 downto 0)) > 1) then
+ reg_testpulse_delay <=
+ unsigned(SLV_DATA_IN(11 downto 0));
+ else
+ reg_testpulse_delay <= x"001";
+ end if;
+ slv_ack_o <= '1';
when x"0003" =>
invalid_t_trigger_ctr_clear <= '1';
);
end component;
+component bus_async_trans
+ generic (
+ BUS_WIDTH : integer range 2 to 32;
+ NUM_FF : integer range 2 to 4);
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SIGNAL_A_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(BUS_WIDTH - 1 downto 0)
+ );
+end component;
+
component pulse_dtrans
generic (
CLK_RATIO : integer range 2 to 15
signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0);
signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0);
signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0);
-
+
-- TRB Register
signal i2c_sm_reset_o : std_logic;
signal nx_ts_reset_1 : std_logic;
signal error_data_receiver : std_logic;
-- Debug Handler
- constant DEBUG_NUM_PORTS : integer := 14;
+ constant DEBUG_NUM_PORTS : integer := 15;
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
+ -- buffer
+ signal nx_setup_data_f : std_logic_vector(31 downto 0);
+ signal nx_setup_ack_f : std_logic;
+ signal nx_setup_no_more_data_f : std_logic;
+ signal nx_setup_unknown_addr_f : std_logic;
+ signal nx_setup_data_ff : std_logic_vector(31 downto 0);
+ signal nx_setup_ack_ff : std_logic;
+ signal nx_setup_no_more_data_ff : std_logic;
+ signal nx_setup_unknown_addr_ff : std_logic;
+
begin
-------------------------------------------------------------------------------
BUS_DATAREADY_IN => slv_ack,
BUS_WRITE_ACK_IN => slv_ack,
BUS_NO_MORE_DATA_IN => slv_no_more_data,
- BUS_UNKNOWN_ADDR_IN => slv_unknown_addr,
+ BUS_UNKNOWN_ADDR_IN => slv_unknown_addr,
-- DEBUG
STAT_DEBUG => open
);
-
-------------------------------------------------------------------------------
-- Registers
-------------------------------------------------------------------------------
INT_DATA_OUT => int_data,
SLV_READ_IN => slv_read(9),
SLV_WRITE_IN => slv_write(9),
- SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),
+ SLV_DATA_OUT => nx_setup_data_f,
SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),
SLV_ADDR_IN => slv_addr(9*16+15 downto 9*16),
- SLV_ACK_OUT => slv_ack(9),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(9),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9),
+ SLV_ACK_OUT => nx_setup_ack_f,
+ SLV_NO_MORE_DATA_OUT => nx_setup_no_more_data_f,
+ SLV_UNKNOWN_ADDR_OUT => nx_setup_unknown_addr_f,
DEBUG_OUT => debug_line(1)
);
+ PROC_NX_SETUP_BUFFER: process (CLK_IN, RESET_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ nx_setup_data_ff <= nx_setup_data_f;
+ nx_setup_ack_ff <= nx_setup_ack_f;
+ nx_setup_no_more_data_ff <= nx_setup_no_more_data_f;
+ nx_setup_unknown_addr_ff <= nx_setup_unknown_addr_f;
+
+ slv_data_rd(9*32+31 downto 9*32) <= nx_setup_data_ff;
+ slv_ack(9) <= nx_setup_ack_ff;
+ slv_no_more_data(9) <= nx_setup_no_more_data_ff;
+ slv_unknown_addr(9) <= nx_setup_unknown_addr_ff;
+ end if;
+ end process PROC_NX_SETUP_BUFFER;
+
-------------------------------------------------------------------------------
-- I2C master block for accessing the nXyter
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => slv_no_more_data(11),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11)
);
-
+ debug_line(14)(0) <= CLK_IN;
+ debug_line(14)(13 downto 1) <= slv_read;
+ debug_line(14)(14) <= '0';
+ debug_line(14)(15) <= '0';
-------------------------------------------------------------------------------
-- END
-------------------------------------------------------------------------------
end entity;
architecture Behavioral of pulse_dtrans is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "PULSE_DTRANS";
signal pulse_a_l : std_logic;
signal pulse_b_o : std_logic;
begin
-
-----------------------------------------------------------------------------
-- Clock A Domain
-----------------------------------------------------------------------------
end entity;
architecture Behavioral of pulse_to_level is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "PULSE_TO_LEVEL";
signal start_timer_x : unsigned(4 downto 0);
0x850f : r ADC Not Lock Frame Counter, should be constant
0x8510 : r Raw Nxyter Frame Rate, must be 31.25 MHz
0x8511 : r Raw ADC Frame Rate, must be 31.25 MHz
-0x8512 : r/w Debug Multiplexer:
+0x8512 : r Test ADC Value
+0x8513 : r/w Debug Multiplexer:
0: no ADC Values, normal Debug
1: ADC Value Nxyter
2: ADC Value Testchannel
end entity;
architecture Behavioral of signal_async_to_pulse is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TO_PULSE";
+
signal pulse_ff : std_logic_vector(NUM_FF - 1 downto 0);
signal pulse_o : std_logic;
end entity;
architecture Behavioral of signal_async_trans is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TRANS";
+
signal signal_ff : std_logic_vector(NUM_FF - 1 downto 0);
signal signal_o : std_logic;
add_file -vhdl -lib "work" "source/pulse_dtrans.vhd"
add_file -vhdl -lib "work" "source/signal_async_to_pulse.vhd"
add_file -vhdl -lib "work" "source/signal_async_trans.vhd"
+add_file -vhdl -lib "work" "source/bus_async_trans.vhd"
add_file -vhdl -lib "work" "source/pulse_delay.vhd"
add_file -vhdl -lib "work" "source/gray_decoder.vhd"
add_file -vhdl -lib "work" "source/gray_encoder.vhd"
add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
-add_file -vhdl -lib "work" "source/ddr_generic_single.vhd"
add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-use work.nxyter_components.all;
-
-library ecp3;
-use ecp3.components.all;
-
-
-entity trb3_periph is
- port(
- --Clocks
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- --Trigger
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- TRIGGER_RIGHT : in std_logic; --Den Da nehmen sagt Jan midestend
- -- , right side trigger input from fan-out
- --Serdes
- CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- SERDES_INT_TX : out std_logic_vector(3 downto 0);
- SERDES_INT_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
-
- ---------------------------------------------------------------------------
- -- BEGIN AddonBoard nXyter
- ---------------------------------------------------------------------------
- --Connections to NXYTER-FEB 1
-
- NX1_RESET_OUT : out std_logic;
- NX1_I2C_SDA_INOUT : inout std_logic;
- NX1_I2C_SCL_INOUT : inout std_logic;
- NX1_I2C_SM_RESET_OUT : out std_logic;
- NX1_I2C_REG_RESET_OUT : out std_logic;
- NX1_SPI_SCLK_OUT : out std_logic;
- NX1_SPI_SDIO_INOUT : inout std_logic;
- NX1_SPI_CSB_OUT : out std_logic;
- NX1_DATA_CLK_IN : in std_logic;
- NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX1_MAIN_CLK_OUT : out std_logic;
- NX1_TESTPULSE_OUT : out std_logic;
- NX1_TS_HOLD_OUT : out std_logic;
- NX1_ADC_FCLK_IN : in std_logic;
- NX1_ADC_DCLK_IN : in std_logic;
- NX1_ADC_SAMPLE_CLK_OUT : out std_logic;
- NX1_ADC_A_IN : in std_logic;
- NX1_ADC_B_IN : in std_logic;
- NX1_ADC_NX_IN : in std_logic;
- NX1_ADC_D_IN : in std_logic;
- NX1B_ADC_FCLK_IN : in std_logic;
- NX1B_ADC_DCLK_IN : in std_logic;
- NX1B_ADC_A_IN : in std_logic;
- NX1B_ADC_B_IN : in std_logic;
- NX1B_ADC_NX_IN : in std_logic;
- NX1B_ADC_D_IN : in std_logic;
-
- --Connections to NXYTER-FEB 2
-
- NX2_RESET_OUT : out std_logic;
- NX2_I2C_SDA_INOUT : inout std_logic;
- NX2_I2C_SCL_INOUT : inout std_logic;
- NX2_I2C_SM_RESET_OUT : out std_logic;
- NX2_I2C_REG_RESET_OUT : out std_logic;
- NX2_SPI_SCLK_OUT : out std_logic;
- NX2_SPI_SDIO_INOUT : inout std_logic;
- NX2_SPI_CSB_OUT : out std_logic;
- NX2_DATA_CLK_IN : in std_logic;
- NX2_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX2_MAIN_CLK_OUT : out std_logic;
- NX2_TESTPULSE_OUT : out std_logic;
- NX2_TS_HOLD_OUT : out std_logic;
- NX2_ADC_FCLK_IN : in std_logic;
- NX2_ADC_DCLK_IN : in std_logic;
- NX2_ADC_SAMPLE_CLK_OUT : out std_logic;
- NX2_ADC_A_IN : in std_logic;
- NX2_ADC_B_IN : in std_logic;
- NX2_ADC_NX_IN : in std_logic;
- NX2_ADC_D_IN : in std_logic;
- NX2B_ADC_FCLK_IN : in std_logic;
- NX2B_ADC_DCLK_IN : in std_logic;
- NX2B_ADC_A_IN : in std_logic;
- NX2B_ADC_B_IN : in std_logic;
- NX2B_ADC_NX_IN : in std_logic;
- NX2B_ADC_D_IN : in std_logic;
-
- ADDON_TRIGGER_OUT : out std_logic;
-
- ---------------------------------------------------------------------------
- -- END AddonBoard nXyter
- ---------------------------------------------------------------------------
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of TRIGGER_LEFT : signal is false;
- attribute syn_useioff of TRIGGER_RIGHT : signal is false;
- --important signals
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_useioff of TEST_LINE : signal is true;
- --attribute syn_useioff of INP : signal is false;
- attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
- attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
-
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of NX2_ADC_NX_IN : signal is true;
- --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
- --attribute syn_useioff of NX2_ADC_D_IN : signal is true;
-
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of DAC_SDO : signal is true;
- --attribute syn_useioff of DAC_SDI : signal is true;
- --attribute syn_useioff of DAC_SCK : signal is true;
- --attribute syn_useioff of DAC_CS : signal is true;
-
-
-end entity;
-
-
-architecture trb3_periph_arch of trb3_periph is
-
- -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
- attribute ODDRAPPS : string;
- attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
- attribute ODDRAPPS of THE_NX_MAIN_ODDR_2 : label is "SCLK_ALIGNED";
- -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED";
- -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_2 : label is "SCLK_ALIGNED";
-
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 5;
- constant REGIO_NUM_CTRL_REGS : integer := 3;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- --Clock / Reset
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
-
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
-
- --LVL1 channel
- signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i : std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic_vector(2-1 downto 0);
- signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0);
- signal fee_data_i : std_logic_vector(2*32-1 downto 0);
- signal fee_data_write_i : std_logic_vector(2-1 downto 0);
- signal fee_data_finished_i : std_logic_vector(2-1 downto 0);
- signal fee_almost_full_i : std_logic_vector(2-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spictrl_read_en : std_logic;
- signal spictrl_write_en : std_logic;
- signal spictrl_data_in : std_logic_vector(31 downto 0);
- signal spictrl_addr : std_logic;
- signal spictrl_data_out : std_logic_vector(31 downto 0);
- signal spictrl_ack : std_logic;
- signal spictrl_busy : std_logic;
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(5 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_ack : std_logic;
- signal spidac_read_en : std_logic;
- signal spidac_write_en : std_logic;
- signal spidac_data_in : std_logic_vector(31 downto 0);
- signal spidac_addr : std_logic_vector(4 downto 0);
- signal spidac_data_out : std_logic_vector(31 downto 0);
- signal spidac_ack : std_logic;
- signal spidac_busy : std_logic;
-
- signal dac_cs_i : std_logic_vector(3 downto 0);
- signal dac_sck_i : std_logic;
- signal dac_sdi_i : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
- --FPGA Test
- signal time_counter : unsigned(31 downto 0);
-
- -- nXyter-FEB-Board Clocks
- signal nx_main_clk : std_logic;
- signal nx_data_clk_test : std_logic;
- signal pll_nx_clk_lock : std_logic;
- signal clk_adc_dat_1 : std_logic;
- signal clk_adc_dat_2 : std_logic;
- signal pll_adc_clk_lock_1 : std_logic;
- signal pll_adc_clk_lock_2 : std_logic;
-
- signal nx1_adc_sample_clk : std_logic;
- signal nx2_adc_sample_clk : std_logic;
-
- -- nXyter 1 Regio Bus
- signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
- signal nx1_regio_data_in : std_logic_vector (31 downto 0);
- signal nx1_regio_data_out : std_logic_vector (31 downto 0);
- signal nx1_regio_read_enable_in : std_logic;
- signal nx1_regio_write_enable_in : std_logic;
- signal nx1_regio_timeout_in : std_logic;
- signal nx1_regio_dataready_out : std_logic;
- signal nx1_regio_write_ack_out : std_logic;
- signal nx1_regio_no_more_data_out : std_logic;
- signal nx1_regio_unknown_addr_out : std_logic;
-
- signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0);
- signal fee1_trigger : std_logic;
-
- -- nXyter 2 Regio Bus
- signal nx2_regio_addr_in : std_logic_vector (15 downto 0);
- signal nx2_regio_data_in : std_logic_vector (31 downto 0);
- signal nx2_regio_data_out : std_logic_vector (31 downto 0);
- signal nx2_regio_read_enable_in : std_logic;
- signal nx2_regio_write_enable_in : std_logic;
- signal nx2_regio_timeout_in : std_logic;
- signal nx2_regio_dataready_out : std_logic;
- signal nx2_regio_write_ack_out : std_logic;
- signal nx2_regio_no_more_data_out : std_logic;
- signal nx2_regio_unknown_addr_out : std_logic;
-
- signal nx2_timestamp_sim_o : std_logic_vector(7 downto 0);
- signal fee2_trigger : std_logic;
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_PCLK_RIGHT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => c_YES, --run on 200 MHz clock
- USE_125_MHZ => c_NO,
- USE_CTC => c_NO
- )
- port map(
- CLK => CLK_PCLK_RIGHT,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => SERDES_INT_RX(2),
- SD_RXD_N_IN => SERDES_INT_RX(3),
- SD_TXD_P_OUT => SERDES_INT_TX(2),
- SD_TXD_N_OUT => SERDES_INT_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => med_stat_debug,
- CTRL_DEBUG => (others => '0')
- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"49",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100_6000",
- REGIO_INIT_ADDRESS => x"3800",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 100,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 2,
- DATA_BUFFER_DEPTH => 13, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEB
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
-
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
-
- --Response from FEB, i.e. nXyter #0
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
- FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
- FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
- FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
-
- --Response from FEE, i.e. nXyter #1
- FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1),
- FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
- FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32),
- FEE_DATA_WRITE_IN(1) => fee_data_write_i(1),
- FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1),
- FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1),
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
- timing_trg_received_i <= TRIGGER_LEFT;
-
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000",
- 1 => x"d100",
- 2 => x"8000",
- 3 => x"9000",
- others => x"0000"),
- PORT_ADDR_MASK => (0 => 1,
- 1 => 6,
- 2 => 12,
- 3 => 12,
- others => 0)
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
-
- --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
- BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
- BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
- BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
- BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
- BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
- BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
-
- --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
- BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
- BUS_ADDR_OUT(3*16+11 downto 3*16) => nx2_regio_addr_in(11 downto 0),
- BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open,
- BUS_TIMEOUT_OUT(3) => open, --nx2_regio_timeout_in,
- BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
- BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
- BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
-
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
- THE_SPI_MASTER : spi_master
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => spictrl_read_en,
- BUS_WRITE_IN => spictrl_write_en,
- BUS_BUSY_OUT => spictrl_busy,
- BUS_ACK_OUT => spictrl_ack,
- BUS_ADDR_IN(0) => spictrl_addr,
- BUS_DATA_IN => spictrl_data_in,
- BUS_DATA_OUT => spictrl_data_out,
- -- SPI connections
- SPI_CS_OUT => FLASH_CS,
- SPI_SDI_IN => FLASH_DOUT,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SCK_OUT => FLASH_CLK,
- -- BRAM for read/write data
- BRAM_A_OUT => spi_bram_addr,
- BRAM_WR_D_IN => spi_bram_wr_d,
- BRAM_RD_D_OUT => spi_bram_rd_d,
- BRAM_WE_OUT => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
- -- data memory for SPI accesses
- THE_SPI_MEMORY : spi_databus_memory
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_ACK_OUT => spimem_ack,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
- -- state machine connections
- BRAM_ADDR_IN => spi_bram_addr,
- BRAM_WR_D_OUT => spi_bram_wr_d,
- BRAM_RD_D_IN => spi_bram_rd_d,
- BRAM_WE_IN => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
- THE_FPGA_REBOOT : fpga_reboot
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- DO_REBOOT => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_GREEN <= not med_stat_op(9);
- LED_ORANGE <= not med_stat_op(10);
- LED_RED <= timing_trg_received_i;
- LED_YELLOW <= not med_stat_op(11);
-
------------------------------------------------------------------------------
--- The xXyter-FEB #1
------------------------------------------------------------------------------
-
- nXyter_FEE_board_0: nXyter_FEE_board
- generic map (
- BOARD_ID => "01"
- )
- port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- CLK_NX_MAIN_IN => nx_main_clk,
- CLK_ADC_IN => clk_adc_dat_1,
- PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
- PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_1,
- NX_DATA_CLK_TEST_IN => nx_data_clk_test,
-
- TRIGGER_OUT => fee1_trigger,
-
- I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
- I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
- I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
- I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
-
- SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
- SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
- SPI_CSB_OUT => NX1_SPI_CSB_OUT,
-
- NX_DATA_CLK_IN => NX1_DATA_CLK_IN,
- NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
-
- NX_RESET_OUT => NX1_RESET_OUT,
- NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
- NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT,
-
- ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
- ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
- ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
- ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
- ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk,
- ADC_A_IN(0) => NX1_ADC_A_IN,
- ADC_A_IN(1) => NX1B_ADC_A_IN,
- ADC_B_IN(0) => NX1_ADC_B_IN,
- ADC_B_IN(1) => NX1B_ADC_B_IN,
- ADC_NX_IN(0) => NX1_ADC_NX_IN,
- ADC_NX_IN(1) => NX1B_ADC_NX_IN,
- ADC_D_IN(0) => NX1_ADC_D_IN,
- ADC_D_IN(1) => NX1B_ADC_D_IN,
-
- TIMING_TRIGGER_IN => TRIGGER_RIGHT,
- LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
- LVL1_INVALID_TRG_IN => trg_invalid_i,
- LVL1_TRG_TYPE_IN => trg_type_i,
- LVL1_TRG_NUMBER_IN => trg_number_i,
- LVL1_TRG_CODE_IN => trg_code_i,
- LVL1_TRG_INFORMATION_IN => trg_information_i,
- LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
-
- FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
- FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
- FEE_DATA_OUT => fee_data_i(31 downto 0),
- FEE_DATA_WRITE_OUT => fee_data_write_i(0),
- FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
- FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
-
- REGIO_ADDR_IN => nx1_regio_addr_in,
- REGIO_DATA_IN => nx1_regio_data_in,
- REGIO_DATA_OUT => nx1_regio_data_out,
- REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
- REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
- REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
- REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
- REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
- REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
-
- DEBUG_LINE_OUT => TEST_LINE
- --DEBUG_LINE_OUT => open
- );
-
------------------------------------------------------------------------------
--- The xXyter-FEB #2
------------------------------------------------------------------------------
-
- nXyter_FEE_board_1: nXyter_FEE_board
- generic map (
- BOARD_ID => "10"
- )
- port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- CLK_NX_MAIN_IN => nx_main_clk,
- CLK_ADC_IN => clk_adc_dat_2,
- PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
- PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_2,
- NX_DATA_CLK_TEST_IN => nx_data_clk_test,
- TRIGGER_OUT => fee2_trigger,
-
- I2C_SDA_INOUT => NX2_I2C_SDA_INOUT,
- I2C_SCL_INOUT => NX2_I2C_SCL_INOUT,
- I2C_SM_RESET_OUT => NX2_I2C_SM_RESET_OUT,
- I2C_REG_RESET_OUT => NX2_I2C_REG_RESET_OUT,
-
- SPI_SCLK_OUT => NX2_SPI_SCLK_OUT,
- SPI_SDIO_INOUT => NX2_SPI_SDIO_INOUT,
- SPI_CSB_OUT => NX2_SPI_CSB_OUT,
-
- NX_DATA_CLK_IN => NX2_DATA_CLK_IN,
- NX_TIMESTAMP_IN => NX2_TIMESTAMP_IN,
-
- NX_RESET_OUT => NX2_RESET_OUT,
- NX_TESTPULSE_OUT => NX2_TESTPULSE_OUT,
- NX_TIMESTAMP_TRIGGER_OUT => NX2_TS_HOLD_OUT,
-
- ADC_FCLK_IN(0) => NX2_ADC_FCLK_IN,
- ADC_FCLK_IN(1) => NX2B_ADC_FCLK_IN,
- ADC_DCLK_IN(0) => NX2_ADC_DCLK_IN,
- ADC_DCLK_IN(1) => NX2B_ADC_DCLK_IN,
- ADC_SAMPLE_CLK_OUT => nx2_adc_sample_clk,
- ADC_A_IN(0) => NX2_ADC_A_IN,
- ADC_A_IN(1) => NX2B_ADC_A_IN,
- ADC_B_IN(0) => NX2_ADC_B_IN,
- ADC_B_IN(1) => NX2B_ADC_B_IN,
- ADC_NX_IN(0) => NX2_ADC_NX_IN,
- ADC_NX_IN(1) => NX2B_ADC_NX_IN,
- ADC_D_IN(0) => NX2_ADC_D_IN,
- ADC_D_IN(1) => NX2B_ADC_D_IN,
-
- TIMING_TRIGGER_IN => TRIGGER_RIGHT,
- LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
- LVL1_INVALID_TRG_IN => trg_invalid_i,
- LVL1_TRG_TYPE_IN => trg_type_i,
- LVL1_TRG_NUMBER_IN => trg_number_i,
- LVL1_TRG_CODE_IN => trg_code_i,
- LVL1_TRG_INFORMATION_IN => trg_information_i,
- LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
-
- FEE_TRG_RELEASE_OUT => fee_trg_release_i(1),
- FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(63 downto 32),
- FEE_DATA_OUT => fee_data_i(63 downto 32),
- FEE_DATA_WRITE_OUT => fee_data_write_i(1),
- FEE_DATA_FINISHED_OUT => fee_data_finished_i(1),
- FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(1),
-
- REGIO_ADDR_IN => nx2_regio_addr_in,
- REGIO_DATA_IN => nx2_regio_data_in,
- REGIO_DATA_OUT => nx2_regio_data_out,
- REGIO_READ_ENABLE_IN => nx2_regio_read_enable_in,
- REGIO_WRITE_ENABLE_IN => nx2_regio_write_enable_in,
- REGIO_TIMEOUT_IN => nx2_regio_timeout_in,
- REGIO_DATAREADY_OUT => nx2_regio_dataready_out,
- REGIO_WRITE_ACK_OUT => nx2_regio_write_ack_out,
- REGIO_NO_MORE_DATA_OUT => nx2_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx2_regio_unknown_addr_out,
-
- --DEBUG_LINE_OUT => TEST_LINE
- DEBUG_LINE_OUT => open
- );
-
- ADDON_TRIGGER_OUT <= fee1_trigger or fee2_trigger;
-
- -----------------------------------------------------------------------------
- -- nXyter Main and ADC Clocks
- -----------------------------------------------------------------------------
-
- -- nXyter Main Clock (250MHz)
- pll_nx_clk250_1: entity work.pll_nx_clk250
- port map (
- CLK => CLK_PCLK_RIGHT,
- CLKOP => nx_main_clk,
- CLKOK => nx_data_clk_test,
- LOCK => pll_nx_clk_lock
- );
-
- -- Port FF for Nxyter Main Clocks
- THE_NX_MAIN_ODDR_1: ODDRXD1
- port map(
- SCLK => nx_main_clk,
- DA => '1',
- DB => '0',
- Q => NX1_MAIN_CLK_OUT
- );
-
- THE_NX_MAIN_ODDR_2: ODDRXD1
- port map(
- SCLK => nx_main_clk,
- DA => '1',
- DB => '0',
- Q => NX2_MAIN_CLK_OUT
- );
-
- --NX1_MAIN_CLK_OUT <= nx_main_clk;
- --NX2_MAIN_CLK_OUT <= nx_main_clk;
-
- -- -- ADC Sample Clocks
- -- THE_ADC_SAMPLE_ODDR_1: ODDRXD1
- -- port map(
- -- SCLK => nx1_adc_sample_clk,
- -- DA => '1',
- -- DB => '0',
- -- Q => NX1_ADC_SAMPLE_CLK_OUT
- -- );
- --
- -- THE_ADC_SAMPLE_ODDR_2: ODDRXD1
- -- port map(
- -- SCLK => nx2_adc_sample_clk,
- -- DA => '1',
- -- DB => '0',
- -- Q => NX2_ADC_SAMPLE_CLK_OUT
- -- );
-
- NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk;
- NX2_ADC_SAMPLE_CLK_OUT <= nx2_adc_sample_clk;
-
- -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
- -- based on same ClockSource as nXyter Main Clock)
- pll_adc_clk_1: pll_adc_clk
- port map (
- CLK => CLK_PCLK_RIGHT,
- CLKOP => clk_adc_dat_1,
- LOCK => pll_adc_clk_lock_1
- );
-
- pll_adc_clk_2: pll_adc_clk
- port map (
- CLK => CLK_PCLK_RIGHT,
- CLKOP => clk_adc_dat_2,
- LOCK => pll_adc_clk_lock_2
- );
-
-end architecture;
--- /dev/null
+trb3_periph_nx2.vhd
\ No newline at end of file
# Speed for the configuration Flash access
SYSCONFIG MCCLK_FREQ = 20;
- # Not used in current design
- #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
- #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz;
# Relax some of the timing constraints
#################################################################
-#MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns;
-#MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns;
-
MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
-MULTICYCLE FROM CLKNET "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9228_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns;
-MULTICYCLE FROM CLKNET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns;
-#MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/pulse_dtrans_2/pulse_async_trans_1/pulse_ff_1" 5 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/timestamp_sync_x" 5 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/trigger_x" 5 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 20 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_FAST_CLEAR*" 20 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_IINVALID_TIMING_TRIGGER*" 20 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TESTPULSE_ENABLE*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/bus_async_trans_TESTPULSE_DELAY*" 100 ns;
+
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_generator_*/bus_async_trans_TESTPULSE_LENGTH*" 100 ns;
-#MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/pulse_dtrans_2/pulse_async_trans_1/pulse_ff_1" 5 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/timestamp_sync_x" 5 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/trigger_x" 5 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_to_pulse_TIMESTAMP_SYNC_IN*" 20 ns;
#################################################################
# Constraints for nxyter inputs
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+use work.nxyter_components.all;
+
+library ecp3;
+use ecp3.components.all;
+
+
+entity trb3_periph is
+ port(
+ --Clocks
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --Den Da nehmen sagt Jan midestend
+ -- , right side trigger input from fan-out
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+
+ ---------------------------------------------------------------------------
+ -- BEGIN AddonBoard nXyter
+ ---------------------------------------------------------------------------
+ --Connections to NXYTER-FEB 1
+
+ NX1_RESET_OUT : out std_logic;
+ NX1_I2C_SDA_INOUT : inout std_logic;
+ NX1_I2C_SCL_INOUT : inout std_logic;
+ NX1_I2C_SM_RESET_OUT : out std_logic;
+ NX1_I2C_REG_RESET_OUT : out std_logic;
+ NX1_SPI_SCLK_OUT : out std_logic;
+ NX1_SPI_SDIO_INOUT : inout std_logic;
+ NX1_SPI_CSB_OUT : out std_logic;
+ NX1_DATA_CLK_IN : in std_logic;
+ NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX1_MAIN_CLK_OUT : out std_logic;
+ NX1_TESTPULSE_OUT : out std_logic;
+ NX1_TS_HOLD_OUT : out std_logic;
+ NX1_ADC_FCLK_IN : in std_logic;
+ NX1_ADC_DCLK_IN : in std_logic;
+ NX1_ADC_SAMPLE_CLK_OUT : out std_logic;
+ NX1_ADC_A_IN : in std_logic;
+ NX1_ADC_B_IN : in std_logic;
+ NX1_ADC_NX_IN : in std_logic;
+ NX1_ADC_D_IN : in std_logic;
+ NX1B_ADC_FCLK_IN : in std_logic;
+ NX1B_ADC_DCLK_IN : in std_logic;
+ NX1B_ADC_A_IN : in std_logic;
+ NX1B_ADC_B_IN : in std_logic;
+ NX1B_ADC_NX_IN : in std_logic;
+ NX1B_ADC_D_IN : in std_logic;
+
+ ADDON_TRIGGER_OUT : out std_logic;
+
+ ---------------------------------------------------------------------------
+ -- END AddonBoard nXyter
+ ---------------------------------------------------------------------------
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ --important signals
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+ --attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of DAC_SDO : signal is true;
+ --attribute syn_useioff of DAC_SDI : signal is true;
+ --attribute syn_useioff of DAC_SCK : signal is true;
+ --attribute syn_useioff of DAC_CS : signal is true;
+
+
+end entity;
+
+
+architecture trb3_periph_arch of trb3_periph is
+
+ -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
+ attribute ODDRAPPS : string;
+ attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED";
+
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 5;
+ constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i : std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic_vector(2-1 downto 0);
+ signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_write_i : std_logic_vector(2-1 downto 0);
+ signal fee_data_finished_i : std_logic_vector(2-1 downto 0);
+ signal fee_almost_full_i : std_logic_vector(2-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+ signal spidac_read_en : std_logic;
+ signal spidac_write_en : std_logic;
+ signal spidac_data_in : std_logic_vector(31 downto 0);
+ signal spidac_addr : std_logic_vector(4 downto 0);
+ signal spidac_data_out : std_logic_vector(31 downto 0);
+ signal spidac_ack : std_logic;
+ signal spidac_busy : std_logic;
+
+ signal dac_cs_i : std_logic_vector(3 downto 0);
+ signal dac_sck_i : std_logic;
+ signal dac_sdi_i : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ --FPGA Test
+ signal time_counter : unsigned(31 downto 0);
+
+ -- nXyter-FEB-Board Clocks
+ signal nx_main_clk : std_logic;
+ signal nx_data_clk_test : std_logic;
+ signal pll_nx_clk_lock : std_logic;
+ signal clk_adc_dat_1 : std_logic;
+ signal pll_adc_clk_lock_1 : std_logic;
+
+ signal nx1_adc_sample_clk : std_logic;
+
+ -- nXyter 1 Regio Bus
+ signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
+ signal nx1_regio_data_in : std_logic_vector (31 downto 0);
+ signal nx1_regio_data_out : std_logic_vector (31 downto 0);
+ signal nx1_regio_read_enable_in : std_logic;
+ signal nx1_regio_write_enable_in : std_logic;
+ signal nx1_regio_timeout_in : std_logic;
+ signal nx1_regio_dataready_out : std_logic;
+ signal nx1_regio_write_ack_out : std_logic;
+ signal nx1_regio_no_more_data_out : std_logic;
+ signal nx1_regio_unknown_addr_out : std_logic;
+
+ signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0);
+ signal fee1_trigger : std_logic;
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"49",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100_6000",
+ REGIO_INIT_ADDRESS => x"3800",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 2,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEB
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEB, i.e. nXyter #0
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
+ FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
+
+ --Response from FEE, i.e. nXyter #1
+ FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1),
+ FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
+ FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32),
+ FEE_DATA_WRITE_IN(1) => fee_data_write_i(1),
+ FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1),
+ FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1),
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000",
+ 1 => x"d100",
+ 2 => x"8000",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1,
+ 1 => 6,
+ 2 => 12,
+ others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
+ BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+ BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
+ BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
+ BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+ -- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN
+ );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= timing_trg_received_i;
+ LED_YELLOW <= not med_stat_op(11);
+
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #1
+-----------------------------------------------------------------------------
+
+ nXyter_FEE_board_0: nXyter_FEE_board
+ generic map (
+ BOARD_ID => "01"
+ )
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ CLK_NX_MAIN_IN => nx_main_clk,
+ CLK_ADC_IN => clk_adc_dat_1,
+ PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
+ PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_1,
+ NX_DATA_CLK_TEST_IN => nx_data_clk_test,
+
+ TRIGGER_OUT => fee1_trigger,
+
+ I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX1_SPI_CSB_OUT,
+
+ NX_DATA_CLK_IN => NX1_DATA_CLK_IN,
+ NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
+
+ NX_RESET_OUT => NX1_RESET_OUT,
+ NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
+ NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT,
+
+ ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk,
+ ADC_A_IN(0) => NX1_ADC_A_IN,
+ ADC_A_IN(1) => NX1B_ADC_A_IN,
+ ADC_B_IN(0) => NX1_ADC_B_IN,
+ ADC_B_IN(1) => NX1B_ADC_B_IN,
+ ADC_NX_IN(0) => NX1_ADC_NX_IN,
+ ADC_NX_IN(1) => NX1B_ADC_NX_IN,
+ ADC_D_IN(0) => NX1_ADC_D_IN,
+ ADC_D_IN(1) => NX1B_ADC_D_IN,
+
+ TIMING_TRIGGER_IN => TRIGGER_RIGHT,
+ LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_IN => trg_invalid_i,
+ LVL1_TRG_TYPE_IN => trg_type_i,
+ LVL1_TRG_NUMBER_IN => trg_number_i,
+ LVL1_TRG_CODE_IN => trg_code_i,
+ LVL1_TRG_INFORMATION_IN => trg_information_i,
+ LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
+
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
+ FEE_DATA_OUT => fee_data_i(31 downto 0),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(0),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
+
+ REGIO_ADDR_IN => nx1_regio_addr_in,
+ REGIO_DATA_IN => nx1_regio_data_in,
+ REGIO_DATA_OUT => nx1_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+
+ DEBUG_LINE_OUT => TEST_LINE
+ --DEBUG_LINE_OUT => open
+ );
+
+ ADDON_TRIGGER_OUT <= fee1_trigger;
+
+ -----------------------------------------------------------------------------
+ -- nXyter Main and ADC Clocks
+ -----------------------------------------------------------------------------
+
+ -- nXyter Main Clock (250MHz)
+ pll_nx_clk250_1: entity work.pll_nx_clk250
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => nx_main_clk,
+ CLKOK => nx_data_clk_test,
+ LOCK => pll_nx_clk_lock
+ );
+
+ -- Port FF for Nxyter Main Clocks
+ THE_NX_MAIN_ODDR_1: ODDRXD1
+ port map(
+ SCLK => nx_main_clk,
+ DA => '1',
+ DB => '0',
+ Q => NX1_MAIN_CLK_OUT
+ );
+
+ NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk;
+
+ -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
+ -- based on same ClockSource as nXyter Main Clock)
+ pll_adc_clk_1: pll_adc_clk
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => clk_adc_dat_1,
+ LOCK => pll_adc_clk_lock_1
+ );
+
+end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+use work.nxyter_components.all;
+
+library ecp3;
+use ecp3.components.all;
+
+
+entity trb3_periph is
+ port(
+ --Clocks
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --Den Da nehmen sagt Jan midestend
+ -- , right side trigger input from fan-out
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+
+ ---------------------------------------------------------------------------
+ -- BEGIN AddonBoard nXyter
+ ---------------------------------------------------------------------------
+ --Connections to NXYTER-FEB 1
+
+ NX1_RESET_OUT : out std_logic;
+ NX1_I2C_SDA_INOUT : inout std_logic;
+ NX1_I2C_SCL_INOUT : inout std_logic;
+ NX1_I2C_SM_RESET_OUT : out std_logic;
+ NX1_I2C_REG_RESET_OUT : out std_logic;
+ NX1_SPI_SCLK_OUT : out std_logic;
+ NX1_SPI_SDIO_INOUT : inout std_logic;
+ NX1_SPI_CSB_OUT : out std_logic;
+ NX1_DATA_CLK_IN : in std_logic;
+ NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX1_MAIN_CLK_OUT : out std_logic;
+ NX1_TESTPULSE_OUT : out std_logic;
+ NX1_TS_HOLD_OUT : out std_logic;
+ NX1_ADC_FCLK_IN : in std_logic;
+ NX1_ADC_DCLK_IN : in std_logic;
+ NX1_ADC_SAMPLE_CLK_OUT : out std_logic;
+ NX1_ADC_A_IN : in std_logic;
+ NX1_ADC_B_IN : in std_logic;
+ NX1_ADC_NX_IN : in std_logic;
+ NX1_ADC_D_IN : in std_logic;
+ NX1B_ADC_FCLK_IN : in std_logic;
+ NX1B_ADC_DCLK_IN : in std_logic;
+ NX1B_ADC_A_IN : in std_logic;
+ NX1B_ADC_B_IN : in std_logic;
+ NX1B_ADC_NX_IN : in std_logic;
+ NX1B_ADC_D_IN : in std_logic;
+
+ --Connections to NXYTER-FEB 2
+
+ NX2_RESET_OUT : out std_logic;
+ NX2_I2C_SDA_INOUT : inout std_logic;
+ NX2_I2C_SCL_INOUT : inout std_logic;
+ NX2_I2C_SM_RESET_OUT : out std_logic;
+ NX2_I2C_REG_RESET_OUT : out std_logic;
+ NX2_SPI_SCLK_OUT : out std_logic;
+ NX2_SPI_SDIO_INOUT : inout std_logic;
+ NX2_SPI_CSB_OUT : out std_logic;
+ NX2_DATA_CLK_IN : in std_logic;
+ NX2_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX2_MAIN_CLK_OUT : out std_logic;
+ NX2_TESTPULSE_OUT : out std_logic;
+ NX2_TS_HOLD_OUT : out std_logic;
+ NX2_ADC_FCLK_IN : in std_logic;
+ NX2_ADC_DCLK_IN : in std_logic;
+ NX2_ADC_SAMPLE_CLK_OUT : out std_logic;
+ NX2_ADC_A_IN : in std_logic;
+ NX2_ADC_B_IN : in std_logic;
+ NX2_ADC_NX_IN : in std_logic;
+ NX2_ADC_D_IN : in std_logic;
+ NX2B_ADC_FCLK_IN : in std_logic;
+ NX2B_ADC_DCLK_IN : in std_logic;
+ NX2B_ADC_A_IN : in std_logic;
+ NX2B_ADC_B_IN : in std_logic;
+ NX2B_ADC_NX_IN : in std_logic;
+ NX2B_ADC_D_IN : in std_logic;
+
+ ADDON_TRIGGER_OUT : out std_logic;
+
+ ---------------------------------------------------------------------------
+ -- END AddonBoard nXyter
+ ---------------------------------------------------------------------------
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ --important signals
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+ --attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
+ attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX2_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
+ --attribute syn_useioff of NX2_ADC_D_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of DAC_SDO : signal is true;
+ --attribute syn_useioff of DAC_SDI : signal is true;
+ --attribute syn_useioff of DAC_SCK : signal is true;
+ --attribute syn_useioff of DAC_CS : signal is true;
+
+
+end entity;
+
+
+architecture trb3_periph_arch of trb3_periph is
+
+ -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
+ attribute ODDRAPPS : string;
+ attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
+ attribute ODDRAPPS of THE_NX_MAIN_ODDR_2 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_2 : label is "SCLK_ALIGNED";
+
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 5;
+ constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i : std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic_vector(2-1 downto 0);
+ signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_write_i : std_logic_vector(2-1 downto 0);
+ signal fee_data_finished_i : std_logic_vector(2-1 downto 0);
+ signal fee_almost_full_i : std_logic_vector(2-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+ signal spidac_read_en : std_logic;
+ signal spidac_write_en : std_logic;
+ signal spidac_data_in : std_logic_vector(31 downto 0);
+ signal spidac_addr : std_logic_vector(4 downto 0);
+ signal spidac_data_out : std_logic_vector(31 downto 0);
+ signal spidac_ack : std_logic;
+ signal spidac_busy : std_logic;
+
+ signal dac_cs_i : std_logic_vector(3 downto 0);
+ signal dac_sck_i : std_logic;
+ signal dac_sdi_i : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ --FPGA Test
+ signal time_counter : unsigned(31 downto 0);
+
+ -- nXyter-FEB-Board Clocks
+ signal nx_main_clk : std_logic;
+ signal nx_data_clk_test : std_logic;
+ signal pll_nx_clk_lock : std_logic;
+ signal clk_adc_dat_1 : std_logic;
+ signal clk_adc_dat_2 : std_logic;
+ signal pll_adc_clk_lock_1 : std_logic;
+ signal pll_adc_clk_lock_2 : std_logic;
+
+ signal nx1_adc_sample_clk : std_logic;
+ signal nx2_adc_sample_clk : std_logic;
+
+ -- nXyter 1 Regio Bus
+ signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
+ signal nx1_regio_data_in : std_logic_vector (31 downto 0);
+ signal nx1_regio_data_out : std_logic_vector (31 downto 0);
+ signal nx1_regio_read_enable_in : std_logic;
+ signal nx1_regio_write_enable_in : std_logic;
+ signal nx1_regio_timeout_in : std_logic;
+ signal nx1_regio_dataready_out : std_logic;
+ signal nx1_regio_write_ack_out : std_logic;
+ signal nx1_regio_no_more_data_out : std_logic;
+ signal nx1_regio_unknown_addr_out : std_logic;
+
+ signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0);
+ signal fee1_trigger : std_logic;
+
+ -- nXyter 2 Regio Bus
+ signal nx2_regio_addr_in : std_logic_vector (15 downto 0);
+ signal nx2_regio_data_in : std_logic_vector (31 downto 0);
+ signal nx2_regio_data_out : std_logic_vector (31 downto 0);
+ signal nx2_regio_read_enable_in : std_logic;
+ signal nx2_regio_write_enable_in : std_logic;
+ signal nx2_regio_timeout_in : std_logic;
+ signal nx2_regio_dataready_out : std_logic;
+ signal nx2_regio_write_ack_out : std_logic;
+ signal nx2_regio_no_more_data_out : std_logic;
+ signal nx2_regio_unknown_addr_out : std_logic;
+
+ signal nx2_timestamp_sim_o : std_logic_vector(7 downto 0);
+ signal fee2_trigger : std_logic;
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"49",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100_6000",
+ REGIO_INIT_ADDRESS => x"3800",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 2,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEB
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEB, i.e. nXyter #0
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
+ FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
+
+ --Response from FEE, i.e. nXyter #1
+ FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1),
+ FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
+ FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32),
+ FEE_DATA_WRITE_IN(1) => fee_data_write_i(1),
+ FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1),
+ FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1),
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000",
+ 1 => x"d100",
+ 2 => x"8000",
+ 3 => x"9000",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1,
+ 1 => 6,
+ 2 => 12,
+ 3 => 12,
+ others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
+ BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+ BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
+ BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
+ BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
+
+ --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
+ BUS_ADDR_OUT(3*16+11 downto 3*16) => nx2_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open,
+ BUS_TIMEOUT_OUT(3) => open, --nx2_regio_timeout_in,
+ BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
+ BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
+ BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
+
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+ -- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN
+ );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= timing_trg_received_i;
+ LED_YELLOW <= not med_stat_op(11);
+
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #1
+-----------------------------------------------------------------------------
+
+ nXyter_FEE_board_0: nXyter_FEE_board
+ generic map (
+ BOARD_ID => "01"
+ )
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ CLK_NX_MAIN_IN => nx_main_clk,
+ CLK_ADC_IN => clk_adc_dat_1,
+ PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
+ PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_1,
+ NX_DATA_CLK_TEST_IN => nx_data_clk_test,
+
+ TRIGGER_OUT => fee1_trigger,
+
+ I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX1_SPI_CSB_OUT,
+
+ NX_DATA_CLK_IN => NX1_DATA_CLK_IN,
+ NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
+
+ NX_RESET_OUT => NX1_RESET_OUT,
+ NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
+ NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT,
+
+ ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk,
+ ADC_A_IN(0) => NX1_ADC_A_IN,
+ ADC_A_IN(1) => NX1B_ADC_A_IN,
+ ADC_B_IN(0) => NX1_ADC_B_IN,
+ ADC_B_IN(1) => NX1B_ADC_B_IN,
+ ADC_NX_IN(0) => NX1_ADC_NX_IN,
+ ADC_NX_IN(1) => NX1B_ADC_NX_IN,
+ ADC_D_IN(0) => NX1_ADC_D_IN,
+ ADC_D_IN(1) => NX1B_ADC_D_IN,
+
+ TIMING_TRIGGER_IN => TRIGGER_RIGHT,
+ LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_IN => trg_invalid_i,
+ LVL1_TRG_TYPE_IN => trg_type_i,
+ LVL1_TRG_NUMBER_IN => trg_number_i,
+ LVL1_TRG_CODE_IN => trg_code_i,
+ LVL1_TRG_INFORMATION_IN => trg_information_i,
+ LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
+
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
+ FEE_DATA_OUT => fee_data_i(31 downto 0),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(0),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
+
+ REGIO_ADDR_IN => nx1_regio_addr_in,
+ REGIO_DATA_IN => nx1_regio_data_in,
+ REGIO_DATA_OUT => nx1_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+
+ DEBUG_LINE_OUT => TEST_LINE
+ --DEBUG_LINE_OUT => open
+ );
+
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #2
+-----------------------------------------------------------------------------
+
+ nXyter_FEE_board_1: nXyter_FEE_board
+ generic map (
+ BOARD_ID => "10"
+ )
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ CLK_NX_MAIN_IN => nx_main_clk,
+ CLK_ADC_IN => clk_adc_dat_2,
+ PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
+ PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_2,
+ NX_DATA_CLK_TEST_IN => nx_data_clk_test,
+ TRIGGER_OUT => fee2_trigger,
+
+ I2C_SDA_INOUT => NX2_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX2_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX2_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX2_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX2_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX2_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX2_SPI_CSB_OUT,
+
+ NX_DATA_CLK_IN => NX2_DATA_CLK_IN,
+ NX_TIMESTAMP_IN => NX2_TIMESTAMP_IN,
+
+ NX_RESET_OUT => NX2_RESET_OUT,
+ NX_TESTPULSE_OUT => NX2_TESTPULSE_OUT,
+ NX_TIMESTAMP_TRIGGER_OUT => NX2_TS_HOLD_OUT,
+
+ ADC_FCLK_IN(0) => NX2_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX2B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX2_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX2B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => nx2_adc_sample_clk,
+ ADC_A_IN(0) => NX2_ADC_A_IN,
+ ADC_A_IN(1) => NX2B_ADC_A_IN,
+ ADC_B_IN(0) => NX2_ADC_B_IN,
+ ADC_B_IN(1) => NX2B_ADC_B_IN,
+ ADC_NX_IN(0) => NX2_ADC_NX_IN,
+ ADC_NX_IN(1) => NX2B_ADC_NX_IN,
+ ADC_D_IN(0) => NX2_ADC_D_IN,
+ ADC_D_IN(1) => NX2B_ADC_D_IN,
+
+ TIMING_TRIGGER_IN => TRIGGER_RIGHT,
+ LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_IN => trg_invalid_i,
+ LVL1_TRG_TYPE_IN => trg_type_i,
+ LVL1_TRG_NUMBER_IN => trg_number_i,
+ LVL1_TRG_CODE_IN => trg_code_i,
+ LVL1_TRG_INFORMATION_IN => trg_information_i,
+ LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
+
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(1),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(63 downto 32),
+ FEE_DATA_OUT => fee_data_i(63 downto 32),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(1),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(1),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(1),
+
+ REGIO_ADDR_IN => nx2_regio_addr_in,
+ REGIO_DATA_IN => nx2_regio_data_in,
+ REGIO_DATA_OUT => nx2_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx2_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx2_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx2_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx2_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx2_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx2_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx2_regio_unknown_addr_out,
+
+ --DEBUG_LINE_OUT => TEST_LINE
+ DEBUG_LINE_OUT => open
+ );
+
+ ADDON_TRIGGER_OUT <= fee1_trigger or fee2_trigger;
+
+ -----------------------------------------------------------------------------
+ -- nXyter Main and ADC Clocks
+ -----------------------------------------------------------------------------
+
+ -- nXyter Main Clock (250MHz)
+ pll_nx_clk250_1: entity work.pll_nx_clk250
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => nx_main_clk,
+ CLKOK => nx_data_clk_test,
+ LOCK => pll_nx_clk_lock
+ );
+
+ -- Port FF for Nxyter Main Clocks
+ THE_NX_MAIN_ODDR_1: ODDRXD1
+ port map(
+ SCLK => nx_main_clk,
+ DA => '1',
+ DB => '0',
+ Q => NX1_MAIN_CLK_OUT
+ );
+
+ THE_NX_MAIN_ODDR_2: ODDRXD1
+ port map(
+ SCLK => nx_main_clk,
+ DA => '1',
+ DB => '0',
+ Q => NX2_MAIN_CLK_OUT
+ );
+
+ --NX1_MAIN_CLK_OUT <= nx_main_clk;
+ --NX2_MAIN_CLK_OUT <= nx_main_clk;
+
+ -- -- ADC Sample Clocks
+ -- THE_ADC_SAMPLE_ODDR_1: ODDRXD1
+ -- port map(
+ -- SCLK => nx1_adc_sample_clk,
+ -- DA => '1',
+ -- DB => '0',
+ -- Q => NX1_ADC_SAMPLE_CLK_OUT
+ -- );
+ --
+ -- THE_ADC_SAMPLE_ODDR_2: ODDRXD1
+ -- port map(
+ -- SCLK => nx2_adc_sample_clk,
+ -- DA => '1',
+ -- DB => '0',
+ -- Q => NX2_ADC_SAMPLE_CLK_OUT
+ -- );
+
+ NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk;
+ NX2_ADC_SAMPLE_CLK_OUT <= nx2_adc_sample_clk;
+
+ -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
+ -- based on same ClockSource as nXyter Main Clock)
+ pll_adc_clk_1: pll_adc_clk
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => clk_adc_dat_1,
+ LOCK => pll_adc_clk_lock_1
+ );
+
+ pll_adc_clk_2: pll_adc_clk
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ CLKOP => clk_adc_dat_2,
+ LOCK => pll_adc_clk_lock_2
+ );
+
+end architecture;
jspc29 / trb3.git / commitdiff