Changed lpf-files removing errors. Currently no working link.

diff --git a/soda_client.lpf b/soda_client.lpf
index 48babc7b2c795433f75bb90797c63b9f60a788c5..33939f2268cce0a9706ba81e709cee1fedfc30a2 100644 (file)
--- a/soda_client.lpf
+++ b/soda_client.lpf
@@ -1,4 +1,4 @@
-rvl_alias "reveal_ist_282" "the_sync_link/the_serdes/rx_full_clk_ch0";
+rvl_alias "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0";
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
@@ -255,14 +255,14 @@ LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
 LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 
 LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+LOCATE UGROUP "THE_SYNC_LINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
 
 
 MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20 ns;
 
 MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
 BLOCK JTAGPATHS;

diff --git a/soda_source.ldf b/soda_source.ldf
index 514b9fe82afe3c2949282752fb4f479fb706a700..5e001a3d0e51f6ddd9d4684c742ec22b9888464e 100644 (file)
--- a/soda_source.ldf
+++ b/soda_source.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_source" dir="soda_source" description="soda_source" default_strategy="Strategy1">
-        <Options top="trb3_periph_sodasource"/>
+        <Options def_top="trb3_periph_sodasource" top="trb3_periph_sodasource"/>
         <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>

diff --git a/soda_source.lpf b/soda_source.lpf
index 7bf08a50e0382282ee6de9d9c77ad0b4db71c106..068461cc7fb104dd316bc612812c46357bf6ce53 100644 (file)
--- a/soda_source.lpf
+++ b/soda_source.lpf
@@ -1,4 +1,4 @@
-rvl_alias "reveal_ist_114" "the_sync_link/the_serdes/rx_full_clk_ch0";
+rvl_alias "clk_raw_internal" "clk_raw_internal";
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
@@ -255,14 +255,14 @@ LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
 LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 
 LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+LOCATE UGROUP "THE_SYNC_LINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
 
 
 MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20 ns;
 
 MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
 BLOCK JTAGPATHS;

diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd
index 8d4c56dfd44186b2014cfd5af372863746264131..b47953607858568e8cac89c6c6c214cfa1f3048d 100644 (file)
--- a/source/med_ecp3_sfp_sync_up.vhd
+++ b/source/med_ecp3_sfp_sync_up.vhd
@@ -38,7 +38,7 @@ entity med_ecp3_sfp_sync_up is
                RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
                TX_DLM             : in  std_logic := '0';
                TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-               TX_DLM_INIT                             : in std_logic := '0';  --PL!
+               TX_DLM_PREVIEW_IN               : in std_logic := '0'; --PL!
                LINK_PHASE_OUT                  : out   std_logic := '0';       --PL!
 
                --SFP Connection
@@ -324,7 +324,7 @@ THE_TX : soda_tx_control
                START_RETRANSMIT_IN             => start_retr_i,               --TODO
                START_POSITION_IN                       => request_retr_position_i,    --TODO
 
-               TX_DLM_INIT                                     =>      TX_DLM_INIT,
+               TX_DLM_PREVIEW_IN                       =>      TX_DLM_PREVIEW_IN,
                SEND_DLM                                                => TX_DLM,
                SEND_DLM_WORD                           => TX_DLM_WORD,
 

diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 38a05303303df65c50e30805b61a9a61c88a7f1a..d78555679e38c43e44f47065ccb1425bf890187d 100644 (file)
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -15,7 +15,7 @@ package soda_components is
        constant        c_HUB_CHILDREN                                  : natural range 1 to 4 := 2;            -- number of children per soda-hub\r
        constant        cSODA_CLOCK_PERIOD                      : natural range 1 to 20 := 5;           -- soda clock-period in ns
        constant        cBURST_PERIOD                                   : natural := 2400;                                              -- particle-beam burst-period in ns\r
-       constant        cSODA_COMMAND_WINDOS_SIZE       : natural range 1 to 65535 := 5000;   -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
+       constant        cSODA_COMMAND_WINDOS_SIZE       : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
 
 
        type            t_HUB_DLM                               is array(c_HUB_CHILDREN-1 downto 0) of std_logic;\r
@@ -29,7 +29,7 @@ package soda_components is
 
        component soda_superburst_generator
                generic(
-                       BURST_COUNT : integer range 1 to 64 := 16   -- number of bursts to be counted between super-bursts
+                       BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts
                );
                port(
                        SODACLK                                                 : in    std_logic; -- fabric clock
@@ -113,7 +113,7 @@ package soda_components is
                        SODA_READ_IN                    : in    std_logic := '0';
                        SODA_WRITE_IN                   : in    std_logic := '0';
                        SODA_ACK_OUT                    : out   std_logic := '0';
-                       LEDS_OUT           : out  std_logic_vector(3 downto 0)
+                       LEDS_OUT         : out std_logic_vector(3 downto 0)
                        );
        end component;\r
 \r
@@ -164,7 +164,7 @@ package soda_components is
                        SODA_READ_IN                    : in    std_logic := '0';
                        SODA_WRITE_IN                   : in    std_logic := '0';
                        SODA_ACK_OUT                    : out   std_logic := '0';
-                       LEDS_OUT           : out  std_logic_vector(3 downto 0);
+                       LEDS_OUT         : out std_logic_vector(3 downto 0);
                        LINK_DEBUG_IN                   : in    std_logic_vector(31 downto 0)   := (others => '0')
                );
        end component;
@@ -216,28 +216,28 @@ package soda_components is
        end component;\r
 \r
        component spi_flash_and_fpga_reload
-         port(
-                CLK_IN               : in  std_logic;
-                RESET_IN             : in  std_logic;
-                
-                BUS_ADDR_IN          : in  std_logic_vector(8 downto 0);
-                BUS_READ_IN          : in  std_logic;
-                BUS_WRITE_IN         : in  std_logic;
-                BUS_DATAREADY_OUT    : out std_logic;
-                BUS_WRITE_ACK_OUT    : out std_logic;
-                BUS_UNKNOWN_ADDR_OUT : out std_logic;
-                BUS_NO_MORE_DATA_OUT : out std_logic;
-                BUS_DATA_IN          : in  std_logic_vector(31 downto 0);
-                BUS_DATA_OUT         : out std_logic_vector(31 downto 0);
-                
-                DO_REBOOT_IN   : in  std_logic;      
-                PROGRAMN       : out std_logic;
-                
-                SPI_CS_OUT     : out std_logic;
-                SPI_SCK_OUT    : out std_logic;
-                SPI_SDO_OUT    : out std_logic;
-                SPI_SDI_IN     : in  std_logic
-                );
+               port(
+                       CLK_IN : in std_logic;
+                       RESET_IN : in std_logic;
+
+                       BUS_ADDR_IN                             : in std_logic_vector(8 downto 0);
+                       BUS_READ_IN                             : in std_logic;
+                       BUS_WRITE_IN                    : in std_logic;
+                       BUS_DATAREADY_OUT               : out std_logic;
+                       BUS_WRITE_ACK_OUT               : out std_logic;
+                       BUS_UNKNOWN_ADDR_OUT    : out std_logic;
+                       BUS_NO_MORE_DATA_OUT    : out std_logic;
+                       BUS_DATA_IN                             : in std_logic_vector(31 downto 0);
+                       BUS_DATA_OUT                    : out std_logic_vector(31 downto 0);
+
+                       DO_REBOOT_IN                    : in std_logic; 
+                       PROGRAMN                                        : out std_logic;
+
+                       SPI_CS_OUT                              : out std_logic;
+                       SPI_SCK_OUT                             : out std_logic;
+                       SPI_SDO_OUT                             : out std_logic;
+                       SPI_SDI_IN                              : in std_logic
+               );
        end component;
 
        component soda_start_of_burst_faker
@@ -254,10 +254,10 @@ package soda_components is
 
        component posedge_to_pulse
                port (
-                       IN_CLK                  : in  std_logic;
-                       OUT_CLK                 : in  std_logic;
-                       CLK_EN                  : in  std_logic;
-                       SIGNAL_IN               : in  std_logic;
+                       IN_CLK                  : in std_logic;
+                       OUT_CLK                 : in std_logic;
+                       CLK_EN                  : in std_logic;
+                       SIGNAL_IN               : in std_logic;
                        PULSE_OUT               : out std_logic
                );
        end component;
@@ -265,149 +265,148 @@ package soda_components is
 component med_ecp3_sfp_sync_down is
        generic(
                SERDES_NUM                              : integer range 0 to 3 := 0;
-               IS_SYNC_SLAVE                   : integer := c_NO);       --select slave mode
+               IS_SYNC_SLAVE                   : integer := c_NO); --select slave mode
        port(
-               CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-               SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-               RESET              : in  std_logic; -- synchronous reset
-               CLEAR              : in  std_logic; -- asynchronous reset
+               CLK                                             : in std_logic; -- _internal_ 200 MHz reference clock
+               SYSCLK                                  : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+               RESET                                           : in std_logic; -- synchronous reset
+               CLEAR                                           : in std_logic; -- asynchronous reset
                --Internal Connection TX
-               MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-               MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-               MED_DATAREADY_IN   : in  std_logic;
-               MED_READ_OUT       : out std_logic := '0';
+               MED_DATA_IN                             : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+               MED_PACKET_NUM_IN               : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+               MED_DATAREADY_IN                : in std_logic;
+               MED_READ_OUT                    : out std_logic := '0';
                --Internal Connection RX
-               MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-               MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-               MED_DATAREADY_OUT  : out std_logic := '0';
-               MED_READ_IN        : in  std_logic;
-               CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
-               CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+               MED_DATA_OUT                    : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+               MED_PACKET_NUM_OUT      : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+               MED_DATAREADY_OUT               : out std_logic := '0';
+               MED_READ_IN                             : in std_logic;
+               CLK_RX_HALF_OUT         : out std_logic := '0'; --received 100 MHz
+               CLK_RX_FULL_OUT         : out std_logic := '0'; --received 200 MHz
 
                --Sync operation
-               RX_DLM             : out std_logic := '0';
-               RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-               TX_DLM             : in  std_logic := '0';
-               TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";\r
-               TX_DLM_PREVIEW_IN               : in  std_logic := '0'; --PL!\r
+               RX_DLM                                  : out std_logic := '0';
+               RX_DLM_WORD                             : out std_logic_vector(7 downto 0) := x"00";
+               TX_DLM                                  : in std_logic := '0';
+               TX_DLM_WORD                             : in std_logic_vector(7 downto 0) := x"00";\r
+               TX_DLM_PREVIEW_IN               : in std_logic := '0'; --PL!\r
                LINK_PHASE_OUT                  : out std_logic := '0'; --PL!
 
                --SFP Connection
-               SD_RXD_P_IN        : in  std_logic;
-               SD_RXD_N_IN        : in  std_logic;
-               SD_TXD_P_OUT       : out std_logic;
-               SD_TXD_N_OUT       : out std_logic;
-               SD_REFCLK_P_IN     : in  std_logic;  --not used
-               SD_REFCLK_N_IN     : in  std_logic;  --not used
-               SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-               SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-               SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+               SD_RXD_P_IN                             : in std_logic;
+               SD_RXD_N_IN                             : in std_logic;
+               SD_TXD_P_OUT                    : out std_logic;
+               SD_TXD_N_OUT                    : out std_logic;
+               SD_REFCLK_P_IN                  : in std_logic; --not used
+               SD_REFCLK_N_IN                  : in std_logic; --not used
+               SD_PRSNT_N_IN                   : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+               SD_LOS_IN                               : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+               SD_TXDIS_OUT                    : out std_logic := '0'; -- SFP disable
                --Control Interface
-               SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-               SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-               SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-               SCI_READ           : in  std_logic := '0';
-               SCI_WRITE          : in  std_logic := '0';
-               SCI_ACK            : out std_logic := '0';
-               SCI_NACK           : out std_logic := '0';
+               SCI_DATA_IN                             : in std_logic_vector(7 downto 0) := (others => '0');
+               SCI_DATA_OUT                    : out std_logic_vector(7 downto 0) := (others => '0');
+               SCI_ADDR                                        : in std_logic_vector(8 downto 0) := (others => '0');
+               SCI_READ                                        : in std_logic := '0';
+               SCI_WRITE                               : in std_logic := '0';
+               SCI_ACK                                 : out std_logic := '0';
+               SCI_NACK                                        : out std_logic := '0';
                -- Status and control port
-               STAT_OP            : out std_logic_vector (15 downto 0);
-               CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-               STAT_DEBUG         : out std_logic_vector (63 downto 0);
-               CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+               STAT_OP                                 : out std_logic_vector (15 downto 0);
+               CTRL_OP                                 : in std_logic_vector (15 downto 0) := (others => '0');
+               STAT_DEBUG                              : out std_logic_vector (63 downto 0);
+               CTRL_DEBUG                              : in std_logic_vector (63 downto 0) := (others => '0')
        );
 end component;
 
 component med_ecp3_sfp_sync_up is
-  generic(
-    SERDES_NUM : integer range 0 to 3 := 0;
---     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
-    IS_SYNC_SLAVE   : integer := c_YES       --select slave mode
-    );
-  port(
-    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    --Internal Connection TX
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic := '0';
-    --Internal Connection RX
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-    MED_DATAREADY_OUT  : out std_logic := '0';
-    MED_READ_IN        : in  std_logic;
-    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
-    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
-    
-    --Sync operation
-    RX_DLM             : out std_logic := '0';
-    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-    TX_DLM             : in  std_logic := '0';
-    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-               TX_DLM_INIT                             : in std_logic := '0';  --PL!
+       generic(
+                               SERDES_NUM              : integer range 0 to 3 := 0;
+                               IS_SYNC_SLAVE   : integer := c_YES --select slave mode
+               );
+       port(
+               CLK                                             : in std_logic; -- _internal_ 200 MHz reference clock
+               SYSCLK                                  : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+               RESET                                           : in std_logic; -- synchronous reset
+               CLEAR                                           : in std_logic; -- asynchronous reset
+               --Internal Connection TX
+               MED_DATA_IN                             : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+               MED_PACKET_NUM_IN               : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+               MED_DATAREADY_IN                : in std_logic;
+               MED_READ_OUT                    : out std_logic := '0';
+               --Internal Connection RX
+               MED_DATA_OUT                    : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+               MED_PACKET_NUM_OUT      : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+               MED_DATAREADY_OUT               : out std_logic := '0';
+               MED_READ_IN                             : in std_logic;
+               CLK_RX_HALF_OUT         : out std_logic := '0'; --received 100 MHz
+               CLK_RX_FULL_OUT         : out std_logic := '0'; --received 200 MHz
+
+               --Sync operation
+               RX_DLM                                  : out std_logic := '0';
+               RX_DLM_WORD                             : out std_logic_vector(7 downto 0) := x"00";
+               TX_DLM                                  : in std_logic := '0';
+               TX_DLM_WORD                             : in std_logic_vector(7 downto 0) := x"00";
+               TX_DLM_PREVIEW_IN               : in std_logic := '0'; --PL!
                LINK_PHASE_OUT                  : out   std_logic := '0';       --PL!
 
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;  --not used
-    SD_REFCLK_N_IN     : in  std_logic;  --not used
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
-   );
+               --SFP Connection
+               SD_RXD_P_IN                             : in std_logic;
+               SD_RXD_N_IN                             : in std_logic;
+               SD_TXD_P_OUT                    : out std_logic;
+               SD_TXD_N_OUT                    : out std_logic;
+               SD_REFCLK_P_IN                  : in std_logic; --not used
+               SD_REFCLK_N_IN                  : in std_logic; --not used
+               SD_PRSNT_N_IN                   : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+               SD_LOS_IN                               : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+               SD_TXDIS_OUT                    : out std_logic := '0'; -- SFP disable
+               --Control Interface
+               SCI_DATA_IN                             : in std_logic_vector(7 downto 0) := (others => '0');
+               SCI_DATA_OUT                    : out std_logic_vector(7 downto 0) := (others => '0');
+               SCI_ADDR                                        : in std_logic_vector(8 downto 0) := (others => '0');
+               SCI_READ                                        : in std_logic := '0';
+               SCI_WRITE                               : in std_logic := '0';
+               SCI_ACK                                 : out std_logic := '0';
+               SCI_NACK                                        : out std_logic := '0';
+               -- Status and control port
+               STAT_OP                                 : out std_logic_vector (15 downto 0);
+               CTRL_OP                                 : in std_logic_vector (15 downto 0) := (others => '0');
+               STAT_DEBUG                              : out std_logic_vector (63 downto 0);
+               CTRL_DEBUG                              : in std_logic_vector (63 downto 0) := (others => '0')
+       );
 end component;
 \r
 component soda_tx_control
-  port(
-    CLK_200                                                                    : in  std_logic;
-    CLK_100                                                                    : in  std_logic;
-    RESET_IN                                                           : in  std_logic;
+ port(
+ CLK_200                                                                       : in std_logic;
+ CLK_100                                                                       : in std_logic;
+ RESET_IN                                                              : in std_logic;
 
-    TX_DATA_IN                                                         : in  std_logic_vector(15 downto 0);
-    TX_PACKET_NUMBER_IN                                        : in  std_logic_vector(2 downto 0);
-    TX_WRITE_IN                                                        : in  std_logic;
-    TX_READ_OUT                                                        : out std_logic;
+ TX_DATA_IN                                                            : in std_logic_vector(15 downto 0);
+ TX_PACKET_NUMBER_IN                                   : in std_logic_vector(2 downto 0);
+ TX_WRITE_IN                                                   : in std_logic;
+ TX_READ_OUT                                                   : out std_logic;
 
-    TX_DATA_OUT                                                        : out std_logic_vector( 7 downto 0);
-    TX_K_OUT                                                           : out std_logic;
+ TX_DATA_OUT                                                   : out std_logic_vector( 7 downto 0);
+ TX_K_OUT                                                              : out std_logic;
 
-    REQUEST_RETRANSMIT_IN                              : in  std_logic := '0';
-    REQUEST_POSITION_IN                                        : in  std_logic_vector( 7 downto 0) := (others => '0');
+ REQUEST_RETRANSMIT_IN                         : in std_logic := '0';
+ REQUEST_POSITION_IN                                   : in std_logic_vector( 7 downto 0) := (others => '0');
 
-    START_RETRANSMIT_IN                                        : in  std_logic := '0';
-    START_POSITION_IN                                  : in  std_logic_vector( 7 downto 0) := (others => '0');
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    TX_DLM_PREVIEW_IN                                  : in  std_logic := '0';
-    SEND_DLM                                                           : in  std_logic := '0';
-    SEND_DLM_WORD                                                      : in  std_logic_vector( 7 downto 0) := (others => '0');
-    
-    SEND_LINK_RESET_IN                                 : in  std_logic := '0';
-    TX_ALLOW_IN                                                        : in  std_logic := '0';
-    RX_ALLOW_IN                                                        : in  std_logic := '0';
+ START_RETRANSMIT_IN                                   : in std_logic := '0';
+ START_POSITION_IN                                     : in std_logic_vector( 7 downto 0) := (others => '0');
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+ TX_DLM_PREVIEW_IN                                     : in std_logic := '0';
+ SEND_DLM                                                              : in std_logic := '0';
+ SEND_DLM_WORD                                                 : in std_logic_vector( 7 downto 0) := (others => '0');
+ 
+ SEND_LINK_RESET_IN                                    : in std_logic := '0';
+ TX_ALLOW_IN                                                   : in std_logic := '0';
+ RX_ALLOW_IN                                                   : in std_logic := '0';
         LINK_PHASE_OUT                                         : out std_logic := '0';
 
-    DEBUG_OUT                                                          : out std_logic_vector(31 downto 0);
-    STAT_REG_OUT                                                       : out std_logic_vector(31 downto 0)
-    );
+ DEBUG_OUT                                                             : out std_logic_vector(31 downto 0);
+ STAT_REG_OUT                                                  : out std_logic_vector(31 downto 0)
+ );
 end component;\r
 \r
 component soda_cmd_window_generator