changed generic COMPILE_VERSION from 16 to 64 bit

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index 6ff5e2a1c2164e983e92277a1e2c4e3386fdbb2d..ba5d9c0b6e8f05935fa49cbb5db4d434b13542be 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -43,7 +43,7 @@ entity trb_net16_endpoint_hades_full is
     REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
     REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_VERSION        : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;

diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd
index 894e0cdc4e38263fd45f2bca515c6e87c16584bc..a1e4fd4dc4729407d26887da3800d4975314e14e 100644 (file)
--- a/trb_net16_endpoint_hades_full_handler.vhd
+++ b/trb_net16_endpoint_hades_full_handler.vhd
@@ -25,7 +25,7 @@ entity trb_net16_endpoint_hades_full_handler is
     REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
     REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_VERSION        : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;

diff --git a/trb_net16_endpoint_sctrl.vhd b/trb_net16_endpoint_sctrl.vhd
index d1ffe614e1a7838e725aaf71d4ddaee53370be56..cf987c573be8e182012a02e17ee15eabb191de76 100644 (file)
--- a/trb_net16_endpoint_sctrl.vhd
+++ b/trb_net16_endpoint_sctrl.vhd
@@ -34,7 +34,7 @@ entity trb_net16_endpoint_sctrl is
     REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
     REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_VERSION        : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 57f29909515100535517763818092a12bf70527c..df6aa64824c6756eb90369d4e1cdc3f157390431 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -28,7 +28,7 @@ entity trb_net16_hub_base is
                                          x"00000000_00000000_00007077_00000000" &
                                          x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index 44ea5593b578d81241bd099ab6cad1535104f672..37cf57be35382d892197333ff18628d386476d95 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -101,7 +101,7 @@ package trb_net16_hub_func is
                                          x"00000000_00000000_000050FF_00000000" &
                                          x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0)  := x"0001";
     USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
@@ -206,7 +206,7 @@ component trb_net16_hub_streaming_port is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -602,7 +602,7 @@ component trb_net16_hub_streaming_port_sctrl is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -712,7 +712,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F3C0";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"9000CE00";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0005";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";

diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd
index e8c8a8fe2606b25182751c1484b45907be2e761f..073aab08e3d9bd7f401ddd373028a1a923a8fc37 100644 (file)
--- a/trb_net16_hub_streaming_port.vhd
+++ b/trb_net16_hub_streaming_port.vhd
@@ -22,7 +22,7 @@ entity trb_net16_hub_streaming_port is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";

diff --git a/trb_net16_hub_streaming_port_sctrl.vhd b/trb_net16_hub_streaming_port_sctrl.vhd
index 64389365b45573e9b439bdad8253480d6ece2113..2b272884a3b8f687af3f395bf444b7ab361e47b8 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl.vhd
+++ b/trb_net16_hub_streaming_port_sctrl.vhd
@@ -35,7 +35,7 @@ entity trb_net16_hub_streaming_port_sctrl is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index f21ace2e83f61b28a6dca5d95934a711a995e8ae..3620663de20f7e38cd52aa451b9478cf349acbdf 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -51,7 +51,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F3C0";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"9000CE00";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0005";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 81837df07d0455ebacf50fbffd58150cb609d4c0..779375bd26d44a97721a05eddaf748e38f909d96 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -26,7 +26,7 @@ entity trb_net16_regIO is
     INIT_BOARD_INFO  : std_logic_vector(31 downto 0) := x"1111_2222";
     INIT_ENDPOINT_ID : std_logic_vector(15 downto 0)  := x"0001";
     COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";  --not used any more!
-    COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
+    COMPILE_VERSION    : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
     CLOCK_FREQ         : integer range 1 to 200 := 100 --MHz
     );
@@ -931,12 +931,12 @@ begin
     generic map(
       INIT0 => COMPILE_TIME_LIB(15 downto 0),
       INIT1 => COMPILE_TIME_LIB(31 downto 16),
-      INIT2 => COMPILE_VERSION,
-      INIT3 => (others => '0'),
+      INIT2 => COMPILE_VERSION(15 downto 0),
+      INIT3 => COMPILE_VERSION(31 downto 16),
       INIT4 => HARDWARE_VERSION(15 downto 0),
       INIT5 => HARDWARE_VERSION(31 downto 16),
-      INIT6 => (others => '0'),
-      INIT7 => (others => '0')
+      INIT6 => COMPILE_VERSION(47 downto 32),
+      INIT7 => COMPILE_VERSION(63 downto 48)
       )
     port map(
       CLK     => CLK,

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 8e5d6c5609a773d5104f1bce4a8b5aebbd5868d9..60d623aa536c1df2b59e0512d0ed63e45206e028 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -615,7 +615,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)          := x"1111_2222";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)          := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)          := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0)          := x"0001";\r
+      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)          := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)          := x"12345678";\r
       REGIO_USE_1WIRE_INTERFACE : integer                                := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES            := c_NO;\r
@@ -746,7 +746,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)      := x"1111_2222";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)      := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)      := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0)      := x"0001";\r
+      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)      := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)      := x"12345678";\r
       REGIO_USE_1WIRE_INTERFACE : integer                            := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES        := c_NO;\r
@@ -886,7 +886,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)          := x"0000_0000";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)          := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)          := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0)          := x"0001";\r
+      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)          := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)          := x"50000000";\r
       REGIO_USE_1WIRE_INTERFACE : integer                                := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES            := c_NO;\r
@@ -2554,7 +2554,7 @@ package trb_net_components is
       INIT_BOARD_INFO   : std_logic_vector(31 downto 0)          := x"1111_2222";\r
       INIT_ENDPOINT_ID  : std_logic_vector(15 downto 0)          := x"0001";\r
       COMPILE_TIME      : std_logic_vector(31 downto 0)          := x"00000000";\r
-      COMPILE_VERSION   : std_logic_vector(15 downto 0)          := x"0001";\r
+      COMPILE_VERSION   : std_logic_vector(63 downto 0)          := (others => '0');\r
       HARDWARE_VERSION  : std_logic_vector(31 downto 0)          := x"12345678";\r
       CLOCK_FREQ        : integer range 1 to 200                 := 100  --MHz\r
       );\r