*** empty log message ***

diff --git a/trb_net_ram.vhd b/basics/ram.vhd
similarity index 89%
rename from trb_net_ram.vhd
rename to basics/ram.vhd
index cbc2abd454ab8c430ec91bf598ca6d7b10a5813c..308ab3c63e8ae8cfeb5bc12f80921ffe8c7e436f 100644 (file)
--- a/trb_net_ram.vhd
+++ b/basics/ram.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_ram is
+entity ram is
   generic(
     depth : integer := 5;
     width : integer := 32
@@ -20,12 +20,12 @@ entity trb_net_ram is
     );
 end entity;
 
-architecture trb_net_ram_arch of trb_net_ram is
+architecture ram_arch of ram is
   type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
        SIGNAL ram : ram_t;
 
 begin
-  process(CLK) 
+  process(CLK)
     begin
       if rising_edge(CLK) then
         if wr = '1' then

diff --git a/trb_net_ram_16x16_dp.vhd b/basics/ram_16x16_dp.vhd
similarity index 94%
rename from trb_net_ram_16x16_dp.vhd
rename to basics/ram_16x16_dp.vhd
index 2485d5f57618ea3d89e5cb495fb2cb5d93257419..2bf97c46e16662f7a46ababd13e71a59f53100c6 100644 (file)
--- a/trb_net_ram_16x16_dp.vhd
+++ b/basics/ram_16x16_dp.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_ram_16x16_dp is
+entity ram_16x16_dp is
   generic(
     INIT0 : std_logic_vector(15 downto 0) := x"0000";
     INIT1 : std_logic_vector(15 downto 0) := x"0000";
@@ -36,7 +36,7 @@ entity trb_net_ram_16x16_dp is
     );
 end entity;
 
-architecture trb_net_ram_16x16_dp_arch of trb_net_ram_16x16_dp is
+architecture ram_16x16_dp_arch of ram_16x16_dp is
   type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
   SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7,
                          INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF);

diff --git a/trb_net_ram_16x8_dp.vhd b/basics/ram_16x8_dp.vhd
similarity index 92%
rename from trb_net_ram_16x8_dp.vhd
rename to basics/ram_16x8_dp.vhd
index 6cc106def299a2209da0fa21d10bb0935f77e797..704831a0672f7b6d7b2c526ae06509ab85d27339 100644 (file)
--- a/trb_net_ram_16x8_dp.vhd
+++ b/basics/ram_16x8_dp.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_ram_16x8_dp is
+entity ram_16x8_dp is
   generic(
     INIT0 : std_logic_vector(15 downto 0) := x"0000";
     INIT1 : std_logic_vector(15 downto 0) := x"0000";
@@ -28,7 +28,7 @@ entity trb_net_ram_16x8_dp is
     );
 end entity;
 
-architecture trb_net_ram_16x8_dp_arch of trb_net_ram_16x8_dp is
+architecture ram_16x8_dp_arch of ram_16x8_dp is
   type ram_t is array(0 to 7) of std_logic_vector(15 downto 0);
   SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7);
 begin

diff --git a/trb_net_ram_dp.vhd b/basics/ram_dp.vhd
similarity index 100%
rename from trb_net_ram_dp.vhd
rename to basics/ram_dp.vhd

diff --git a/trb_net_ram_true_dp.vhd b/basics/ram_true_dp.vhd
similarity index 90%
rename from trb_net_ram_true_dp.vhd
rename to basics/ram_true_dp.vhd
index 169e158b0bba8745cbf0f980bdc1ef6efc7f4487..48ca545940b044bc1aff37c2ac85a37ea49b2b52 100644 (file)
--- a/trb_net_ram_true_dp.vhd
+++ b/basics/ram_true_dp.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_ram_true_dp is
+entity ram_true_dp is
   generic(
     depth : integer := 5;
     width : integer := 32
@@ -24,12 +24,12 @@ entity trb_net_ram_true_dp is
     );
 end entity;
 
-architecture trb_net_ram_true_dp_arch of trb_net_ram_true_dp is
+architecture ram_true_dp_arch of ram_true_dp is
   type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
   SIGNAL ram : ram_t;
 
 begin
-  process(CLK) 
+  process(CLK)
     begin
       if rising_edge(CLK) then
         if wr1 = '1' then

diff --git a/trb_net_rom_16x16.vhd b/basics/rom_16x16.vhd
similarity index 94%
rename from trb_net_rom_16x16.vhd
rename to basics/rom_16x16.vhd
index 2d83453de2735573ac74e9a4bf2fdd824cd72110..c3ac79b58ec60c5b98e38d258bd4b5b61f401b08 100644 (file)
--- a/trb_net_rom_16x16.vhd
+++ b/basics/rom_16x16.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_rom_16x16 is
+entity rom_16x16 is
   generic(
     INIT0 : std_logic_vector(15 downto 0) := x"12A0";
     INIT1 : std_logic_vector(15 downto 0) := x"23b1";
@@ -32,7 +32,7 @@ entity trb_net_rom_16x16 is
     );
 end entity;
 
-architecture trb_net_rom_16x16_arch of trb_net_rom_16x16 is
+architecture rom_16x16_arch of rom_16x16 is
   type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
   SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7, INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF);
 begin

diff --git a/trb_net_rom_16x8.vhd b/basics/rom_16x8.vhd
similarity index 91%
rename from trb_net_rom_16x8.vhd
rename to basics/rom_16x8.vhd
index c53a8d9d731cce578bb0d260dd640e9d5bf8f14a..f664fe84950b5950a6af8cb86ac714c7bbd8c48b 100644 (file)
--- a/trb_net_rom_16x8.vhd
+++ b/basics/rom_16x8.vhd
@@ -6,7 +6,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
 
-entity trb_net_rom_16x8 is
+entity rom_16x8 is
   generic(
     INIT0 : std_logic_vector(15 downto 0) := x"12A0";
     INIT1 : std_logic_vector(15 downto 0) := x"23b1";
@@ -24,7 +24,7 @@ entity trb_net_rom_16x8 is
     );
 end entity;
 
-architecture trb_net_rom_16x8_arch of trb_net_rom_16x8 is
+architecture rom_16x8_arch of rom_16x8 is
   type ram_t is array(0 to 7) of std_logic_vector(15 downto 0);
   SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7);
 begin

diff --git a/etrax_interface.vhd b/etrax_interface.vhd
new file mode 100644 (file)
index 0000000..5cd8049
--- /dev/null
+++ b/etrax_interface.vhd
@@ -0,0 +1,287 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+entity etrax_interface is
+  generic(
+    STATUS_REGISTERS  : integer := 4;
+    CONTROL_REGISTERS : integer := 4
+    );
+  port (
+    CLK                     : in    std_logic;
+    RESET                   : in    std_logic;
+    --Connection to Etrax
+    ETRAX_DATA_BUS_B        : out std_logic_vector(17 downto 0);
+    ETRAX_DATA_BUS_C        : inout    std_logic_vector(17 downto 0);
+    ETRAX_BUS_BUSY          : out   std_logic;
+    ETRAX_IS_READY_TO_READ  : out    std_logic;
+    --Connection to internal FPGA logic (all addresses above 0x100)
+    INTERNAL_DATA_OUT       : out std_logic_vector(31 downto 0);
+    INTERNAL_DATA_IN        : in  std_logic_vector(31 downto 0);
+    INTERNAL_READ_OUT       : out std_logic;
+    INTERNAL_WRITE_OUT      : out std_logic;
+    INTERNAL_DATAREADY_IN   : in  std_logic;
+    INTERNAL_ADDRESS_OUT    : out std_logic_vector(15 downto 0);
+    --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)
+    FPGA_REGISTER_IN        : in    std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
+    FPGA_REGISTER_OUT       : out   std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
+    --Reset FPGA via Etrax
+    EXTERNAL_RESET          : out   std_logic
+    );
+end etrax_interface;
+architecture etrax_interface of etrax_interface is
+
+  component signal_sync is
+    generic(
+      WIDTH : integer := 2;     --
+      DEPTH : integer := 1
+      );
+    port(
+      RESET    : in  std_logic; --Reset is neceessary to avoid optimization to shift register
+      CLK0     : in  std_logic;                          --clock for first FF
+      CLK1     : in  std_logic;                          --Clock for other FF
+      D_IN     : in  std_logic_vector(WIDTH-1 downto 0); --Data input
+      D_OUT    : out std_logic_vector(WIDTH-1 downto 0)  --Data output
+      );
+  end component;
+
+  type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_ADDRESS_1, SAVE_ADDRESS_2, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER );
+  signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate  : ETRAX_RW_STATE_MACHINE;
+
+  signal etrax_trigger_pulse : std_logic;
+  signal saved_rw_mode : std_logic_vector(17 downto 0);
+  signal saved_address : std_logic_vector (15 downto 0);
+  signal saved_data : std_logic_vector(31 downto 0);
+  signal saved_data_fpga : std_logic_vector(31 downto 0);
+
+  signal read_cycle : std_logic;
+  signal write_cycle : std_logic;
+
+  signal etrax_is_ready_to_read_i : std_logic;
+  signal internal_reset_i : std_logic;
+  signal communication_state : std_logic_vector(3 downto 0);
+  signal buf_FPGA_REGISTER_OUT : std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
+  signal reg_BUSC, last_BUSC : std_logic_vector(1 downto 0);
+
+begin
+  MAKE_RESET: process (CLK)
+  begin
+    if rising_edge(CLK) then
+      if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+        internal_reset_i <= '1';
+      elsif ETRAX_DATA_BUS_C(16)='0' and ETRAX_DATA_BUS_C(17)='0' then
+        internal_reset_i <= '0';
+      else
+        internal_reset_i <= '0';
+      end if;
+    end if;
+  end process MAKE_RESET;
+
+  BUSC_SYNC : signal_sync
+    port map(
+      RESET => RESET,
+      CLK0 => CLK,
+      CLK1 => CLK,
+      D_IN => ETRAX_DATA_BUS_C(17 downto 16),
+      D_OUT => reg_BUSC
+      );
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        last_BUSC <= reg_BUSC;
+        etrax_trigger_pulse <= '0';
+        etrax_is_ready_to_read_i <= '0';
+        if (not last_BUSC(0) and reg_BUSC(0)) = '1' then
+          etrax_trigger_pulse <= '1';
+        end if;
+        if (not last_BUSC(1) and reg_BUSC(1)) = '1' then
+          etrax_is_ready_to_read_i <= '1';
+        end if;
+      end if;
+    end process;
+
+
+  EXTERNAL_RESET <= internal_reset_i;
+  ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1';
+  ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i;
+
+  read_cycle  <= saved_rw_mode(15);
+  write_cycle <= not saved_rw_mode(15);
+
+
+  ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK)
+  begin
+    if rising_edge(CLK) then
+      if internal_reset_i = '1' then
+        ETRAX_RW_STATE_currentstate <= IDLE;
+      else
+        ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
+      end if;
+    end if;
+  end process ETRAX_FPGA_COMUNICATION_CLOCK;
+
+  ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse,
+                  saved_rw_mode(15), read_cycle, write_cycle,
+                  INTERNAL_DATAREADY_IN, saved_address)
+  begin
+    communication_state <= x"1";
+    ETRAX_RW_STATE_nextstate <= ETRAX_RW_STATE_currentstate;
+    case ETRAX_RW_STATE_currentstate is
+      when IDLE         =>
+        communication_state <= x"1";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= SAVE_ADDRESS_1;
+        end if;
+
+      when SAVE_ADDRESS_1  =>
+        communication_state <= x"2";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2;
+        end if;
+
+      when SAVE_ADDRESS_2  =>
+        communication_state <= x"3";
+          if etrax_trigger_pulse = '1' then
+            if read_cycle = '1' then
+              ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
+            else
+              ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
+            end if;
+          end if;
+
+      when SAVE_DATA_1     =>
+        communication_state <= x"4";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= SAVE_DATA_2;
+        end if;
+
+      when SAVE_DATA_2     =>
+        communication_state <= x"5";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= SEND_EXTERNAL_TRIGGER;
+        end if;
+
+      when SEND_EXTERNAL_TRIGGER =>
+        ETRAX_RW_STATE_nextstate   <= WAIT_FOR_DATA;
+
+      when WAIT_FOR_DATA =>
+        communication_state <= x"6";
+        if write_cycle = '1' then
+          ETRAX_RW_STATE_nextstate     <= SEND_VALID;
+        elsif INTERNAL_DATAREADY_IN = '1' or saved_address(15 downto 8) = 0 then
+          ETRAX_RW_STATE_nextstate     <= SAVING_EXTERNAL_DATA;
+        end if;
+
+      when SEND_VALID =>
+        communication_state <= x"7";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= IDLE;
+        end if;
+
+      when SAVING_EXTERNAL_DATA =>
+        ETRAX_RW_STATE_nextstate     <= SEND_DATA_1;
+
+      when SEND_DATA_1     =>
+        communication_state <= x"8";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= SEND_ZERO;
+        end if;
+
+      when SEND_ZERO =>
+        communication_state <= x"a";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= SEND_DATA_2;
+        end if;
+
+      when SEND_DATA_2     =>
+        communication_state <= x"9";
+        if etrax_trigger_pulse = '1' then
+          ETRAX_RW_STATE_nextstate   <= IDLE;
+        end if;
+    end case;
+  end process ETRAX_FPGA_COMUNICATION;
+
+  REGISTER_ETRAX_BUS: process (CLK)
+  begin
+    if rising_edge(CLK) then
+      if internal_reset_i = '1' then
+        saved_rw_mode <= (others => '0');
+        saved_address <= (others => '0');
+        saved_data <= (others => '0');
+      elsif ETRAX_RW_STATE_currentstate = IDLE  and etrax_trigger_pulse = '1' then
+        saved_rw_mode <= ETRAX_DATA_BUS_C;
+      elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2  and etrax_trigger_pulse = '1' then
+        saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+      elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1  and etrax_trigger_pulse = '1' then
+        saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+      elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2  and etrax_trigger_pulse = '1' then
+        saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+      end if;
+    end if;
+  end process REGISTER_ETRAX_BUS;
+
+
+  INTERNAL_ADDRESS_OUT <= saved_address;
+  INTERNAL_DATA_OUT    <= saved_data;
+
+  INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(15 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0';
+  INTERNAL_READ_OUT  <= '1' when read_cycle = '1' and saved_address(15 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0';
+
+  FPGA_REGISTER_OUT <= buf_FPGA_REGISTER_OUT;
+
+  ETRAX_DATA_BUS_CHOOSE : process (CLK)
+    begin
+      if rising_edge(CLK) then
+        if internal_reset_i = '1' then
+          ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";--(others => 'Z');
+        elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
+          ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);--
+          ETRAX_DATA_BUS_B(16) <= '1';
+        elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
+          ETRAX_DATA_BUS_B(15 downto 0) <=  saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);--
+          ETRAX_DATA_BUS_B(16) <= '1';
+        else
+          ETRAX_DATA_BUS_B(16 downto 0) <=  "0"& x"0000";
+        end if;
+      end if;
+    end process ETRAX_DATA_BUS_CHOOSE;
+
+   ETRAX_DATA_BUS_B(17) <= '1';
+   ETRAX_DATA_BUS_C     <= (others => 'Z');
+
+  DATA_SOURCE_SELECT : process (CLK)
+    variable stat_num : integer range 0 to STATUS_REGISTERS-1;
+    variable ctrl_num : integer range 0 to CONTROL_REGISTERS-1;
+    begin
+      if rising_edge(CLK) then
+        stat_num := conv_integer(saved_address(3 downto 0));
+        ctrl_num := conv_integer(saved_address(3 downto 0));
+        case saved_rw_mode(7 downto 0) is
+          when x"00"        =>
+            if saved_rw_mode(15) = '1' then
+              if saved_address(15 downto 8) = 0 then
+                if saved_address(7 downto 4) = 0   then  --status regs
+                  saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32);
+                elsif saved_address(4) = '1' then
+                  saved_data_fpga <= buf_FPGA_REGISTER_OUT((ctrl_num)*32+31 downto (ctrl_num)*32);
+                else
+                  saved_data_fpga <= (others => '0');
+                end if;
+              elsif INTERNAL_DATAREADY_IN = '1' then
+                saved_data_fpga <= INTERNAL_DATA_IN;
+              end if;
+            elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
+              buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
+            end if;
+          when others       =>
+            saved_data_fpga   <= x"deadface";
+        end case;
+      end if;
+    end process DATA_SOURCE_SELECT;
+end architecture;

diff --git a/optical_link/f_divider.vhd b/optical_link/f_divider.vhd
index 7366e7e03586ba90a36db6ad4e2612fd30b33bfa..50133b99e0e2f3c2f1e43359da8e9860be17ad17 100644 (file)
--- a/optical_link/f_divider.vhd
+++ b/optical_link/f_divider.vhd
@@ -35,9 +35,9 @@ architecture arch_f_divider of f_divider is
   end How_many_bits;
 
 
-  --+          
+  --+
   --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können?                                                  |
-  --+          
+  --+
   constant c_counter_width : integer := How_many_Bits(cnt - 2);
 
   --+                                   ---------------------------------------------------------------------------------------------+
@@ -115,6 +115,7 @@ begin  -- arch_edge_to_pulse
 
   fsm_comb : process (current_state, signal_sync)
   begin  -- process fsm_comb
+    pulse        <= '0';
     case current_state is
       when idle         =>
         pulse        <= '0';
@@ -167,7 +168,7 @@ package support is
       signal_in : in  std_logic;
       pulse     : out std_logic);
   end component;
-  
+
 
 end support;
 

diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd
index 5afc1a2a1eb3ce4298271605c6aa86bccf96ee62..f671dd8d075ec58c5f39de13764ffd3be59519e3 100644 (file)
--- a/testbench/trb_net16_dummy_apl.vhd
+++ b/testbench/trb_net16_dummy_apl.vhd
@@ -64,10 +64,10 @@ begin
 --   address <= x"0008";
 --   reghigh <= x"DEAD";
 --   reglow  <= x"AFFE";
-  address <= x"0001"; --x"0001";
+  address <= x"5E1D"; --x"0001";
   reghigh <= x"0022";
   reglow  <= xor_all(APL_DATA_IN) & "000000000000011";
-  APL_DTYPE_OUT <= x"8";
+  APL_DTYPE_OUT <= x"F";
   APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
 
   process(current_state)

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index 623e5ab5249dcbd58ecc7824854f848faa88fd1d..2124823490d65b498dd6e94d007de8b6ef040ef9 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -36,7 +36,7 @@ entity trb_net16_addresses is
 end entity;
 
 architecture trb_net16_addresses_arch of trb_net16_addresses is
-  component trb_net_ram_16x16_dp is
+  component ram_16x16_dp is
     generic(
       INIT0 : std_logic_vector(15 downto 0) := x"0000";
       INIT1 : std_logic_vector(15 downto 0) := x"0000";
@@ -239,7 +239,7 @@ begin
       end if;
     end process;
 
-  STAT_RAM : trb_net_ram_16x16_dp
+  STAT_RAM : ram_16x16_dp
     generic map(
       INIT0 => INIT_UNIQUE_ID(15 downto 0),
       INIT1 => INIT_UNIQUE_ID(31 downto 16),

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 473ae7d17f4fde0aaaef8a42d002dec4421155df..2767db87af9beea3bca8aafe27bd544265ab793c 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -129,7 +129,7 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
       );
   end component;
 
-  component trb_net_rom_16x8 is
+  component rom_16x8 is
     generic(
       INIT0 : std_logic_vector(15 downto 0) := x"0000";
       INIT1 : std_logic_vector(15 downto 0) := x"0000";
@@ -689,7 +689,7 @@ begin
     end process;
 
 
-  board_rom : trb_net_rom_16x8
+  board_rom : rom_16x8
     generic map(
       INIT0 => COMPILE_TIME(15 downto 0),
       INIT1 => COMPILE_TIME(31 downto 16),

diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd
deleted file mode 100644 (file)
index e30c2c9..0000000
--- a/trb_net_fifo.vhd
+++ /dev/null
@@ -1,36 +0,0 @@
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo
-
-library ieee;
-use ieee.std_logic_1164.all;
-USE ieee.std_logic_signed.ALL;
-USE ieee.std_logic_arith.ALL;
-library work;
-use work.trb_net_std.all;
-
-
-entity trb_net_fifo is
-  
-  generic (
-   WIDTH : integer := 18;      -- FIFO word width
-   DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
-   FORCE_LUT : integer range 0 to 1 := 0 --don't allow use of BlockRAM
-   );
-  port (
-    CLK    : in std_logic;             
-    RESET  : in std_logic;     
-    CLK_EN : in std_logic;
-
-    DATA_IN         : in  std_logic_vector(WIDTH - 1 downto 0);  -- Input data
-    WRITE_ENABLE_IN : in  std_logic;           
-    DATA_OUT        : out std_logic_vector(WIDTH - 1 downto 0);  -- Output data
-       --output data MUST BE 0 if no data is available
-    READ_ENABLE_IN  : in  std_logic; 
-    FULL_OUT        : out std_logic;   -- Full Flag
-    EMPTY_OUT       : out std_logic;
-    DEPTH_OUT       : out std_logic_vector(7 downto 0)
-    );
-
-end trb_net_fifo;
-
-
-

diff --git a/trb_net_fifo_16bit_bram_dualport.vhd b/trb_net_fifo_16bit_bram_dualport.vhd
deleted file mode 100644 (file)
index f4205e2..0000000
--- a/trb_net_fifo_16bit_bram_dualport.vhd
+++ /dev/null
@@ -1,28 +0,0 @@
---this fifo uses standard read behaviour: data is available one clock cycle after read was high.
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-library unisim;
-use UNISIM.VComponents.all;
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_fifo_16bit_bram_dualport is
-   generic(
-     USE_STATUS_FLAGS : integer  := c_YES
-     );
-   port (
-     read_clock_in:   IN  std_logic;
-     write_clock_in:  IN  std_logic;
-     read_enable_in:  IN  std_logic;
-     write_enable_in: IN  std_logic;
-     fifo_gsr_in:     IN  std_logic;
-     write_data_in:   IN  std_logic_vector(17 downto 0);
-     read_data_out:   OUT std_logic_vector(17 downto 0);
-     full_out:        OUT std_logic;
-     empty_out:       OUT std_logic;
-     fifostatus_out:  OUT std_logic_vector(3 downto 0) --counter for 1/16th of fifo
-    ); 
-end entity trb_net_fifo_16bit_bram_dualport;
\ No newline at end of file