signal debug_status : std_logic_vector(31 downto 0);
signal additional_reg_i : std_logic_vector(31 downto 0) := x"00000000";
signal control_reg_i : std_logic_vector(15 downto 0);
+signal dtrout : std_logic_vector(7 downto 0) := x"00"; --temperature in ECP5
+
+
+attribute syn_black_box: boolean ;
+component dtr
+ generic (
+ dtr_temp : integer := 25);
+ port (
+ startpulse : in std_logic := 'x';
+ dtrout7,dtrout6,dtrout5,dtrout4,dtrout3,dtrout2,dtrout1,dtrout0 : out std_logic := 'x'
+ );
+end component;
+attribute syn_black_box of dtr : component is true;
+
begin
busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
else
busctrl_tx.data(control_reg_i'left downto 0) <= control_reg_i;
+ busctrl_tx.data(31 downto 24) <= dtrout;
end if;
busctrl_tx.ack <= '1';
elsif busctrl_rx.write = '1' then
ADDITIONAL_REG <= additional_reg_i;
+---------------------------------------------------------------------------
+-- ECP5 Temperature Diode
+---------------------------------------------------------------------------
+gen_temperature : if FPGA_TYPE = 5 generate
+ THE_DTR : DTR
+ port map (
+ STARTPULSE => busctrl_tx.ack,
+ DTROUT0 => dtrout(0),
+ DTROUT1 => dtrout(1),
+ DTROUT2 => dtrout(2),
+ DTROUT3 => dtrout(3),
+ DTROUT4 => dtrout(4),
+ DTROUT5 => dtrout(5),
+ DTROUT6 => dtrout(6),
+ DTROUT7 => dtrout(7)
+ );
+end generate;
+
+
---------------------------------------------------------------------------
-- HEADER_IO
---------------------------------------------------------------------------