begin
-<<<<<<< trb_net16_hub_base.vhd
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 2 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
- -- Status and control port
- STAT_GEN : out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_GEN : in std_logic_vector (31 downto 0);
- STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
- );
- end component;
-=======
+
---------------------------------------------------------------------
--Generate various reset signals
---------------------------------------------------------------------
reset_i <= RESET;
end if;
end process;
->>>>>>> 1.57
+
gen_internal_reset : for i in 0 to MII_NUMBER-1 generate
signal waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0);
signal next_waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal reply_adder_input : std_logic_vector(17*16-1 downto 0);
- signal reply_adder_start : std_logic;
- signal reply_adder_overflow : std_logic;
- signal reply_adder_ready : std_logic;
+ signal reply_adder_input : std_logic_vector(17*16-1 downto 0);
+ signal reply_adder_start : std_logic;
+ signal reg_reply_adder_start : std_logic;
+ signal reply_adder_overflow : std_logic;
+ signal reply_adder_ready : std_logic;
signal reply_adder_val_enable : std_logic_vector(17-1 downto 0);
signal reply_adder_result : std_logic_vector(15 downto 0);
signal next_reply_adder_start : std_logic;
signal next_reply_compare_start : std_logic;
- signal reply_compare_start : std_logic;
- signal reply_compare_finished : std_logic;
- signal reply_compare_result : std_logic_vector(17-1 downto 0);
- signal reply_compare_flag : std_logic;
- signal reply_compare_input : std_logic_vector(17-1 downto 0);
+ signal reply_compare_start : std_logic;
+ signal reg_reply_compare_start : std_logic;
+ signal reply_compare_finished : std_logic;
+ signal reply_compare_result : std_logic_vector(17-1 downto 0);
+ signal reply_compare_flag : std_logic;
+ signal reply_compare_input : std_logic_vector(17-1 downto 0);
- signal last_dhdr_addr : std_logic_vector(2 downto 0);
- signal last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
- signal next_last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
+ signal dhdr_addr : std_logic_vector(2 downto 0);
+ signal dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
+ signal next_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
signal current_point_length : unsigned(15 downto 0);
signal start_read_padding : std_logic_vector(POINT_NUMBER-1 downto 0);
PROC_reading_signals : process(CLK)
begin
if rising_edge(CLK) then
- reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i);
- reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i);
+ reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i);
+ reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i);
reg_current_reply_reading_DHDR(i) <= current_reply_reading_DHDR(i);
end if;
end process;
----------------------------------
gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate
hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i);
-
--- (current_reply_reading_HDR(i) and
--- (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or
--- (current_reply_reading_DHDR(i) and
--- (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i)
--- (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2))
--- ));
- --read normal HDR_F0 to DHDR_F1 and DHDR_F2 without read='1'
hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH);
hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0';
wr1 => hdrram_write_enable(i),
a1 => hdrram_address(i*3+2 downto i*3),
din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- a2 => last_dhdr_addr,
- dout2 => next_last_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
+ a2 => dhdr_addr,
+ dout2 => next_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
);
end generate;
- PROC_REG_DHDR_RAM_OUT : process(CLK)
+
+ PROC_dhdr_data_reg : process(CLK)
begin
if rising_edge(CLK) then
- last_dhdr_data <= next_last_dhdr_data;
+ dhdr_data <= next_dhdr_data;
+ if RESET = '1' then
+ reply_adder_start <= '0';
+ reply_compare_start <= '0';
+ else
+ reg_reply_adder_start <= next_reply_adder_start;
+ reg_reply_compare_start <= next_reply_compare_start;
+ reply_adder_start <= reg_reply_adder_start;
+ reply_compare_start <= reg_reply_compare_start;
+ end if;
end if;
end process;
READY_OUT => reply_adder_ready
);
- PROC_LED : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reply_adder_start <= '0';
- reply_compare_start <= '0';
- else
- reply_adder_start <= next_reply_adder_start;
- reply_compare_start <= next_reply_compare_start;
- end if;
- end if;
- end process;
+ reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints);
+ reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0');
- reply_adder_input(POINT_NUMBER*16-1 downto 0) <= last_dhdr_data;
+ reply_adder_input(POINT_NUMBER*16-1 downto 0) <= dhdr_data;
gen_spare_bits : if POINT_NUMBER < 17 generate
reply_adder_input(reply_adder_input'left downto POINT_NUMBER*16) <= (others => '0');
end generate;
else
gen_current_length : for i in 0 to POINT_NUMBER-1 loop
if reply_arbiter_result(i) = '1' then
- current_point_length <= unsigned(last_dhdr_data((i)*c_DATA_WIDTH+c_DATA_WIDTH-1 downto i*c_DATA_WIDTH));
+ current_point_length <= unsigned(dhdr_data((i)*c_DATA_WIDTH+c_DATA_WIDTH-1 downto i*c_DATA_WIDTH));
end if;
end loop;
end if;
process(RESET, send_reply_trm, REPLY_PACKET_NUM_IN, REPLY_DATAREADY_IN, REPLY_DATA_IN, start_read_padding,
saved_reading_padding)
begin
- if RESET = '1' or send_reply_trm = '1' then
- reading_padding <= (others => '0');
- else
- for i in 0 to POINT_NUMBER-1 loop
- if REPLY_DATAREADY_IN(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 and REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM then
- reading_padding(i) <= '0';
- elsif start_read_padding(i) = '1' then
- reading_padding(i) <= '1';
- else
- reading_padding(i) <= saved_reading_padding(i);
- end if;
- end loop;
- end if;
+ for i in 0 to POINT_NUMBER-1 loop
+ if reply_reading_F0(i) = '1' and reg_current_reply_reading_TRM(i) = '1' then
+ --REPLY_DATAREADY_IN(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 and REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM then
+ reading_padding(i) <= '0';
+ elsif start_read_padding(i) = '1' then
+ reading_padding(i) <= '1';
+ else
+ reading_padding(i) <= saved_reading_padding(i);
+ end if;
+ end loop;
end process;
gen_saved_padding : process (CLK)
begin
if rising_edge(CLK) then
- if locked = '0' then
+ if RESET = '1' or send_reply_trm = '1' or locked = '0' then
saved_reading_padding <= (others => '0');
else
saved_reading_padding <= reading_padding;
if RESET = '1' or send_reply_trm = '1' or locked = '0' then
got_trm <= (others => '0');
else
- got_trm <= got_trm or locking_point or (reply_reading_F3 and reg_current_reply_reading_TRM) or not real_activepoints or connection_timed_out;
+ got_trm <= got_trm or locking_point or (reply_reading_F3 and reg_current_reply_reading_TRM)
+ or not real_activepoints or connection_timed_out;
end if;
end if;
end process;
PROC_REG_COMB_DATAREADY : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- last_comb_REPLY_POOL_DATAREADY <= '0';
- else
- last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY;
- end if;
+ last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY;
end if;
end process;
CTRL => (others => '0')
);
- reply_arbiter_reset <= RESET or not locked;
+ reply_arbiter_reset <= RESET or not locked;
reply_arbiter_input <= REPLY_DATAREADY_IN and not current_reply_reading_TRM and current_reply_reading_DHDR and not saved_reading_padding;
-- reply_arbiter_CLK_EN <= not next_point_lock;
REPLY_MUX_reading <= reply_arbiter_result;
end generate;
---Muxed data is ready, when the selected port has data, and this is neither padding, H0 nor termination.
+--Muxed data is ready, when the selected port has data, and this is neither padding, H0, padding nor termination.
--
comb_REPLY_muxed_DATAREADY <= or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not reg_current_reply_reading_trm
and not reply_reading_H0 and not saved_reading_padding)
variable tmp_code, tmp_number, tmp_pack : std_logic;
begin
if rising_edge(CLK) then
- reply_compare_finished <= '0';
+ reply_compare_finished <= reply_compare_finished and not REPLY_POOL_next_read;
tmp_code := '0';
tmp_pack := '1';
tmp_number := '0';
if reply_compare_start = '1' then
- if last_dhdr_addr = "100" then --upper part
+ if dhdr_addr = "100" then --upper part
for i in 0 to POINT_NUMBER-1 loop
- if last_dhdr_data(i*16+12) = '0' and reply_adder_val_enable(i) = '1' then
+ if dhdr_data(i*16+12) = '0' and reply_adder_val_enable(i) = '1' then
tmp_pack := '0';
end if;
- if last_dhdr_data(i*16+7 downto i*16) /= evt_random_code and reply_adder_val_enable(i) = '1' then
+ if dhdr_data(i*16+7 downto i*16) /= evt_random_code and reply_adder_val_enable(i) = '1' then
tmp_code := '1';
end if;
end loop;
enable_packing <= tmp_pack;
evt_code_mismatch <= tmp_code;
reply_compare_finished <= '1';
- elsif last_dhdr_addr = "101" then
+ elsif dhdr_addr = "101" then
for i in 0 to POINT_NUMBER-1 loop
- if last_dhdr_data(i*16+15 downto i*16) /= evt_number and reply_adder_val_enable(i) = '1' then
+ if dhdr_data(i*16+15 downto i*16) /= evt_number and reply_adder_val_enable(i) = '1' then
tmp_number := '1';
end if;
end loop;
comb_REPLY_POOL_DATA <= (others => '0');
next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints
and not (reg_current_reply_reading_DHDR and reply_reading_F2);
- last_dhdr_addr <= "000";
+ dhdr_addr <= "000";
next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints;
next_reply_adder_start <= '0';
- reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints);
- reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0');
reply_arbiter_enable <= '0';
next_reply_compare_start <= '0';
reply_arbiter_CLK_EN <= '0';
end if;
when WAIT_FOR_HDR_DATA => --start writing HDR when first reply is received, stop waiting for length
- last_dhdr_addr <= "010";
+ dhdr_addr <= "010";
case packet_counter is
when c_H0 =>
comb_REPLY_POOL_DATA <= (others => '0');
end case;
when GEN_LENGTH => --now, all HDR are stored, calc sum of HDR lengths
- last_dhdr_addr <= "010";
- comb_REPLY_POOL_DATAREADY <= '0';
+ dhdr_addr <= "010";
next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) - number_of_replies + 2);
- if last_reply_adder_ready = '1' then
- comb_REPLY_POOL_DATA <= reply_adder_final_result;
- comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
- end if;
- if packet_counter = c_F3 then
- last_dhdr_addr <= "100";
- comb_REPLY_POOL_DATA <= "0000" & evt_seqnr & evt_dtype;
- comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
- if REPLY_POOL_next_read = '1' then
- next_state <= CHECK_DHDR;
- end if;
- end if;
+ comb_REPLY_POOL_DATAREADY <= '0';
+
+ case packet_counter is
+ when c_F2 =>
+ comb_REPLY_POOL_DATA <= reply_adder_final_result;
+ comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and last_reply_adder_ready;
+ when c_F3 =>
+ dhdr_addr <= "100";
+ comb_REPLY_POOL_DATA <= "0000" & evt_seqnr & evt_dtype;
+ comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
+ if REPLY_POOL_next_read = '1' then
+ next_state <= CHECK_DHDR;
+ end if;
+ end case;
when CHECK_DHDR =>
comb_REPLY_POOL_DATAREADY <= '0';
case packet_counter is
when c_H0 =>
- last_dhdr_addr <= "100";
- if got_all_DHDR = '1' then
- comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
- end if;
+ comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and got_all_DHDR;
comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_DAT;
comb_REPLY_POOL_DATA(c_DATA_WIDTH-1 downto 3) <= (others => '0');
+ dhdr_addr <= "100";
+ next_reply_compare_start <= REPLY_POOL_next_read and got_all_DHDR;
when c_F0 =>
- last_dhdr_addr <= "100";
- next_reply_compare_start <= '1';
+ dhdr_addr <= "100";
comb_REPLY_POOL_DATA <= "0001" & evt_dtype & evt_random_code;
if reply_compare_finished = '1' then
+ next_reply_compare_start <= REPLY_POOL_next_read;
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
- next_reply_compare_start <= '0';
- last_dhdr_addr <= "101";
+ dhdr_addr <= "101";
end if;
when c_F1 =>
- last_dhdr_addr <= "101";
- next_reply_compare_start <= '1';
+ dhdr_addr <= "101";
comb_REPLY_POOL_DATA <= evt_number;
if reply_compare_finished = '1' then
- next_reply_compare_start <= '0';
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
- last_dhdr_addr <= "110";
+ next_reply_adder_start <= REPLY_POOL_next_read;
+ dhdr_addr <= "110";
end if;
when c_F2 =>
- next_reply_adder_start <= '1';
- last_dhdr_addr <= "110";
+ dhdr_addr <= "110";
next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) + number_of_replies);
if last_reply_adder_ready = '1' then
comb_REPLY_POOL_DATA <= reply_adder_final_result;
if REPLY_POOL_next_read = '1' then
next_state <= SENDING_DATA;
reply_arbiter_CLK_EN <= '1';
- reply_arbiter_CLK_EN <= '1';
reply_arbiter_enable <= '1';
- last_dhdr_addr <= "110";
+ dhdr_addr <= "110";
reply_data_counter_reset <= '1';
end if;
end case;
when SENDING_DATA =>
reply_arbiter_enable <= '1';
- last_dhdr_addr <= "110"; --length
+ dhdr_addr <= "110"; --length
if packet_counter = c_H0 then
-- and not (comb_REPLY_muxed_PACKET_NUM = c_H0 and comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM)
number_of_replies <= to_unsigned(count_ones(expected_replies),5);
expected_replies <= real_activepoints and not locking_point;
reply_adder_final_result <= next_reply_adder_final_result;
- last_reply_adder_ready <= reply_adder_ready;
+ last_reply_adder_ready <= reply_adder_ready or (last_reply_adder_ready and not REPLY_POOL_next_read);
end if;
end if;
end process;
STAT_FSM(8) <= reply_adder_start;
STAT_FSM(9) <= reply_compare_start;
STAT_FSM(12 downto 10)<= packet_counter;
- STAT_FSM(15 downto 13)<= last_dhdr_addr;
+ STAT_FSM(15 downto 13)<= dhdr_addr;
end architecture;
jspc29 / trbnet.git / commitdiff