+++ /dev/null
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
- #SYSCONFIG MCCLK_FREQ = 2.5;
-
- #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
- #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
-LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
-
-
-#################################################################
-# Trigger I/O
-#################################################################
-
-#Trigger from fan-out
-LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-
-
-#################################################################
-# To central FPGA
-#################################################################
-
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-LOCATE COMP "TEST_LINE_0" SITE "A5";
-LOCATE COMP "TEST_LINE_1" SITE "A6";
-LOCATE COMP "TEST_LINE_2" SITE "G8";
-LOCATE COMP "TEST_LINE_3" SITE "F9";
-LOCATE COMP "TEST_LINE_4" SITE "D9";
-LOCATE COMP "TEST_LINE_5" SITE "D10";
-LOCATE COMP "TEST_LINE_6" SITE "F10";
-LOCATE COMP "TEST_LINE_7" SITE "E10";
-LOCATE COMP "TEST_LINE_8" SITE "A8";
-LOCATE COMP "TEST_LINE_9" SITE "B8";
-LOCATE COMP "TEST_LINE_10" SITE "G10";
-LOCATE COMP "TEST_LINE_11" SITE "G9";
-LOCATE COMP "TEST_LINE_12" SITE "C9";
-LOCATE COMP "TEST_LINE_13" SITE "C10";
-LOCATE COMP "TEST_LINE_14" SITE "H10";
-LOCATE COMP "TEST_LINE_15" SITE "H11";
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST;
-
-#################################################################
-# Connection to AddOn
-#################################################################
-#All DQ groups from one bank are grouped.
-#All DQS are inserted in the DQ lines at position 6 and 7
-#DQ 6-9 are shifted to 8-11
-#Order per bank is kept, i.e. adjacent numbers have adjacent pins
-#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
-#even numbers are positive LVDS line, odd numbers are negative LVDS line
-#DQUL can be switched to 1.8V
-
-
-
-# nXyter 1
-
-LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
-LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
-LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
-#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
-
-LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36
-LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42
-LOCATE COMP "NX1_I2C_SCL_INOUT" SITE "R6"; #DQLL1_7 #44
-
-LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74
-LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78
-LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82
-LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86
-LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90
-LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94
-LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89
-
-LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
-LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
-LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
-
-LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50
-LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54
-LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58
-LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66
-LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70
-LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49
-LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53
-LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57
-
-
-#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
-#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
-#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
-
-
-
-# nXyter 2
-
-LOCATE COMP "NX2_ADC_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133
-LOCATE COMP "NX2_RESET_OUT" SITE "W23"; #DQLR1_0 #169
-LOCATE COMP "NX2_MAIN_CLK_OUT" SITE "AA26"; #DQLR1_4 #177
-LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185
-LOCATE COMP "NX2_DATA_CLK_IN" SITE "M23"; #DQSUR1_T #118
-#LOCATE COMP "NX2_DATA_CLK_IN" SITE "N23"; #DQUR2_2 #134
-LOCATE COMP "ADDON_TRIGGER_OUT" SITE "N23"; #DQUR2_2 #134
-
-LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170
-LOCATE COMP "NX2_I2C_SDA_INOUT" SITE "R26"; #DQLR2_1 #172
-LOCATE COMP "NX2_I2C_REG_RESET_OUT" SITE "T25"; #DQLR2_2 #174
-LOCATE COMP "NX2_I2C_SM_RESET_OUT" SITE "T24"; #DQLR2_3 #176
-
-LOCATE COMP "NX2_SPI_SDIO_INOUT" SITE "T26"; #DQLR2_4 #178
-LOCATE COMP "NX2_SPI_SCLK_OUT" SITE "U26"; #DQLR2_5 #180
-LOCATE COMP "NX2_SPI_CSB_OUT" SITE "U24"; #DQLR2_6 #186
-
-LOCATE COMP "NX2_ADC_D_IN" SITE "J23"; #DQUR0_0 #105
-LOCATE COMP "NX2_ADC_A_IN" SITE "G26"; #DQUR0_2 #109
-LOCATE COMP "NX2_ADC_DCLK_IN" SITE "F24"; #DQSUR0_T #113
-LOCATE COMP "NX2_ADC_NX_IN" SITE "H26"; #DQUR0_4 #117
-LOCATE COMP "NX2_ADC_B_IN" SITE "K23"; #DQUR0_6 #121
-LOCATE COMP "NX2_ADC_FCLK_IN" SITE "F25"; #DQUR0_8 #125 #input only
-
-LOCATE COMP "NX2_TIMESTAMP_IN_0" SITE "H24"; #DQUR1_0 #106
-LOCATE COMP "NX2_TIMESTAMP_IN_1" SITE "L20"; #DQUR1_2 #110
-LOCATE COMP "NX2_TIMESTAMP_IN_2" SITE "K24"; #DQUR1_4 #114
-LOCATE COMP "NX2_TIMESTAMP_IN_3" SITE "L24"; #DQUR1_6 #122
-LOCATE COMP "NX2_TIMESTAMP_IN_4" SITE "M22"; #DQUR1_8 #126
-LOCATE COMP "NX2_TIMESTAMP_IN_5" SITE "J26"; #DQUR2_0 #130
-LOCATE COMP "NX2_TIMESTAMP_IN_6" SITE "K19"; #DQUR2_4 #138
-LOCATE COMP "NX2_TIMESTAMP_IN_7" SITE "L25"; #DQUR2_6 #146
-
-
-#DEFINE PORT GROUP "LVDS_group3" "NX2_TIMESTAMP*" ;
-#IOBUF GROUP "LVDS_group3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-
-#DEFINE PORT GROUP "LVDS_group4" "NX2_ADC*IN" ;
-#IOBUF GROUP "LVDS_group4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "ADDON_TRIGGER_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX2_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX2_RESET_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX2_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX2_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-IOBUF PORT "NX2_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
-IOBUF PORT "NX2_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
-IOBUF PORT "NX2_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-
-
-
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-
-LOCATE COMP "FLASH_CLK" SITE "B12";
-LOCATE COMP "FLASH_CS" SITE "E11";
-LOCATE COMP "FLASH_DIN" SITE "E12";
-LOCATE COMP "FLASH_DOUT" SITE "A12";
-
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-
-LOCATE COMP "PROGRAMN" SITE "B11";
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-
-
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13";
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20";
-LOCATE COMP "CODE_LINE_0" SITE "Y21";
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-#terminated differential pair to pads
-#LOCATE COMP "SUPPL" SITE "C14";
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-
-
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12";
-LOCATE COMP "LED_ORANGE" SITE "G13";
-LOCATE COMP "LED_RED" SITE "A15";
-LOCATE COMP "LED_YELLOW" SITE "A16";
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
--- /dev/null
+../nxyter/trb3_periph_nxyter.lpf
\ No newline at end of file
./compile_munich21.pl
-grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup"
+#grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup"
+grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup
echo "Script DONE!"
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_44_data_delay" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 01 16:22:47.436" version="4.8" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_44_data_delay.lpc" type="lpc" modified="2013 12 01 16:22:45.000"/>
- <File name="fifo_44_data_delay.vhd" type="top_level_vhdl" modified="2013 12 01 16:22:45.000"/>
- <File name="fifo_44_data_delay_tmpl.vhd" type="template_vhdl" modified="2013 12 01 16:22:45.000"/>
- <File name="tb_fifo_44_data_delay_tmpl.vhd" type="testbench_vhdl" modified="2013 12 01 16:22:45.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 44 -depth 256 -regout -no_enable -pe 0 -pf -1 -e
-
--- Sun Dec 1 16:22:45 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_44_data_delay is
- port (
- Data: in std_logic_vector(43 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmEmptyThresh: in std_logic_vector(7 downto 0);
- Q: out std_logic_vector(43 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic);
-end fifo_44_data_delay;
-
-architecture Structure of fifo_44_data_delay is
-
- -- internal signal declarations
- signal invout_2: std_logic;
- signal invout_1: std_logic;
- signal rden_i_inv: std_logic;
- signal invout_0: std_logic;
- signal r_nw: std_logic;
- signal rcnt_reg_7_inv: std_logic;
- signal fcnt_en: std_logic;
- signal empty_i: std_logic;
- signal empty_d: std_logic;
- signal full_i: std_logic;
- signal full_d: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rcnt_reg_8: std_logic;
- signal ifcount_0: std_logic;
- signal ifcount_1: std_logic;
- signal bdcnt_bctr_ci: std_logic;
- signal ifcount_2: std_logic;
- signal ifcount_3: std_logic;
- signal co0: std_logic;
- signal ifcount_4: std_logic;
- signal ifcount_5: std_logic;
- signal co1: std_logic;
- signal ifcount_6: std_logic;
- signal ifcount_7: std_logic;
- signal co2: std_logic;
- signal ifcount_8: std_logic;
- signal co4: std_logic;
- signal cnt_con: std_logic;
- signal co3: std_logic;
- signal cmp_ci: std_logic;
- signal co0_1: std_logic;
- signal co1_1: std_logic;
- signal co2_1: std_logic;
- signal co3_1: std_logic;
- signal cmp_le_1: std_logic;
- signal cmp_le_1_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
- signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
- signal co1_2: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
- signal co2_2: std_logic;
- signal wren_i: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
- signal co3_2: std_logic;
- signal wren_i_inv: std_logic;
- signal fcount_8: std_logic;
- signal cmp_ge_d1: std_logic;
- signal cmp_ge_d1_c: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_ctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0_3: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1_3: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2_3: std_logic;
- signal iwcount_8: std_logic;
- signal co4_1: std_logic;
- signal wcount_8: std_logic;
- signal co3_3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_ctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_4: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_4: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_4: std_logic;
- signal ircount_8: std_logic;
- signal co4_2: std_logic;
- signal rcount_8: std_logic;
- signal co3_4: std_logic;
- signal rcnt_sub_0: std_logic;
- signal r_nw_inv_inv: std_logic;
- signal rcount_0: std_logic;
- signal r_nw_inv: std_logic;
- signal wcount_0: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rcount_1: std_logic;
- signal rcount_2: std_logic;
- signal wcount_1: std_logic;
- signal wcount_2: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rcount_3: std_logic;
- signal rcount_4: std_logic;
- signal wcount_3: std_logic;
- signal wcount_4: std_logic;
- signal rcnt_sub_5: std_logic;
- signal rcnt_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rcount_5: std_logic;
- signal rcount_6: std_logic;
- signal wcount_5: std_logic;
- signal wcount_6: std_logic;
- signal rcnt_sub_7: std_logic;
- signal rcnt_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rcount_7: std_logic;
- signal wcount_7: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co4_3d: std_logic;
- signal co4_3: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_6: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_6: std_logic;
- signal rcnt_reg_4: std_logic;
- signal rcnt_reg_5: std_logic;
- signal co2_6: std_logic;
- signal rcnt_reg_6: std_logic;
- signal rcnt_reg_7: std_logic;
- signal co3_6: std_logic;
- signal ae_set_clrsig: std_logic;
- signal ae_set_setsig: std_logic;
- signal ae_set_d: std_logic;
- signal ae_set_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; LE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
- NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_44_data_delay.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_44_data_delay.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t7: AND2
- port map (A=>WrEn, B=>invout_2, Z=>wren_i);
-
- INV_7: INV
- port map (A=>full_i, Z=>invout_2);
-
- AND2_t6: AND2
- port map (A=>RdEn, B=>invout_1, Z=>rden_i);
-
- INV_6: INV
- port map (A=>empty_i, Z=>invout_1);
-
- AND2_t5: AND2
- port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
-
- XOR2_t4: XOR2
- port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
-
- INV_5: INV
- port map (A=>rden_i, Z=>rden_i_inv);
-
- INV_4: INV
- port map (A=>wren_i, Z=>wren_i_inv);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"3232")
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
- AD0=>empty_i, DO0=>empty_d);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"3232")
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
- AD0=>full_i, DO0=>full_d);
-
- AND2_t3: AND2
- port map (A=>rden_i, B=>invout_0, Z=>r_nw);
-
- INV_3: INV
- port map (A=>wren_i, Z=>invout_0);
-
- INV_2: INV
- port map (A=>r_nw, Z=>r_nw_inv);
-
- XOR2_t2: XOR2
- port map (A=>wcount_8, B=>rcount_8, Z=>rcnt_sub_msb);
-
- INV_1: INV
- port map (A=>r_nw_inv, Z=>r_nw_inv_inv);
-
- INV_0: INV
- port map (A=>rcnt_reg_7, Z=>rcnt_reg_7_inv);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_8, B=>rcnt_reg_7_inv, Z=>ae_set_clrsig);
-
- AND2_t0: AND2
- port map (A=>rcnt_reg_8, B=>rcnt_reg_7, Z=>ae_set_setsig);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock,
- CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
- DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22),
- DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27),
- DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31),
- DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), DO17=>Q(35),
- DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
- DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
- DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
- DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
- DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
- DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
- DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
- DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
- DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
- DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
- DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
- DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
- DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1,
- ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5,
- ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
- CLKW=>Clock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
- ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
- ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
- CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
- DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
- DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
- DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
- DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
- DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
- DO34=>open, DO35=>open);
-
- FF_56: FD1P3DX
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_0);
-
- FF_55: FD1P3DX
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_1);
-
- FF_54: FD1P3DX
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_2);
-
- FF_53: FD1P3DX
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_3);
-
- FF_52: FD1P3DX
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_4);
-
- FF_51: FD1P3DX
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_5);
-
- FF_50: FD1P3DX
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_6);
-
- FF_49: FD1P3DX
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_7);
-
- FF_48: FD1P3DX
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_8);
-
- FF_47: FD1S3BX
- port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
-
- FF_46: FD1S3DX
- port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
-
- FF_45: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
- Q=>wcount_0);
-
- FF_44: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_1);
-
- FF_43: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_2);
-
- FF_42: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_3);
-
- FF_41: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_4);
-
- FF_40: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_5);
-
- FF_39: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_6);
-
- FF_38: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_7);
-
- FF_37: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_8);
-
- FF_36: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
- Q=>rcount_0);
-
- FF_35: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_1);
-
- FF_34: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_2);
-
- FF_33: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_3);
-
- FF_32: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_4);
-
- FF_31: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_5);
-
- FF_30: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_6);
-
- FF_29: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_7);
-
- FF_28: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_8);
-
- FF_27: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_0);
-
- FF_26: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_1);
-
- FF_25: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_2);
-
- FF_24: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_3);
-
- FF_23: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_4);
-
- FF_22: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_5);
-
- FF_21: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_6);
-
- FF_20: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_7);
-
- FF_19: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_8);
-
- FF_18: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_0);
-
- FF_17: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_1);
-
- FF_16: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_2);
-
- FF_15: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_3);
-
- FF_14: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_4);
-
- FF_13: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_5);
-
- FF_12: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_6);
-
- FF_11: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_7);
-
- FF_10: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_8);
-
- FF_9: FD1S3DX
- port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0);
-
- FF_8: FD1S3DX
- port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1);
-
- FF_7: FD1S3DX
- port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2);
-
- FF_6: FD1S3DX
- port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3);
-
- FF_5: FD1S3DX
- port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4);
-
- FF_4: FD1S3DX
- port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5);
-
- FF_3: FD1S3DX
- port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6);
-
- FF_2: FD1S3DX
- port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7);
-
- FF_1: FD1S3DX
- port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8);
-
- FF_0: FD1S3BX
- port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
-
- bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
- CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
-
- bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
- CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
-
- bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
- CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
-
- bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
- CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
-
- bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
- CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
-
- bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>scuba_vlo, CON=>cnt_con,
- CO=>co4, NC0=>ifcount_8, NC1=>open);
-
- e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
- S1=>open);
-
- e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
- CI=>cmp_ci, LE=>co0_1);
-
- e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
-
- e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
-
- e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
-
- e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
- S1=>open);
-
- g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
- S1=>open);
-
- g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
- CI=>cmp_ci_1, GE=>co0_2);
-
- g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
- CI=>co0_2, GE=>co1_2);
-
- g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
- CI=>co1_2, GE=>co2_2);
-
- g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
- CI=>co2_2, GE=>co3_2);
-
- g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>scuba_vlo, B0=>wren_i_inv,
- B1=>scuba_vlo, CI=>co3_2, GE=>cmp_ge_d1_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
- S1=>open);
-
- w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
- S1=>open);
-
- w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4_1,
- NC0=>iwcount_8, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
- S1=>open);
-
- r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>scuba_vlo, CO=>co4_2,
- NC0=>ircount_8, NC1=>open);
-
- rcnt_0: FSUB2B
- port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4,
- BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4);
-
- rcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6,
- BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6);
-
- rcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>rcnt_sub_msb, B0=>rcount_7,
- B1=>scuba_vlo, BI=>co3_5, BOUT=>co4_3, S0=>rcnt_sub_7,
- S1=>rcnt_sub_8);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co4_3, COUT=>open, S0=>co4_3d, S1=>open);
-
- ae_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_set_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6);
-
- ae_set_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6);
-
- ae_set_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
- B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6);
-
- ae_set_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
- B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6);
-
- ae_set_cmp_4: AGEB2
- port map (A0=>ae_set_setsig, A1=>scuba_vlo, B0=>ae_set_clrsig,
- B1=>scuba_vlo, CI=>co3_6, GE=>ae_set_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_44_data_delay is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:ALEB2 use entity ecp3.ALEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:CB2 use entity ecp3.CB2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ram_dp_128x40" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 15 14:15:58.011" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2013 12 15 14:15:58.000"/>
+ <File name="ram_dp_128x40.lpc" type="lpc" modified="2013 12 15 14:15:56.000"/>
+ <File name="ram_dp_128x40.vhd" type="top_level_vhdl" modified="2013 12 15 14:15:56.000"/>
+ <File name="ram_dp_128x40_tmpl.vhd" type="template_vhdl" modified="2013 12 15 14:15:56.000"/>
+ <File name="tb_ram_dp_128x40_tmpl.vhd" type="testbench_vhdl" modified="2013 12 15 14:15:56.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=ram_dp_128x40
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/15/2013
+Time=14:15:56
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=128
+RData=40
+WAddress=128
+WData=40
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=0
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 6.1
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 40 -data_width 40 -num_rows 128 -cascade -1 -e
+
+-- Sun Dec 15 14:15:56 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ram_dp_128x40 is
+ port (
+ WrAddress: in std_logic_vector(6 downto 0);
+ RdAddress: in std_logic_vector(6 downto 0);
+ Data: in std_logic_vector(39 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(39 downto 0));
+end ram_dp_128x40;
+
+architecture Structure of ram_dp_128x40 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ram_dp_128x40_0_0_1 : label is "ram_dp_128x40.lpc";
+ attribute MEM_INIT_FILE of ram_dp_128x40_0_0_1 : label is "";
+ attribute RESETMODE of ram_dp_128x40_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of ram_dp_128x40_0_1_0 : label is "ram_dp_128x40.lpc";
+ attribute MEM_INIT_FILE of ram_dp_128x40_0_1_0 : label is "";
+ attribute RESETMODE of ram_dp_128x40_0_1_0 : label is "SYNC";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ ram_dp_128x40_0_0_1: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
+ ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
+ ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
+ ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
+ ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
+ DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
+ DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
+ DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
+ DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
+ DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
+ DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
+ DO35=>Q(17));
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ ram_dp_128x40_0_1_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>scuba_vlo, DI5=>scuba_vlo,
+ DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
+ DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo,
+ DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
+ DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
+ ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
+ ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
+ ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
+ ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36),
+ DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>open,
+ DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
+ DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
+ DO33=>open, DO34=>open, DO35=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ram_dp_128x40 is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ram_fifo_delay_256x44" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 01 16:38:04.085" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2013 12 01 16:38:04.000"/>
+ <File name="ram_fifo_delay_256x44.lpc" type="lpc" modified="2013 12 01 16:38:02.000"/>
+ <File name="ram_fifo_delay_256x44.vhd" type="top_level_vhdl" modified="2013 12 01 16:38:02.000"/>
+ <File name="ram_fifo_delay_256x44_tmpl.vhd" type="template_vhdl" modified="2013 12 01 16:38:02.000"/>
+ <File name="tb_ram_fifo_delay_256x44_tmpl.vhd" type="testbench_vhdl" modified="2013 12 01 16:38:02.000"/>
+ </Package>
+</DiamondModule>
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
-CoreName=FIFO
-CoreRevision=4.8
-ModuleName=fifo_44_data_delay
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=ram_fifo_delay_256x44
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=12/01/2013
-Time=16:22:45
+Time=16:38:02
[Parameters]
Verilog=0
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
-FIFOImp=EBR Based
-Depth=256
-Width=44
-regout=1
-CtrlByRdEn=0
-EmpFlg=1
-PeMode=Dynamic - Single Threshold
-PeAssert=2
-PeDeassert=12
-FullFlg=0
-PfMode=Dynamic - Single Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
+RAddress=256
+RData=44
+WAddress=256
+WData=44
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=1
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
EnECC=0
-EnFWFT=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 6.1
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 44 -data_width 44 -num_rows 256 -outdata REGISTERED -cascade -1 -e
+
+-- Sun Dec 1 16:38:02 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ram_fifo_delay_256x44 is
+ port (
+ WrAddress: in std_logic_vector(7 downto 0);
+ RdAddress: in std_logic_vector(7 downto 0);
+ Data: in std_logic_vector(43 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(43 downto 0));
+end ram_fifo_delay_256x44;
+
+architecture Structure of ram_fifo_delay_256x44 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ram_fifo_delay_256x44_0_0_1 : label is "ram_fifo_delay_256x44.lpc";
+ attribute MEM_INIT_FILE of ram_fifo_delay_256x44_0_0_1 : label is "";
+ attribute RESETMODE of ram_fifo_delay_256x44_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of ram_fifo_delay_256x44_0_1_0 : label is "ram_fifo_delay_256x44.lpc";
+ attribute MEM_INIT_FILE of ram_fifo_delay_256x44_0_1_0 : label is "";
+ attribute RESETMODE of ram_fifo_delay_256x44_0_1_0 : label is "SYNC";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ ram_fifo_delay_256x44_0_0_1: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
+ ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
+ ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
+ ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
+ ADR10=>RdAddress(5), ADR11=>RdAddress(6),
+ ADR12=>RdAddress(7), ADR13=>scuba_vlo, CER=>RdClockEn,
+ CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
+ DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
+ DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
+ DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ ram_fifo_delay_256x44_0_1_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
+ DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>WrAddress(0),
+ ADW1=>WrAddress(1), ADW2=>WrAddress(2), ADW3=>WrAddress(3),
+ ADW4=>WrAddress(4), ADW5=>WrAddress(5), ADW6=>WrAddress(6),
+ ADW7=>WrAddress(7), ADW8=>scuba_vlo, BE0=>scuba_vhi,
+ BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi,
+ CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>RdAddress(0), ADR6=>RdAddress(1), ADR7=>RdAddress(2),
+ ADR8=>RdAddress(3), ADR9=>RdAddress(4), ADR10=>RdAddress(5),
+ ADR11=>RdAddress(6), ADR12=>RdAddress(7), ADR13=>scuba_vlo,
+ CER=>RdClockEn, CLKR=>RdClock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
+ DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
+ DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ram_fifo_delay_256x44 is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
CLK_IN : in std_logic;
RESET_IN : in std_logic;
CLK_ADCDAT_IN : in std_logic;
- RESTART_IN : in std_logic;
ADC0_SCLK_IN : in std_logic; -- Sampling Clock ADC0
ADC0_SCLK_OUT : out std_logic;
ERROR_ADC0_OUT : out std_logic;
ERROR_ADC1_OUT : out std_logic;
+ DEBUG_IN : in std_logic_vector(3 downto 0);
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end adc_ad9228;
-- DDR Generic Handler
signal DDR_DATA_CLK : std_logic;
- signal reset_0 : std_logic;
- signal reset_1 : std_logic;
- signal clkdiv_reset : std_logic;
signal q_0 : std_logic_vector(19 downto 0);
signal q_1 : std_logic_vector(19 downto 0);
-- NotLock Counters
- signal adc0_frame_notlocked_p : std_logic;
signal adc0_frame_notlocked : std_logic;
+ signal adc0_frame_notlocked_p : std_logic;
signal adc0_notlock_ctr : unsigned(7 downto 0);
signal adc0_bit_shift : unsigned(1 downto 0);
signal adc0_bit_shift_last : unsigned(1 downto 0);
signal adc0_bit_shift_change : std_logic;
- signal adc1_frame_notlocked_p : std_logic;
signal adc1_frame_notlocked : std_logic;
+ signal adc1_frame_notlocked_p : std_logic;
signal adc1_notlock_ctr : unsigned(7 downto 0);
signal adc1_bit_shift : unsigned(1 downto 0);
signal adc1_bit_shift_last : unsigned(1 downto 0);
type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0);
signal adc0_data_buf : adc_data_buf_t;
- signal adc0_frame_ctr : unsigned(3 downto 0);
+ signal adc0_frame_ctr : unsigned(2 downto 0);
signal adc0_frame_locked : std_logic;
signal adc0_new_data_t : std_logic;
signal adc0_data_t : adc_data_t;
signal adc1_data_buf : adc_data_buf_t;
- signal adc1_frame_ctr : unsigned(3 downto 0);
+ signal adc1_frame_ctr : unsigned(2 downto 0);
signal adc1_frame_locked : std_logic;
signal adc1_new_data_t : std_logic;
signal adc1_data_f : adc_data_t;
signal adc1_data_o : adc_data_t;
+
+ -- Resets
+ signal RESET_CLK_ADCDAT_IN : std_logic;
+ signal RESET_DDR_DATA_CLK : std_logic;
+
begin
- -- DEBUG
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= DDR_DATA_CLK;
- --DEBUG_OUT(2) <= adc0_bit_shift_change;
- --DEBUG_OUT(3) <= adc0_write_enable;
- --DEBUG_OUT(4) <= adc0_fifo_full;
- --DEBUG_OUT(5) <= adc0_fifo_empty;
- --DEBUG_OUT(6) <= adc0_frame_locked;
- --DEBUG_OUT(7) <= adc0_new_data_t;
- --DEBUG_OUT(8) <= adc0_read_enable;
- --DEBUG_OUT(9) <= adc0_read_enable_t;
- --DEBUG_OUT(10) <= adc0_read_enable_tt;
- --DEBUG_OUT(11) <= adc0_data_valid_o;
- --DEBUG_OUT(15 downto 12) <= adc0_data_f(0)(3 downto 0);
-
- DEBUG_OUT(5 downto 2) <= adc0_data_t(0)(3 downto 0);
- DEBUG_OUT(6) <= adc0_fifo_full;
- DEBUG_OUT(7) <= adc0_write_enable;
- DEBUG_OUT(8) <= adc0_fifo_empty;
- DEBUG_OUT(9) <= adc0_read_enable;
- DEBUG_OUT(10) <= adc0_read_enable_tt;
- DEBUG_OUT(11) <= adc0_data_valid_o;
- DEBUG_OUT(15 downto 12) <= adc0_data_f(0)(3 downto 0);
+ PROC_DEBUG: process (DEBUG_IN)
+ begin
+ case DEBUG_IN is
+ when x"0" =>
+ -- DEBUG
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= DDR_DATA_CLK;
+ DEBUG_OUT(2) <= adc0_bit_shift_change;
+ DEBUG_OUT(3) <= adc0_write_enable;
+ DEBUG_OUT(4) <= adc0_fifo_full;
+ DEBUG_OUT(5) <= adc0_fifo_empty;
+ DEBUG_OUT(6) <= adc0_frame_locked;
+ DEBUG_OUT(7) <= adc0_new_data_t;
+ DEBUG_OUT(8) <= adc0_read_enable;
+ DEBUG_OUT(9) <= adc0_read_enable_t;
+ DEBUG_OUT(10) <= adc0_read_enable_tt;
+ DEBUG_OUT(11) <= adc0_data_valid_o;
+ DEBUG_OUT(15 downto 12) <= (others => '0');
+
+ when x"1" =>
+ DEBUG_OUT <= adc0_data_buf(0);
+
+ when x"2" =>
+ DEBUG_OUT <= adc0_data_buf(1);
+
+ when x"3" =>
+ DEBUG_OUT <= adc0_data_buf(2);
+
+ when x"4" =>
+ DEBUG_OUT <= adc0_data_buf(3);
+
+ when x"5" =>
+ DEBUG_OUT <= adc0_data_buf(4);
+
+ --when x"e" =>
+ -- DEBUG_OUT <= q_0(15 downto 0);
+
+ --when x"f" =>
+ -- DEBUG_OUT <= q_1(15 downto 0);
+
+ when others =>
+ DEBUG_OUT <= (others => '0');
+ end case;
+ end process PROC_DEBUG;
+
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
+ signal_async_trans_RESET_IN: signal_async_trans
+ port map (
+ CLK_IN => CLK_ADCDAT_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_CLK_ADCDAT_IN
+ );
+
+ signal_async_trans_RESET_IN_2: signal_async_trans
+ port map (
+ CLK_IN => DDR_DATA_CLK,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_DDR_DATA_CLK
+ );
-----------------------------------------------------------------------------
+
adc_ddr_generic_1: adc_ddr_generic
port map (
clk_0 => ADC0_DCLK_IN,
clk_1 => ADC1_DCLK_IN,
- clkdiv_reset => clkdiv_reset,
+ clkdiv_reset => RESET_CLK_ADCDAT_IN,
eclk => CLK_ADCDAT_IN,
- reset_0 => reset_0,
- reset_1 => reset_1,
+ reset_0 => RESET_DDR_DATA_CLK,
+ reset_1 => RESET_DDR_DATA_CLK,
sclk => DDR_DATA_CLK,
datain_0(0) => ADC0_DATA_A_IN,
q_1 => q_1
);
--- ddr_generic_single_1: ddr_generic_single
--- port map (
--- clk_0 => ADC0_DCLK_IN,
--- clkdiv_reset => clkdiv_reset,
--- eclk => CLK_ADCDAT_IN,
--- reset_0 => reset_0,
--- sclk => DDR_DATA_CLK,
---
--- datain_0(0) => ADC0_DATA_A_IN,
--- datain_0(1) => ADC0_DATA_B_IN,
--- datain_0(2) => ADC0_DATA_C_IN,
--- datain_0(3) => ADC0_DATA_D_IN,
--- datain_0(4) => ADC0_FCLK_IN
--- );
-
- reset_0 <= RESET_IN or RESTART_IN;
- reset_1 <= RESET_IN or RESTART_IN;
- clkdiv_reset <= RESET_IN;
-
-----------------------------------------------------------------------------
PROC_MERGE_DATA0: process(DDR_DATA_CLK)
variable q_0_map : q_map_t;
begin
if (rising_edge(DDR_DATA_CLK)) then
- if (RESET_IN = '1' or RESTART_IN = '1') then
- for I in 0 to 3 loop
- adc0_data_buf(I) <= (others => '0');
- end loop;
+ -- Remap DDR Output q_value
+ for I in 0 to 4 loop
+ q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15);
+ end loop;
+
+ for I in 0 to 4 loop
+ adc0_data_buf(I)(3 downto 0) <= q_0_map(I);
+ adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0);
+ end loop;
+
+ if (RESET_DDR_DATA_CLK = '1') then
adc0_new_data_t <= '0';
adc0_frame_ctr <= (others => '0');
adc0_frame_locked <= '0';
adc0_bit_shift_last <= "00";
adc0_bit_shift_change <= '0';
else
- -- Remap DDR Output q_value
- for I in 0 to 4 loop
- q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15);
- end loop;
-
- for I in 0 to 4 loop
- adc0_data_buf(I)(3 downto 0) <= q_0_map(I);
- adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0);
- end loop;
-
-- Test Frame Clock Pattern
adc0_new_data_t <= '0';
case adc0_data_buf(4) is -- adc0_data_buf(4) is frame clock
adc0_frame_locked <= '1';
elsif (adc0_frame_ctr < x"4") then
adc0_frame_ctr <= adc0_frame_ctr + 1;
- adc0_frame_locked <= adc0_frame_locked;
else
adc0_frame_locked <= '0';
end if;
variable q_1_map : q_map_t;
begin
if (rising_edge(DDR_DATA_CLK)) then
- if (RESET_IN = '1' or RESTART_IN = '1') then
- for I in 0 to 3 loop
- adc1_data_buf(I) <= (others => '0');
- end loop;
+ -- Remap DDR Output q_value
+ for I in 0 to 4 loop
+ q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15);
+ end loop;
+
+ for I in 0 to 4 loop
+ adc1_data_buf(I)(3 downto 0) <= q_1_map(I);
+ adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0);
+ end loop;
+
+ if (RESET_DDR_DATA_CLK = '1') then
adc1_new_data_t <= '0';
adc1_frame_ctr <= (others => '0');
adc1_frame_locked <= '0';
adc1_bit_shift_last <= "00";
adc1_bit_shift_change <= '0';
else
- -- Remap DDR Output q_value
- for I in 0 to 4 loop
- q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15);
- end loop;
-
- for I in 0 to 4 loop
- adc1_data_buf(I)(3 downto 0) <= q_1_map(I);
- adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0);
- end loop;
-
-- Test Frame Clock Pattern
adc1_new_data_t <= '0';
case adc1_data_buf(4) is -- adc1_data_buf(4) is frame clock
adc1_frame_locked <= '1';
elsif (adc1_frame_ctr < x"4") then
adc1_frame_ctr <= adc1_frame_ctr + 1;
- adc1_frame_locked <= adc1_frame_locked;
else
adc1_frame_locked <= '0';
end if;
Empty => adc0_fifo_empty,
Full => adc0_fifo_full
);
-
- adc0_fifo_reset <= RESET_IN or RESTART_IN;
+
+ -- Readout Handler
+ adc0_fifo_reset <= RESET_IN;
adc0_write_enable <= adc0_new_data_t and not adc0_fifo_full;
adc0_read_enable <= not adc0_fifo_empty;
PROC_ADC0_FIFO_READ: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1' or RESTART_IN = '1') then
- adc0_read_enable_t <= '0';
+ adc0_read_enable_t <= adc0_read_enable;
+ if (RESET_IN = '1') then
adc0_read_enable_tt <= '0';
for I in 0 to 3 loop
adc0_data_o(I) <= (others => '0');
adc0_data_valid_o <= '0';
else
-- Read enable
- adc0_read_enable_t <= adc0_read_enable;
adc0_read_enable_tt <= adc0_read_enable_t;
-
+
if (adc0_read_enable_tt = '1') then
for I in 0 to 3 loop
adc0_data_o(I) <= adc0_data_f(I);
Empty => adc1_fifo_empty,
Full => adc1_fifo_full
);
- adc1_fifo_reset <= RESET_IN or RESTART_IN;
+
+ -- Readout Handler
+ adc1_fifo_reset <= RESET_IN;
adc1_write_enable <= adc1_new_data_t and not adc1_fifo_full;
adc1_read_enable <= not adc1_fifo_empty;
PROC_ADC1_FIFO_READ: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1' or RESTART_IN = '1') then
+ if (RESET_IN = '1') then
adc1_read_enable_t <= '0';
adc1_read_enable_tt <= '0';
for I in 0 to 3 loop
level_to_pulse_1: level_to_pulse
port map (
CLK_IN => DDR_DATA_CLK,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_DDR_DATA_CLK,
LEVEL_IN => not adc0_frame_locked,
PULSE_OUT => adc0_frame_notlocked_p
);
level_to_pulse_2: level_to_pulse
port map (
CLK_IN => DDR_DATA_CLK,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_DDR_DATA_CLK,
LEVEL_IN => not adc1_frame_locked,
PULSE_OUT => adc1_frame_notlocked_p
);
)
port map (
CLK_A_IN => DDR_DATA_CLK,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_DDR_DATA_CLK,
PULSE_A_IN => adc0_frame_notlocked_p,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
)
port map (
CLK_A_IN => DDR_DATA_CLK,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_DDR_DATA_CLK,
PULSE_A_IN => adc1_frame_notlocked_p,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
if (adc1_frame_notlocked = '1' or
adc1_bit_shift_change = '1') then
- error_adc0_o <= '1';
+ error_adc1_o <= '1';
end if;
end if;
end if;
signal spi_busy : std_logic;
signal takeover_sdio : std_logic;
- signal wait_timer_init : unsigned(7 downto 0);
+ signal wait_timer_start : std_logic;
signal sendbyte_seq_start : std_logic;
signal readbyte_seq_start : std_logic;
signal sendbyte_byte : std_logic_vector(7 downto 0);
signal reg_data : std_logic_vector(31 downto 0);
signal spi_busy_x : std_logic;
- signal wait_timer_init_x : unsigned(7 downto 0);
+ signal wait_timer_start_x : std_logic;
signal sendbyte_seq_start_x : std_logic;
signal sendbyte_byte_x : std_logic_vector(7 downto 0);
signal readbyte_seq_start_x : std_logic;
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 8
+ CTR_WIDTH => 8,
+ CTR_END => to_integer(SPI_SPEED srl 2)
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
TIMER_DONE_OUT => wait_timer_done
);
-
+
adc_spi_sendbyte_1: adc_spi_sendbyte
generic map (
SPI_SPEED => SPI_SPEED
sendbyte_seq_start <= '0';
readbyte_seq_start <= '0';
sendbyte_byte <= (others => '0');
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
reg_data <= (others => '0');
read_seq_ctr <= '0';
STATE <= S_RESET;
sendbyte_seq_start <= sendbyte_seq_start_x;
readbyte_seq_start <= readbyte_seq_start_x;
sendbyte_byte <= sendbyte_byte_x;
- wait_timer_init <= wait_timer_init_x;
+ wait_timer_start <= wait_timer_start_x;
reg_data <= reg_data_x;
read_seq_ctr <= read_seq_ctr_x;
STATE <= NEXT_STATE;
sendbyte_seq_start_x <= '0';
sendbyte_byte_x <= (others => '0');
readbyte_seq_start_x <= '0';
- wait_timer_init_x <= (others => '0');
+ wait_timer_start_x <= '0';
reg_data_x <= reg_data;
read_seq_ctr_x <= read_seq_ctr;
-- SPI START Sequence
when S_START =>
- wait_timer_init_x <= SPI_SPEED srl 2;
- NEXT_STATE <= S_START_WAIT;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_START_WAIT;
when S_START_WAIT =>
if (wait_timer_done = '0') then
-- SPI STOP Sequence
when S_STOP =>
- wait_timer_init_x <= SPI_SPEED srl 2;
+ wait_timer_start_x <= '1';
NEXT_STATE <= S_STOP_WAIT;
when S_STOP_WAIT =>
architecture Behavioral of adc_spi_readbyte is
-- Send Byte
- signal sclk_o : std_logic;
- signal spi_start : std_logic;
-
- signal sequence_done_o : std_logic;
- signal spi_byte : unsigned(7 downto 0);
- signal bit_ctr : unsigned(3 downto 0);
- signal spi_ack_o : std_logic;
- signal wait_timer_init : unsigned(7 downto 0);
-
- signal sequence_done_o_x : std_logic;
- signal spi_byte_x : unsigned(7 downto 0);
- signal bit_ctr_x : unsigned(3 downto 0);
- signal spi_ack_o_x : std_logic;
- signal wait_timer_init_x : unsigned(7 downto 0);
-
+ signal sclk_o : std_logic;
+ signal spi_start : std_logic;
+
+ signal sequence_done_o : std_logic;
+ signal spi_byte : unsigned(7 downto 0);
+ signal bit_ctr : unsigned(3 downto 0);
+ signal spi_ack_o : std_logic;
+ signal wait_timer_start : std_logic;
+
+ signal sequence_done_o_x : std_logic;
+ signal spi_byte_x : unsigned(7 downto 0);
+ signal bit_ctr_x : unsigned(3 downto 0);
+ signal spi_ack_o_x : std_logic;
+ signal wait_timer_start_x : std_logic;
+
type STATES is (S_IDLE,
S_UNSET_SCKL,
S_UNSET_SCKL_HOLD,
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map(
- CTR_WIDTH => 8
+ CTR_WIDTH => 8,
+ CTR_END => to_integer(SPI_SPEED srl 1)
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
TIMER_DONE_OUT => wait_timer_done
);
-
PROC_READ_BYTE_TRANSFER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
sequence_done_o <= '0';
bit_ctr <= (others => '0');
spi_ack_o <= '0';
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
STATE <= S_IDLE;
else
sequence_done_o <= sequence_done_o_x;
spi_byte <= spi_byte_x;
bit_ctr <= bit_ctr_x;
spi_ack_o <= spi_ack_o_x;
- wait_timer_init <= wait_timer_init_x;
+ wait_timer_start <= wait_timer_start_x;
STATE <= NEXT_STATE;
end if;
end if;
spi_byte_x <= spi_byte;
bit_ctr_x <= bit_ctr;
spi_ack_o_x <= spi_ack_o;
- wait_timer_init_x <= (others => '0');
+ wait_timer_start_x <= '0';
case STATE is
when S_IDLE =>
if (START_IN = '1') then
- spi_byte_x <= (others => '0');
- bit_ctr_x <= x"7";
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_UNSET_SCKL;
+ spi_byte_x <= (others => '0');
+ bit_ctr_x <= x"7";
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_UNSET_SCKL;
else
- NEXT_STATE <= S_IDLE;
+ NEXT_STATE <= S_IDLE;
end if;
-- SPI Read byte
when S_UNSET_SCKL =>
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_UNSET_SCKL_HOLD;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_UNSET_SCKL_HOLD;
when S_UNSET_SCKL_HOLD =>
if (wait_timer_done = '0') then
end if;
when S_GET_BIT =>
- spi_byte_x(0) <= SDIO_IN;
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_SET_SCKL;
+ spi_byte_x(0) <= SDIO_IN;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_SET_SCKL;
when S_SET_SCKL =>
sclk_o <= '1';
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SCKL;
else
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_NEXT_BIT;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_NEXT_BIT;
end if;
when S_NEXT_BIT =>
if (bit_ctr > 0) then
bit_ctr_x <= bit_ctr - 1;
spi_byte_x <= spi_byte sll 1;
- wait_timer_init_x <= SPI_SPEED srl 1;
+ wait_timer_start_x <= '1';
NEXT_STATE <= S_UNSET_SCKL;
else
NEXT_STATE <= S_DONE;
architecture Behavioral of adc_spi_sendbyte is
-- Send Byte
- signal sclk_o : std_logic;
- signal sdio_o : std_logic;
- signal spi_start : std_logic;
-
- signal sequence_done_o : std_logic;
- signal spi_byte : unsigned(7 downto 0);
- signal bit_ctr : unsigned(3 downto 0);
- signal wait_timer_init : unsigned(7 downto 0);
-
- signal sequence_done_o_x : std_logic;
- signal spi_byte_x : unsigned(7 downto 0);
- signal bit_ctr_x : unsigned(3 downto 0);
- signal wait_timer_init_x : unsigned(7 downto 0);
+ signal sclk_o : std_logic;
+ signal sdio_o : std_logic;
+ signal spi_start : std_logic;
+
+ signal sequence_done_o : std_logic;
+ signal spi_byte : unsigned(7 downto 0);
+ signal bit_ctr : unsigned(3 downto 0);
+ signal wait_timer_start : std_logic;
+
+ signal sequence_done_o_x : std_logic;
+ signal spi_byte_x : unsigned(7 downto 0);
+ signal bit_ctr_x : unsigned(3 downto 0);
+ signal wait_timer_start_x : std_logic;
type STATES is (S_IDLE,
S_SET_SDIO,
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 8
+ CTR_WIDTH => 8,
+ CTR_END => to_integer(SPI_SPEED srl 1)
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
TIMER_DONE_OUT => wait_timer_done
);
-
PROC_SEND_BYTE_TRANSFER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
sequence_done_o <= '0';
bit_ctr <= (others => '0');
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
STATE <= S_IDLE;
else
sequence_done_o <= sequence_done_o_x;
spi_byte <= spi_byte_x;
bit_ctr <= bit_ctr_x;
- wait_timer_init <= wait_timer_init_x;
+ wait_timer_start <= wait_timer_start_x;
STATE <= NEXT_STATE;
end if;
end if;
sequence_done_o_x <= '0';
spi_byte_x <= spi_byte;
bit_ctr_x <= bit_ctr;
- wait_timer_init_x <= (others => '0');
+ wait_timer_start_x <= '0';
case STATE is
when S_IDLE =>
if (START_IN = '1') then
- spi_byte_x <= BYTE_IN;
- bit_ctr_x <= x"7";
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_SET_SDIO;
+ spi_byte_x <= BYTE_IN;
+ bit_ctr_x <= x"7";
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_SET_SDIO;
else
NEXT_STATE <= S_IDLE;
end if;
when S_SET_SDIO =>
sdio_o <= spi_byte(7);
if (wait_timer_done = '0') then
- NEXT_STATE <= S_SET_SDIO;
+ NEXT_STATE <= S_SET_SDIO;
else
- wait_timer_init_x <= SPI_SPEED srl 1;
- NEXT_STATE <= S_SET_SCLK;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_SET_SCLK;
end if;
when S_SET_SCLK =>
sdio_o <= spi_byte(7);
sclk_o <= '1';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_SET_SCLK;
+ NEXT_STATE <= S_SET_SCLK;
else
- NEXT_STATE <= S_NEXT_BIT;
+ NEXT_STATE <= S_NEXT_BIT;
end if;
when S_NEXT_BIT =>
if (bit_ctr > 0) then
bit_ctr_x <= bit_ctr - 1;
spi_byte_x <= spi_byte sll 1;
- wait_timer_init_x <= SPI_SPEED srl 1;
+ wait_timer_start_x <= '1';
NEXT_STATE <= S_SET_SDIO;
else
NEXT_STATE <= S_DONE;
when S_DONE =>
sdio_o <= spi_byte(7);
sclk_o <= '1';
- sequence_done_o_x <= '1';
- NEXT_STATE <= S_IDLE;
+ sequence_done_o_x <= '1';
+ NEXT_STATE <= S_IDLE;
end case;
end process PROC_SEND_BYTE;
end entity;
architecture Behavioral of bus_async_trans is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "BUS_ASYNC_TRANS";
-
type buffer_t is array(0 to NUM_FF - 1) of
std_logic_vector(BUS_WIDTH - 1 downto 0);
signal signal_ff : buffer_t;
signal STATE : STATES;
-- Wait Timer
+ signal wait_timer_start : std_logic;
signal wait_timer_init : unsigned(7 downto 0);
signal wait_timer_done : std_logic;
DEBUG_OUT(14) <= online_on;
DEBUG_OUT(15) <= '0';
- nx_timer_1: nx_timer
+ timer_1: timer
generic map (
CTR_WIDTH => 8
)
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
- TIMER_DONE_OUT => wait_timer_done
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => wait_timer_init,
+ TIMER_DONE_OUT => wait_timer_done
);
-----------------------------------------------------------------------------
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
i2c_sm_reset_o <= '0';
i2c_reg_reset_o <= '0';
nx_ts_reset_o <= '0';
i2c_sm_reset_o <= '0';
i2c_reg_reset_o <= '0';
nx_ts_reset_o <= '0';
- wait_timer_init <= (others => '0');
-
+ wait_timer_start <= '0';
+
case STATE is
when S_IDLE =>
if (i2c_sm_reset_start = '1') then
when S_I2C_SM_RESET =>
i2c_sm_reset_o <= '1';
wait_timer_init <= x"8f";
+ wait_timer_start <= '1';
STATE <= S_I2C_SM_RESET_WAIT;
when S_I2C_SM_RESET_WAIT =>
when S_I2C_REG_RESET =>
i2c_reg_reset_o <= '1';
wait_timer_init <= x"8f";
+ wait_timer_start <= '1';
STATE <= S_I2C_REG_RESET_WAIT;
when S_I2C_REG_RESET_WAIT =>
when S_NX_TS_RESET =>
nx_ts_reset_o <= '1';
wait_timer_init <= x"01";
+ wait_timer_start <= '1';
STATE <= S_NX_TS_RESET_WAIT;
when S_NX_TS_RESET_WAIT =>
signal_async_trans_1: signal_async_trans
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => PLL_NX_CLK_LOCK_IN,
SIGNAL_OUT => pll_nx_clk_lock
);
signal_async_trans_2: signal_async_trans
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => PLL_ADC_DCLK_LOCK_IN,
SIGNAL_OUT => pll_adc_dclk_lock
);
signal_async_trans_3: signal_async_trans
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => PLL_ADC_SCLK_LOCK_IN,
SIGNAL_OUT => pll_adc_sclk_lock
);
PROC_PLL_UNLOCK_COUNTERS: process (CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' or clear_notlock_counters = '1') then
- pll_nx_clk_notlock_ctr <= (others => '0');
+ if( RESET_IN = '1') then
+ pll_nx_clk_notlock_ctr <= (others => '0');
pll_adc_dclk_notlock_ctr <= (others => '0');
pll_adc_sclk_notlock_ctr <= (others => '0');
else
- if (pll_nx_clk_notlock = '1') then
- pll_nx_clk_notlock_ctr <= pll_nx_clk_notlock_ctr + 1;
- end if;
+ if (clear_notlock_counters = '1') then
+ pll_nx_clk_notlock_ctr <= (others => '0');
+ pll_adc_dclk_notlock_ctr <= (others => '0');
+ pll_adc_sclk_notlock_ctr <= (others => '0');
+ else
+ if (pll_nx_clk_notlock = '1') then
+ pll_nx_clk_notlock_ctr <= pll_nx_clk_notlock_ctr + 1;
+ end if;
- if (pll_adc_dclk_notlock = '1') then
- pll_adc_dclk_notlock_ctr <= pll_adc_dclk_notlock_ctr + 1;
- end if;
+ if (pll_adc_dclk_notlock = '1') then
+ pll_adc_dclk_notlock_ctr <= pll_adc_dclk_notlock_ctr + 1;
+ end if;
- if (pll_adc_sclk_notlock = '1') then
- pll_adc_sclk_notlock_ctr <= pll_adc_sclk_notlock_ctr + 1;
+ if (pll_adc_sclk_notlock = '1') then
+ pll_adc_sclk_notlock_ctr <= pll_adc_sclk_notlock_ctr + 1;
+ end if;
end if;
-
end if;
end if;
end process PROC_PLL_UNLOCK_COUNTERS;
signal fifo_write_enable : std_logic;
signal fifo_reset : std_logic;
- -- My FIFO
- signal fifo_full_0 : std_logic;
- signal fifo_empty_0 : std_logic;
- signal fifo_almost_empty_0 : std_logic;
- signal fifo_data_out_0 : std_logic_vector(43 downto 0);
- signal fifo_read_enable_0 : std_logic;
-
- -- Lattice FIFO
- signal fifo_full_1 : std_logic;
- signal fifo_empty_1 : std_logic;
- signal fifo_almost_empty_1 : std_logic;
- signal fifo_data_out_1 : std_logic_vector(43 downto 0);
- signal fifo_read_enable_1 : std_logic;
- signal fifo_read_enable_r_1 : std_logic;
-
-- FIFO READ
signal fifo_data_out : std_logic_vector(43 downto 0);
signal fifo_read_enable : std_logic;
-----------------------------------------------------------------------------
-- FIFO Delay Handler
-----------------------------------------------------------------------------
-
- fifo_44_data_delay_1: fifo_44_data_delay
- port map (
- Data => fifo_data_in,
- Clock => CLK_IN,
- WrEn => fifo_write_enable,
- RdEn => fifo_read_enable_1,
- Reset => fifo_reset,
- AmEmptyThresh => fifo_delay,
- Q => fifo_data_out_1,
- Empty => fifo_empty_1,
- Full => fifo_full_1,
- AlmostEmpty => fifo_almost_empty_1
- );
-
- fifo_read_enable_r_1 <= fifo_read_enable_1 when rising_edge(CLK_IN);
fifo_44_data_delay_my_1: fifo_44_data_delay_my
port map (
Data => fifo_data_in,
Clock => CLK_IN,
WrEn => fifo_write_enable,
- RdEn => fifo_read_enable_0,
+ RdEn => fifo_read_enable, --LOOP??
Reset => fifo_reset,
AmEmptyThresh => fifo_delay,
- Q => fifo_data_out_0,
- Empty => fifo_empty_0,
- Full => fifo_full_0,
- AlmostEmpty => fifo_almost_empty_0,
+ Q => fifo_data_out, --fifo_data_out_0,
+ Empty => fifo_empty, -- fifo_empty_0,
+ Full => fifo_full, --fifo_full_0,
+ AlmostEmpty => fifo_almost_empty, -- fifo_almost_empty_0,
DEBUG_OUT => debug_fifo
);
- PROC_FIFO_SELECT: process(fifo_select)
- begin
- if (fifo_select = '0') then
- fifo_read_enable_0 <= not fifo_almost_empty_0;
- fifo_read_enable <= fifo_read_enable_0;
- fifo_full <= fifo_full_0;
- fifo_empty <= fifo_empty_0;
- fifo_almost_empty <= fifo_almost_empty_0;
- fifo_data_out <= fifo_data_out_0;
- else
- fifo_read_enable_1 <= not fifo_almost_empty_1
- and not fifo_read_enable_r_1;
- fifo_read_enable <= fifo_read_enable_1;
- fifo_full <= fifo_full_1;
- fifo_empty <= fifo_empty_1;
- fifo_almost_empty <= fifo_almost_empty_1;
- fifo_data_out <= fifo_data_out_1;
-
- end if;
- end process PROC_FIFO_SELECT;
-
+ fifo_read_enable <= not fifo_almost_empty;
fifo_reset <= RESET_IN or fifo_reset_r or fifo_delay_reset;
fifo_data_in(31 downto 0) <= NX_FRAME_IN;
fifo_data_in(43 downto 32) <= ADC_DATA_IN;
-- ADC RESET
signal adc_clk_ok_last : std_logic;
- signal adc_reset_s : std_logic;
+ signal adc_reset_sync_s : std_logic;
+ signal adc_reset_sync : std_logic;
signal adc_reset_ctr : unsigned(11 downto 0);
-- Reset Handler
- signal r_wait_timer_init : unsigned(27 downto 0);
- signal r_wait_timer_done : std_logic;
- signal reset_adc_handler : std_logic;
+ signal r1_wait_timer_start : std_logic;
+ signal r1_wait_timer_done : std_logic;
+ signal r2_wait_timer_start : std_logic;
+ signal r2_wait_timer_done : std_logic;
+
type R_STATES is (R_IDLE,
R_PLL_RESET,
R_PLL_WAIT_UNLOCK,
signal sampling_clk_reset_p : std_logic;
signal sampling_clk_reset : std_logic;
signal adc_reset_p : std_logic;
- signal adc_reset : std_logic;
- signal adc_reset_h : std_logic;
+ signal ADC_RESET_AD9228 : std_logic;
signal data_handler_reset_p : std_logic;
signal data_handler_reset : std_logic;
signal reset_handler_counter : unsigned(15 downto 0);
signal adc_data : std_logic_vector(11 downto 0);
signal test_adc_data : std_logic_vector(11 downto 0);
signal adc_data_valid : std_logic;
-
+
signal adc_data_t : std_logic_vector(11 downto 0);
signal adc_new_data : std_logic;
signal adc_new_data_ctr : unsigned(3 downto 0);
signal adc_notlock_ctr : unsigned(7 downto 0);
signal ADC_DEBUG : std_logic_vector(15 downto 0);
+ signal adc_debug_type : std_logic_vector(3 downto 0);
-- Data Output Handler
type STATES is (IDLE,
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
+
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
signal johnson_counter_sync_r : unsigned(1 downto 0);
signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0);
+ -- Resets
+ signal RESET_NX_TIMESTAMP_CLK_IN : std_logic;
+ signal RESET_NX_DATA_CLK_TEST_IN : std_logic;
+
begin
PROC_DEBUG_MULT: process(debug_adc,
adc_clk_ok,
adc_clk_ok_last,
adc_clk_skip,
- adc_reset_s,
- adc_reset,
+ adc_reset_sync,
+ adc_reset_sync_s,
+ ADC_RESET_AD9228,
nx_new_frame,
adc_reset_ctr,
nx_fifo_full,
begin
case debug_adc is
when "001" =>
+ -- AD9228 Hanlder Debug output
DEBUG_OUT <= ADC_DEBUG;
-
+
when "010" =>
+ -- Reset Handler
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= nx_new_frame;
- DEBUG_OUT(2) <= TRIGGER_IN;
- DEBUG_OUT(3) <= adc_data_valid;
- DEBUG_OUT(15 downto 4) <= adc_data;
+ DEBUG_OUT(1) <= TRIGGER_IN;
+ DEBUG_OUT(2) <= nx_new_frame;
+ DEBUG_OUT(3) <= adc_clk_ok;
+ DEBUG_OUT(4) <= adc_clk_ok_last;
+ DEBUG_OUT(5) <= adc_clk_skip;
+ DEBUG_OUT(6) <= nx_data_clock_ok;
+ DEBUG_OUT(7) <= data_handler_reset;
+ DEBUG_OUT(8) <= pll_adc_not_lock;
+ DEBUG_OUT(9) <= adc_reset_sync_s;
+ DEBUG_OUT(10) <= adc_reset_sync;
+ DEBUG_OUT(11) <= reset_adc_handler_r;
+ DEBUG_OUT(12) <= ADC_RESET_AD9228;
+ DEBUG_OUT(13) <= sampling_clk_reset;
+ DEBUG_OUT(14) <= adc_reset_p;
+ DEBUG_OUT(15) <= '0';
- when "100" =>
+ when "011" =>
+ -- Test Channel
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= nx_new_frame;
DEBUG_OUT(2) <= TRIGGER_IN;
DEBUG_OUT(3) <= adc_data_valid;
DEBUG_OUT(15 downto 4) <= test_adc_data;
- when "011" =>
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= reset_adc_handler;
- DEBUG_OUT(2) <= TRIGGER_IN;
- DEBUG_OUT(3) <= adc_clk_ok;
- DEBUG_OUT(4) <= adc_clk_ok_last;
- DEBUG_OUT(5) <= adc_clk_skip;
- DEBUG_OUT(6) <= sampling_clk_reset;
- DEBUG_OUT(7) <= adc_reset;
- DEBUG_OUT(8) <= r_wait_timer_done;
- DEBUG_OUT(9) <= reset_adc_handler_r;
- DEBUG_OUT(10) <= nx_new_frame;
- DEBUG_OUT(11) <= nx_data_clock_ok;
- DEBUG_OUT(12) <= data_handler_reset;
- DEBUG_OUT(13) <= pll_adc_not_lock;
- DEBUG_OUT(14) <= '0';
- DEBUG_OUT(15) <= '0';
-
- --DEBUG_OUT(15 downto 11) <= adc_reset_ctr(4 downto 0) ;
-
- when others =>
+ when others =>
+ -- Default
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= TRIGGER_IN;
DEBUG_OUT(2) <= nx_fifo_full;
DEBUG_OUT(8) <= adc_data_valid;
DEBUG_OUT(9) <= nx_new_timestamp;
DEBUG_OUT(10) <= adc_new_data;
--- DEBUG_OUT(12 downto 11) <= STATE_d;
DEBUG_OUT(11) <= nx_fifo_reset;
DEBUG_OUT(12) <= '0';
DEBUG_OUT(13) <= nx_new_frame;
end case;
end process PROC_DEBUG_MULT;
+
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
+ signal_async_trans_RESET_IN: signal_async_trans
+ port map (
+ CLK_IN => NX_TIMESTAMP_CLK_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_NX_TIMESTAMP_CLK_IN
+ );
+
+ signal_async_trans_RESET_IN_2: signal_async_trans
+ port map (
+ CLK_IN => NX_DATA_CLK_TEST_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_NX_DATA_CLK_TEST_IN
+ );
-----------------------------------------------------------------------------
-- Check NX Data Clk
PROC_COUNTER_NX_CLOCK: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if( RESET_IN = '1' ) then
+ if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
counter_nx_domain <= (others => '0');
else
counter_nx_domain <= counter_nx_domain + 1;
PROC_COUNTER_NX_REF_CLOCK: process(NX_DATA_CLK_TEST_IN)
begin
if (rising_edge(NX_DATA_CLK_TEST_IN) ) then
- if( RESET_IN = '1' ) then
+ if (NX_DATA_CLK_TEST_IN = '1') then
counter_nx_ref_domain <= (others => '0');
else
counter_nx_ref_domain <= counter_nx_ref_domain + 1;
signal_async_trans_2: signal_async_trans
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => not pll_adc_sampling_clk_lock,
SIGNAL_OUT => pll_adc_not_lock
);
end if;
end process PROC_PLL_LOCK_COUNTER;
-
- adc_reset_h <= RESET_IN or adc_reset;
+ ADC_RESET_AD9228 <= RESET_IN or adc_reset_p;
adc_ad9228_1: adc_ad9228
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => ADC_RESET_AD9228,
CLK_ADCDAT_IN => ADC_CLK_DAT_IN,
- RESTART_IN => adc_reset_h,
ADC0_SCLK_IN => pll_adc_sampling_clk_o,
ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT,
ERROR_ADC0_OUT => error_adc0,
ERROR_ADC1_OUT => error_adc1,
+ DEBUG_IN => adc_debug_type,
DEBUG_OUT => ADC_DEBUG
);
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
+ generic map (
+ CTR_WIDTH => 28,
+ CTR_END => 1000000 -- 1ms
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TIMER_START_IN => r1_wait_timer_start,
+ TIMER_DONE_OUT => r1_wait_timer_done
+ );
+
+ timer_static_2: timer_static
generic map (
- CTR_WIDTH => 28
+ CTR_WIDTH => 28,
+ CTR_END => 50000000 -- 50ms
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => r_wait_timer_init,
- TIMER_DONE_OUT => r_wait_timer_done
+ TIMER_START_IN => r2_wait_timer_start,
+ TIMER_DONE_OUT => r2_wait_timer_done
);
- reset_adc_handler <= '0';
+
+ pulse_dtrans_1: pulse_dtrans
+ generic map (
+ CLK_RATIO => 4
+ )
+ port map (
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ PULSE_A_IN => adc_reset_sync_s,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => adc_reset_sync
+ );
PROC_RESET_HANDLER: process(CLK_IN)
begin
sampling_clk_reset_p <= '0';
adc_reset_p <= '0';
data_handler_reset_p <= '0';
- r_wait_timer_init <= x"00f_4240"; -- 1ms to settle down
+ r1_wait_timer_start <= '0';
+ r2_wait_timer_start <= '0';
reset_handler_counter <= (others => '0');
R_STATE <= R_PLL_RESET;
else
sampling_clk_reset_p <= '0';
adc_reset_p <= '0';
data_handler_reset_p <= '0';
- r_wait_timer_init <= (others => '0');
-
+ r1_wait_timer_start <= '0';
+ r2_wait_timer_start <= '0';
+
if (reset_handler_counter_clear = '1') then
reset_handler_counter <= (others => '0');
end if;
case R_STATE is
when R_IDLE =>
- if (reset_adc_handler = '1' or
- reset_adc_handler_r = '1' or
- pll_adc_not_lock = '1') then
- r_wait_timer_init <= x"00f_4240"; -- 1ms to settle down
+ if (reset_adc_handler_r = '1' or
+ pll_adc_not_lock = '1' or
+ adc_reset_sync = '1') then
+ r1_wait_timer_start <= '1'; -- 1ms to settle down
R_STATE <= R_PLL_RESET;
else
R_STATE <= R_IDLE;
if (reset_handler_counter_clear = '0') then
reset_handler_counter <= reset_handler_counter + 1;
end if;
- if (r_wait_timer_done = '0') then
+ if (r1_wait_timer_done = '0') then
R_STATE <= R_WAIT_RESET_ADC;
else
sampling_clk_reset_p <= '1';
if (pll_adc_not_lock = '1') then
R_STATE <= R_PLL_WAIT_LOCK;
else
- r_wait_timer_init <= x"2fa_f080"; -- 50ms
+ r2_wait_timer_start <= '1'; -- 50ms
R_STATE <= R_WAIT_RESET_ADC;
end if;
-
+
when R_WAIT_RESET_ADC =>
- if (r_wait_timer_done = '0') then
+ if (r2_wait_timer_done = '0') then
R_STATE <= R_WAIT_RESET_ADC;
else
adc_reset_p <= '1';
- r_wait_timer_init <= x"2fa_f080"; -- 50ms
+ r2_wait_timer_start <= '1'; -- 50ms
R_STATE <= R_WAIT_ADC_SETTLED;
end if;
when R_WAIT_ADC_SETTLED =>
- if (r_wait_timer_done = '0') then
+ if (r2_wait_timer_done = '0') then
R_STATE <= R_WAIT_ADC_SETTLED;
else
- data_handler_reset_p <= '1';
- r_wait_timer_init <= x"00f_4240"; -- 1ms
+ data_handler_reset_p <= '1';
+ r1_wait_timer_start <= '1'; -- 1ms
R_STATE <= R_WAIT_RESET_DATA_HANDLER;
end if;
when R_WAIT_RESET_DATA_HANDLER =>
- if (r_wait_timer_done = '0') then
+ if (r1_wait_timer_done = '0') then
R_STATE <= R_WAIT_RESET_DATA_HANDLER;
else
R_STATE <= R_IDLE;
LEVEL_OUT => sampling_clk_reset
);
- pulse_to_level_ADC_RESET: pulse_to_level
- generic map (
- NUM_CYCLES => 5
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- PULSE_IN => adc_reset_p,
- LEVEL_OUT => adc_reset
- );
-
pulse_to_level_DATA_HANDLER_RESET: pulse_to_level
generic map (
NUM_CYCLES => 5
PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if( RESET_IN = '1' ) then
+ if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
frame_byte_ctr <= (others => '0');
nx_frame_word <= (others => '0');
nx_timestamp_ff <= (others => '0');
PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if( RESET_IN = '1' ) then
+ if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
frame_byte_pos <= "11";
rs_sync_set <= '0';
rs_sync_reset <= '0';
PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if (RESET_IN = '1' or rs_sync_reset = '1') then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1' or rs_sync_reset = '1') then
nx_frame_synced <= '0';
elsif (rs_sync_set = '1') then
nx_frame_synced <= '1';
variable parity : std_logic;
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if (RESET_IN = '1') then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
parity_error <= '0';
else
parity_error <= '0';
PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if(RESET_IN = '1' ) then
+ if(RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
nx_clk_active_ff_0 <= '0';
nx_clk_active_ff_1 <= '0';
nx_clk_active_ff_2 <= '0';
PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (RESET_IN = '1') then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
johnson_ff_0 <= '0';
johnson_ff_1 <= '0';
else
variable adc_clk_state : std_logic_vector(1 downto 0);
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (RESET_IN = '1') then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
adc_clk_skip <= '0';
adc_clk_ok <= '0';
else
PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (RESET_IN = '1') then
- adc_clk_ok_last <= '0';
- adc_reset_s <= '0';
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ adc_clk_ok_last <= '0';
+ adc_reset_sync_s <= '0';
else
- adc_reset_s <= '0';
- adc_clk_ok_last <= adc_clk_ok;
+ adc_reset_sync_s <= '0';
+ adc_clk_ok_last <= adc_clk_ok;
if (adc_clk_ok_last = '0' and adc_clk_ok = '1') then
- adc_reset_s <= '1';
+ adc_reset_sync_s <= '1';
end if;
end if;
end if;
end process PROC_ADC_RESET;
- PROC_RESET_CTR: process(NX_TIMESTAMP_CLK_IN)
+ PROC_RESET_CTR: process(CLK_IN)
begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
+ if (rising_edge(CLK_IN)) then
if (RESET_IN = '1') then
adc_reset_ctr <= (others => '0');
else
- if (adc_reset = '1') then
+ if (adc_reset_p = '1') then
adc_reset_ctr <= adc_reset_ctr + 1;
end if;
end if;
)
port map (
CLK_A_IN => NX_TIMESTAMP_CLK_IN,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
PULSE_A_IN => rs_sync_reset,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
)
port map (
CLK_A_IN => NX_TIMESTAMP_CLK_IN,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
PULSE_A_IN => parity_error,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
signal_async_trans_1: signal_async_trans
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => nx_frame_synced,
SIGNAL_OUT => reg_nx_frame_synced
);
reset_adc_handler_r <= '0';
reset_handler_counter_clear <= '0';
adc_bit_shift <= x"0";
+ adc_debug_type <= (others => '0');
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(31 downto 0) <= (others => '0');
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"000a" =>
reset_adc_handler_r <= '1';
slv_ack_o <= '1';
+ when x"0013" =>
+ debug_adc <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
+
when x"000b" =>
reset_adc_handler_r <= '1';
slv_ack_o <= '1';
unsigned(SLV_DATA_IN(3 downto 0));
slv_ack_o <= '1';
- when x"0013" =>
- debug_adc <= SLV_DATA_IN(2 downto 0);
- slv_ack_o <= '1';
+ when x"001f" =>
+ adc_debug_type <=
+ unsigned(SLV_DATA_IN(3 downto 0));
+ slv_unknown_addr_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
nx_frame_ctr_t <= nx_frame_ctr_t + 1;
end if;
if (pileup_rate_inc = '1') then
- nx_pileup_ctr_t <= nx_trigger_ctr_t + 1;
+ nx_pileup_ctr_t <= nx_pileup_ctr_t + 1;
end if;
if (overflow_rate_inc = '1') then
- nx_overflow_ctr_t <= nx_frame_ctr_t + 1;
+ nx_overflow_ctr_t <= nx_overflow_ctr_t + 1;
end if;
nx_rate_timer <= nx_rate_timer + 1;
else
std_logic_vector(adc_average_divisor);
slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
+
+ when x"0009" =>
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_pileup_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000a" =>
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_overflow_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
end entity;
architecture Behavioral of nx_fpga_timestamp is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_FPGA_TIMESTAMP is";
-
+
signal timestamp_ctr : unsigned(11 downto 0);
signal timestamp_current_o : unsigned(11 downto 0);
signal timestamp_hold_o : std_logic_vector(11 downto 0);
- signal trigger : std_logic;
+ signal timestamp_trigger_o : std_logic;
signal timestamp_sync : std_logic;
signal timestamp_synced : std_logic;
signal fifo_full : std_logic;
signal fifo_write_enable : std_logic;
+ -- Reset
+ signal RESET_NX_MAIN_CLK_IN : std_logic;
+
begin
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= TIMESTAMP_SYNC_IN;
DEBUG_OUT(2) <= timestamp_synced_o;
DEBUG_OUT(3) <= TRIGGER_IN;
- DEBUG_OUT(4) <= trigger;
- DEBUG_OUT(15 downto 5) <= timestamp_hold_o(10 downto 0);
-
+ DEBUG_OUT(15 downto 4) <= timestamp_hold_o(11 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
+ signal_async_trans_RESET_IN: signal_async_trans
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_NX_MAIN_CLK_IN
+ );
+
-----------------------------------------------------------------------------
-- NX Clock Domain
-----------------------------------------------------------------------------
- -- signal_async_to_pulse_1: signal_async_to_pulse
- -- port map (
- -- CLK_IN => NX_MAIN_CLK_IN,
- -- RESET_IN => RESET_IN,
- -- PULSE_A_IN => TRIGGER_IN,
- -- PULSE_OUT => trigger
- -- );
- trigger <= TRIGGER_IN;
-
signal_async_to_pulse_TIMESTAMP_SYNC_IN: signal_async_to_pulse
+ generic map (
+ NUM_FF => 3
+ )
port map (
CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
PULSE_A_IN => TIMESTAMP_SYNC_IN,
PULSE_OUT => timestamp_sync
);
PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
- if( RESET_IN = '1' ) then
- timestamp_ctr <= (others => '0');
- timestamp_hold_o <= (others => '0');
- timestamp_synced <= '0';
+ if( RESET_NX_MAIN_CLK_IN = '1' ) then
+ timestamp_ctr <= (others => '0');
+ timestamp_hold_o <= (others => '0');
+ timestamp_synced <= '0';
else
- timestamp_synced <= '0';
+ timestamp_trigger_o <= '1';
+ timestamp_synced <= '0';
+
if (timestamp_sync = '1') then
- timestamp_ctr <= (others => '0');
- timestamp_synced <= '1';
+ timestamp_ctr <= (others => '0');
+ timestamp_synced <= '1';
else
- if (trigger = '1') then
- timestamp_hold_o <= std_logic_vector(timestamp_ctr);
+ if (TRIGGER_IN = '1') then
+ timestamp_hold_o <= std_logic_vector(timestamp_ctr);
+ timestamp_trigger_o <= '1';
end if;
- timestamp_ctr <= timestamp_ctr + 1;
+ timestamp_ctr <= timestamp_ctr + 1;
end if;
end if;
end if;
)
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_NX_MAIN_CLK_IN,
PULSE_A_IN => timestamp_synced,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
TIMESTAMP_CURRENT_OUT <= timestamp_current_o;
TIMESTAMP_HOLD_OUT <= timestamp_hold_o;
TIMESTAMP_SYNCED_OUT <= timestamp_synced_o;
- TIMESTAMP_TRIGGER_OUT <= trigger;
+ TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o;
end Behavioral;
end entity;
architecture Behavioral of nx_histogram is
-
+
-- Hist Fill/Ctr Handler
type H_STATES is (H_IDLE,
H_WRITEADD_CHANNEL,
slv_ack_o <= '0';
elsif (unsigned(SLV_ADDR_IN) >= x"0100" and
unsigned(SLV_ADDR_IN) <= x"017f") then
- ovfl_read_id <= SLV_ADDR_IN(6 downto 0);
- ovfl_read <= '1';
+ pileup_read_id <= SLV_ADDR_IN(6 downto 0);
+ pileup_read <= '1';
slv_ack_o <= '0';
elsif (unsigned(SLV_ADDR_IN) >= x"0200" and
unsigned(SLV_ADDR_IN) <= x"027f") then
- pileup_read_id <= SLV_ADDR_IN(6 downto 0);
- pileup_read <= '1';
+ ovfl_read_id <= SLV_ADDR_IN(6 downto 0);
+ ovfl_read <= '1';
slv_ack_o <= '0';
elsif (unsigned(SLV_ADDR_IN) >= x"0300" and
unsigned(SLV_ADDR_IN) <= x"037f") then
architecture Behavioral of nx_i2c_readbyte is
-- Send Byte
- signal sda_o : std_logic;
- signal scl_o : std_logic;
- signal i2c_start : std_logic;
-
- signal sequence_done_o : std_logic;
- signal i2c_data : unsigned(31 downto 0);
- signal bit_ctr : unsigned(3 downto 0);
- signal i2c_ack_o : std_logic;
- signal byte_ctr : unsigned(2 downto 0);
- signal wait_timer_init : unsigned(11 downto 0);
-
- signal sequence_done_o_x : std_logic;
- signal i2c_data_x : unsigned(31 downto 0);
- signal bit_ctr_x : unsigned(3 downto 0);
- signal i2c_ack_o_x : std_logic;
- signal byte_ctr_x : unsigned(2 downto 0);
- signal wait_timer_init_x : unsigned(11 downto 0);
+ signal sda_o : std_logic;
+ signal scl_o : std_logic;
+ signal i2c_start : std_logic;
+
+ signal sequence_done_o : std_logic;
+ signal i2c_data : unsigned(31 downto 0);
+ signal bit_ctr : unsigned(3 downto 0);
+ signal i2c_ack_o : std_logic;
+ signal byte_ctr : unsigned(2 downto 0);
+ signal wait_timer_start : std_logic;
+ signal wait_timer_init : unsigned(11 downto 0);
+
+ signal sequence_done_o_x : std_logic;
+ signal i2c_data_x : unsigned(31 downto 0);
+ signal bit_ctr_x : unsigned(3 downto 0);
+ signal i2c_ack_o_x : std_logic;
+ signal byte_ctr_x : unsigned(2 downto 0);
+ signal wait_timer_start_x : std_logic;
+ signal wait_timer_init_x : unsigned(11 downto 0);
type STATES is (S_IDLE,
S_INIT,
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_1: timer
generic map(
CTR_WIDTH => 12
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
bit_ctr <= (others => '0');
i2c_ack_o <= '0';
byte_ctr <= (others => '0');
+ wait_timer_start <= '0';
wait_timer_init <= (others => '0');
STATE <= S_IDLE;
else
bit_ctr <= bit_ctr_x;
i2c_ack_o <= i2c_ack_o_x;
byte_ctr <= byte_ctr_x;
+ wait_timer_start <= wait_timer_start_x;
wait_timer_init <= wait_timer_init_x;
STATE <= NEXT_STATE;
end if;
bit_ctr_x <= bit_ctr;
i2c_ack_o_x <= i2c_ack_o;
byte_ctr_x <= byte_ctr;
- wait_timer_init_x <= (others => '0');
-
+ wait_timer_init_x <= wait_timer_init;
+ wait_timer_start_x <= '0';
+
case STATE is
when S_IDLE =>
if (START_IN = '1') then
when S_INIT =>
sda_o <= '0';
scl_o <= '0';
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 1;
NEXT_STATE <= S_INIT_WAIT;
scl_o <= '0';
bit_ctr_x <= x"7";
byte_ctr_x <= byte_ctr + 1;
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_UNSET_SCL1;
if (wait_timer_done = '0') then
NEXT_STATE <= S_UNSET_SCL1;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
+ wait_timer_start_x <= '1';
+ wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_SET_SCL1;
end if;
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SCL1;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_GET_BIT;
end if;
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SCL2;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_UNSET_SCL2;
end if;
scl_o <= '0';
if (bit_ctr > 0) then
bit_ctr_x <= bit_ctr - 1;
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_UNSET_SCL1;
else
if (byte_ctr < NUM_BYTES_IN) then
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_SET;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_NACK_SET;
end if;
-- I2C Send ACK (ACK) Sequence to tell client to read next byte
when S_ACK_SET =>
- sda_o <= '0';
- scl_o <= '0';
+ sda_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_ACK_SET;
+ NEXT_STATE <= S_ACK_SET;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_ACK_SET_SCL;
+ wait_timer_start_x <= '1';
+ wait_timer_init_x <= I2C_SPEED srl 1;
+ NEXT_STATE <= S_ACK_SET_SCL;
end if;
when S_ACK_SET_SCL =>
- sda_o <= '0';
+ sda_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_ACK_SET_SCL;
+ NEXT_STATE <= S_ACK_SET_SCL;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_ACK_UNSET_SCL;
+ wait_timer_start_x <= '1';
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_ACK_UNSET_SCL;
end if;
when S_ACK_UNSET_SCL =>
- sda_o <= '0';
- scl_o <= '0';
+ sda_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_ACK_UNSET_SCL;
+ NEXT_STATE <= S_ACK_UNSET_SCL;
else
- NEXT_STATE <= S_READ_BYTE;
+ NEXT_STATE <= S_READ_BYTE;
end if;
-- I2C Send NOT_ACK (NACK) Sequence to tell client to release the bus
when S_NACK_SET =>
- scl_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_SET;
+ NEXT_STATE <= S_NACK_SET;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_NACK_SET_SCL;
+ wait_timer_start_x <= '1';
+ wait_timer_init_x <= I2C_SPEED srl 1;
+ NEXT_STATE <= S_NACK_SET_SCL;
end if;
when S_NACK_SET_SCL =>
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_SET_SCL;
+ NEXT_STATE <= S_NACK_SET_SCL;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_NACK_UNSET_SCL;
+ wait_timer_start_x <= '1';
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_NACK_UNSET_SCL;
end if;
when S_NACK_UNSET_SCL =>
- scl_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_UNSET_SCL;
+ NEXT_STATE <= S_NACK_UNSET_SCL;
else
- sequence_done_o_x <= '1';
- NEXT_STATE <= S_IDLE;
+ sequence_done_o_x <= '1';
+ NEXT_STATE <= S_IDLE;
end if;
end case;
architecture Behavioral of nx_i2c_sendbyte is
-- Send Byte
- signal sda_o : std_logic;
- signal scl_o : std_logic;
- signal i2c_start : std_logic;
+ signal sda_o : std_logic;
+ signal scl_o : std_logic;
+ signal i2c_start : std_logic;
- signal sequence_done_o : std_logic;
- signal i2c_byte : unsigned(7 downto 0);
- signal bit_ctr : unsigned(3 downto 0);
- signal i2c_ack_o : std_logic;
- signal wait_timer_init : unsigned(11 downto 0);
- signal stretch_timeout : unsigned(19 downto 0);
+ signal sequence_done_o : std_logic;
+ signal i2c_byte : unsigned(7 downto 0);
+ signal bit_ctr : unsigned(3 downto 0);
+ signal i2c_ack_o : std_logic;
+ signal wait_timer_start : std_logic;
+ signal wait_timer_init : unsigned(11 downto 0);
+ signal stretch_timeout : unsigned(19 downto 0);
- signal sequence_done_o_x : std_logic;
- signal i2c_byte_x : unsigned(7 downto 0);
- signal bit_ctr_x : unsigned(3 downto 0);
- signal i2c_ack_o_x : std_logic;
- signal wait_timer_init_x : unsigned(11 downto 0);
- signal stretch_timeout_x : unsigned(19 downto 0);
+ signal sequence_done_o_x : std_logic;
+ signal i2c_byte_x : unsigned(7 downto 0);
+ signal bit_ctr_x : unsigned(3 downto 0);
+ signal i2c_ack_o_x : std_logic;
+ signal wait_timer_start_x : std_logic;
+ signal wait_timer_init_x : unsigned(11 downto 0);
+ signal stretch_timeout_x : unsigned(19 downto 0);
type STATES is (S_IDLE,
S_INIT,
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_1: timer
generic map (
CTR_WIDTH => 12
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
sequence_done_o <= '0';
bit_ctr <= (others => '0');
i2c_ack_o <= '0';
+ wait_timer_start <= '0';
wait_timer_init <= (others => '0');
stretch_timeout <= (others => '0');
STATE <= S_IDLE;
i2c_byte <= i2c_byte_x;
bit_ctr <= bit_ctr_x;
i2c_ack_o <= i2c_ack_o_x;
+ wait_timer_start <= wait_timer_start_x;
wait_timer_init <= wait_timer_init_x;
stretch_timeout <= stretch_timeout_x;
STATE <= NEXT_STATE;
i2c_byte_x <= i2c_byte;
bit_ctr_x <= bit_ctr;
i2c_ack_o_x <= i2c_ack_o;
- wait_timer_init_x <= (others => '0');
+ wait_timer_start_x <= '0';
+ wait_timer_init_x <= wait_timer_init;
stretch_timeout_x <= stretch_timeout;
case STATE is
when S_INIT =>
sda_o <= '0';
scl_o <= '0';
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 1;
NEXT_STATE <= S_INIT_WAIT;
sda_o <= '0';
scl_o <= '0';
bit_ctr_x <= x"7";
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_SET_SDA;
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SDA;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 1;
NEXT_STATE <= S_SET_SCL;
end if;
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SCL;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_UNSET_SCL;
end if;
if (bit_ctr > 0) then
bit_ctr_x <= bit_ctr - 1;
i2c_byte_x <= i2c_byte sll 1;
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_SET_SDA;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_UNSET_SCL;
end if;
if (wait_timer_done = '0') then
NEXT_STATE <= S_ACK_UNSET_SCL;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_SET_SCL;
end if;
-- Check for Clock Stretching
when S_STRETCH_CHECK_SCL =>
if (SCL_IN = '1') then
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_STORE;
else
NEXT_STATE <= S_STRETCH_WAIT_SCL;
else
i2c_ack_o_x <= '0';
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_UNSET_SCL;
end if;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_STRETCH_PAUSE;
end if;
if (wait_timer_done = '0') then
NEXT_STATE <= S_STRETCH_PAUSE;
else
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_STORE;
end if;
NEXT_STATE <= S_ACK_STORE;
else
i2c_ack_o_x <= not SDA_IN;
+ wait_timer_start_x <= '1';
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_ACK_UNSET_SCL2;
end if;
architecture Behavioral of nx_i2c_startstop is
-- I2C Bus
- signal sda_o : std_logic;
- signal scl_o : std_logic;
- signal sequence_done_o : std_logic;
- signal wait_timer_init : unsigned(11 downto 0);
+ signal sda_o : std_logic;
+ signal scl_o : std_logic;
+ signal sequence_done_o : std_logic;
+ signal wait_timer_start : std_logic;
- signal sequence_done_o_x : std_logic;
- signal wait_timer_init_x : unsigned(11 downto 0);
+ signal wait_timer_start_x : std_logic;
+ signal sequence_done_o_x : std_logic;
type STATES is (S_IDLE,
S_START,
begin
-- Timer
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 12
+ CTR_WIDTH => 12,
+ CTR_END => to_integer(I2C_SPEED srl 1)
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
TIMER_DONE_OUT => wait_timer_done
);
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
+ wait_timer_start <= '0';
sequence_done_o <= '0';
- wait_timer_init <= (others => '0');
STATE <= S_IDLE;
else
+ wait_timer_start <= wait_timer_start_x;
sequence_done_o <= sequence_done_o_x;
- wait_timer_init <= wait_timer_init_x;
STATE <= NEXT_STATE;
end if;
end if;
wait_timer_done
)
begin
- sda_o <= '1';
- scl_o <= '1';
- wait_timer_init_x <= (others => '0');
- sequence_done_o_x <= '0';
+ sda_o <= '1';
+ scl_o <= '1';
+ sequence_done_o_x <= '0';
+ wait_timer_start_x <= '0';
case STATE is
when S_IDLE =>
-- I2C START Sequence
when S_START =>
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_START_1;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_START_1;
when S_WAIT_START_1 =>
if (wait_timer_done = '0') then
- NEXT_STATE <= S_WAIT_START_1;
+ NEXT_STATE <= S_WAIT_START_1;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_START_2;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_START_2;
end if;
when S_WAIT_START_2 =>
- sda_o <= '0';
+ sda_o <= '0';
if (wait_timer_done = '0') then
NEXT_STATE <= S_WAIT_START_2;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_START_3;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_START_3;
end if;
when S_WAIT_START_3 =>
- sda_o <= '0';
- scl_o <= '0';
+ sda_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_WAIT_START_3;
+ NEXT_STATE <= S_WAIT_START_3;
else
- sequence_done_o_x <= '1';
- NEXT_STATE <= S_IDLE;
+ sequence_done_o_x <= '1';
+ NEXT_STATE <= S_IDLE;
end if;
-- I2C STOP Sequence
when S_STOP =>
- sda_o <= '0';
- scl_o <= '0';
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_STOP_1;
+ sda_o <= '0';
+ scl_o <= '0';
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_STOP_1;
when S_WAIT_STOP_1 =>
- sda_o <= '0';
- scl_o <= '0';
+ sda_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_WAIT_STOP_1;
+ NEXT_STATE <= S_WAIT_STOP_1;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_STOP_2;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_STOP_2;
end if;
when S_WAIT_STOP_2 =>
- sda_o <= '0';
+ sda_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_WAIT_STOP_2;
+ NEXT_STATE <= S_WAIT_STOP_2;
else
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_WAIT_STOP_3;
+ wait_timer_start_x <= '1';
+ NEXT_STATE <= S_WAIT_STOP_3;
end if;
when S_WAIT_STOP_3 =>
architecture Behavioral of nx_setup is
---attribute HGROUP : string;
---attribute HGROUP of Behavioral : architecture is "SLAVE_BUS_NX_SETUP";
-
-- I2C Command Multiplexer
signal i2c_lock_0 : std_logic;
signal i2c_lock_1 : std_logic;
signal R_STATE : R_STATES;
- signal wait_timer_init : unsigned(31 downto 0);
+ signal wait_timer_start : std_logic;
signal wait_timer_done : std_logic;
signal i2c_online_command : std_logic_vector(31 downto 0);
signal i2c_lock_3_clear : std_logic;
signal int_ack_o : std_logic;
-- TRBNet Slave Bus
- signal slv_read : std_logic;
- signal slv_write : std_logic;
- signal slv_addr : std_logic_vector(15 downto 0);
- signal slv_data : std_logic_vector(31 downto 0);
-
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal nxyter_testchannels : std_logic_vector(2 downto 0);
signal i2c_update_memory_r : std_logic;
- -- Buffer
- signal slv_data_out_o_b : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o_b : std_logic;
- signal slv_unknown_addr_o_b : std_logic;
- signal slv_ack_o_b : std_logic;
-
begin
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
DEBUG_OUT(0) <= CLK_IN;
--- DEBUG_OUT(1) <= I2C_COMMAND_BUSY_IN;
--- DEBUG_OUT(2) <= i2c_command_busy_o;
--- DEBUG_OUT(3) <= i2c_error;
--- DEBUG_OUT(4) <= i2c_command_done;
--- DEBUG_OUT(5) <= next_token_dac_r or
--- next_token_dac_w;
--- DEBUG_OUT(6) <= i2c_update_memory;
--- DEBUG_OUT(7) <= i2c_lock_0_clear;
--- DEBUG_OUT(8) <= i2c_lock_1_clear;
--- DEBUG_OUT(9) <= i2c_lock_2_clear;
--- DEBUG_OUT(10) <= i2c_lock_4_clear;
--- DEBUG_OUT(11) <= i2c_online_o;
--- DEBUG_OUT(12) <= i2c_lock_0;
--- DEBUG_OUT(13) <= i2c_lock_1;
--- DEBUG_OUT(14) <= i2c_lock_2;
--- DEBUG_OUT(15) <= i2c_lock_4;
-
- DEBUG_OUT(2 downto 1) <= (others => '0');
- DEBUG_OUT(3) <= SLV_WRITE_IN;
- DEBUG_OUT(4) <= SLV_READ_IN;
- DEBUG_OUT(5) <= slv_no_more_data_o;
- DEBUG_OUT(6) <= slv_unknown_addr_o;
- DEBUG_OUT(7) <= slv_ack_o;
- DEBUG_OUT(15 downto 8) <= slv_data_out_o(7 downto 0);
+ DEBUG_OUT(1) <= I2C_COMMAND_BUSY_IN;
+ DEBUG_OUT(2) <= i2c_command_busy_o;
+ DEBUG_OUT(3) <= i2c_error;
+ DEBUG_OUT(4) <= i2c_command_done;
+ DEBUG_OUT(5) <= next_token_dac_r or
+ next_token_dac_w;
+ DEBUG_OUT(6) <= i2c_update_memory;
+ DEBUG_OUT(7) <= i2c_lock_0_clear;
+ DEBUG_OUT(8) <= i2c_lock_1_clear;
+ DEBUG_OUT(9) <= i2c_lock_2_clear;
+ DEBUG_OUT(10) <= i2c_lock_4_clear;
+ DEBUG_OUT(11) <= i2c_online_o;
+ DEBUG_OUT(12) <= i2c_lock_0;
+ DEBUG_OUT(13) <= i2c_lock_1;
+ DEBUG_OUT(14) <= i2c_lock_2;
+ DEBUG_OUT(15) <= i2c_lock_4;
-----------------------------------------------------------------------------
end process PROC_ADC_REGISTERS_HANDLER;
-----------------------------------------------------------------------------
-
- nx_timer_1: nx_timer
+
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 32
+ CTR_WIDTH => 32,
+ CTR_END => 500000000 --5S
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
TIMER_DONE_OUT => wait_timer_done
);
-
+
PROC_I2C_ONLINE: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
i2c_online_command <= (others => '0');
i2c_online_o <= '0';
i2c_lock_3_clear <= '0';
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
R_STATE <= R_TIMER_RESTART;
else
i2c_online_command <= (others => '0');
i2c_lock_3_clear <= '0';
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
case R_STATE is
when R_TIMER_RESTART =>
- wait_timer_init <= x"1dcd_6500"; -- 5s
+ wait_timer_start <= '1';
R_STATE <= R_IDLE;
when R_IDLE =>
variable index : integer := 0;
begin
if( rising_edge(CLK_IN) ) then
- -- Buffer input
- slv_read <= SLV_READ_IN;
- slv_write <= SLV_WRITE_IN;
- slv_addr <= SLV_ADDR_IN;
- slv_data <= SLV_DATA_IN;
-
if( RESET_IN = '1' ) then
slv_data_out_o <= (others => '0');
slv_no_more_data_o <= '0';
nxyter_testpulse <= (others => '0');
nxyter_testchannels <= (others => '0');
- if (slv_write = '1') then
- if (slv_addr >= x"0000" and slv_addr <= x"002d") then
- index := to_integer(unsigned(slv_addr(5 downto 0)));
+ if (SLV_WRITE_IN = '1') then
+ if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then
+ index := to_integer(unsigned(SLV_ADDR_IN(5 downto 0)));
if (i2c_disable_memory = '0') then
ram_index_0 <= index;
- ram_data_0 <= slv_data(7 downto 0);
+ ram_data_0 <= SLV_DATA_IN(7 downto 0);
ram_write_0 <= '1';
end if;
slv_ack_o <= '1';
- elsif (slv_addr >= x"0100" and slv_addr <= x"0180") then
+ elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then
-- Write value to ram
- index := to_integer(unsigned(slv_addr(7 downto 0)));
+ index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0)));
if (index = 0) then
index := 128;
else
if (i2c_disable_memory = '0') then
dac_ram_index_0 <= index;
- dac_ram_data_0 <= slv_data(5 downto 0);
+ dac_ram_data_0 <= SLV_DATA_IN(5 downto 0);
dac_ram_write_0 <= '1';
end if;
slv_ack_o <= '1';
else
- case slv_addr is
+ case SLV_ADDR_IN is
when x"0050" =>
-- Nxyter Clock
if (i2c_disable_memory = '0') then
- nxyter_clock(0) <= slv_data(0);
+ nxyter_clock(0) <= SLV_DATA_IN(0);
nxyter_clock(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0051" =>
-- Nxyter Polarity
if (i2c_disable_memory = '0') then
- nxyter_polarity(0) <= slv_data(0);
+ nxyter_polarity(0) <= SLV_DATA_IN(0);
nxyter_polarity(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0053" =>
-- Nxyter Testpulse
if (i2c_disable_memory = '0') then
- nxyter_testpulse(0) <= slv_data(0);
+ nxyter_testpulse(0) <= SLV_DATA_IN(0);
nxyter_testpulse(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0054" =>
-- Nxyter Testtrigger
if (i2c_disable_memory = '0') then
- nxyter_testtrigger(0) <= slv_data(0);
+ nxyter_testtrigger(0) <= SLV_DATA_IN(0);
nxyter_testtrigger(1) <= '1';
end if;
slv_ack_o <= '1';
when x"0055" =>
-- Nxyter Testtrigger
if (i2c_disable_memory = '0') then
- nxyter_testchannels(1 downto 0) <= slv_data(1 downto 0);
+ nxyter_testchannels(1 downto 0) <= SLV_DATA_IN(1 downto 0);
nxyter_testchannels(2) <= '1';
end if;
slv_ack_o <= '1';
end case;
end if;
- elsif (slv_read = '1') then
- if (slv_addr >= x"0000" and slv_addr <= x"002d") then
- index := to_integer(unsigned(slv_addr(5 downto 0)));
+ elsif (SLV_READ_IN = '1') then
+ if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then
+ index := to_integer(unsigned(SLV_ADDR_IN(5 downto 0)));
if (i2c_disable_memory = '0') then
slv_data_out_o(7 downto 0) <= i2c_ram(index);
slv_data_out_o(28 downto 8) <= (others => '0');
end if;
slv_ack_o <= '1';
- elsif (slv_addr >= x"0100" and slv_addr <= x"0180") then
- index := to_integer(unsigned(slv_addr(7 downto 0)));
+ elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then
+ index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0)));
if (index = 0) then
index := 128;
else
end if;
slv_ack_o <= '1';
- elsif (slv_addr >= x"0080" and slv_addr <= x"0083") then
- index := to_integer(unsigned(slv_addr(1 downto 0)));
+ elsif (SLV_ADDR_IN >= x"0080" and SLV_ADDR_IN <= x"0083") then
+ index := to_integer(unsigned(SLV_ADDR_IN(1 downto 0)));
if (i2c_disable_memory = '0') then
slv_data_out_o(12 downto 0) <= adc_ram(index);
slv_data_out_o(31 downto 13) <= (others => '0');
slv_ack_o <= '1';
else
- case slv_addr is
+ case SLV_ADDR_IN is
when x"0050" =>
-- Nxyter Clock
if (i2c_disable_memory = '0') then
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+use work.trb3_components.all;
+
+entity nx_status_event is
+ generic (
+ BOARD_ID : std_logic_vector(1 downto 0) := "11"
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NXYTER_OFFLINE_IN : in std_logic;
+
+ -- Trigger
+ TRIGGER_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+
+ --Response from FEE
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_ALMOST_FULL_IN : in std_logic;
+
+ -- Interface to NX Setup
+ INT_READ_OUT : out std_logic;
+ INT_ADDR_OUT : out std_logic_vector(15 downto 0);
+ INT_ACK_IN : in std_logic;
+ INT_DATA_IN : in std_logic_vector(31 downto 0);
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+
+end entity;
+
+architecture Behavioral of nx_status_event is
+
+ --Data channel
+ signal trigger_busy_o : std_logic;
+ signal event_write_start : std_logic;
+
+ type STATES is (S_IDLE,
+ S_EVT_WRITE_WAIT
+ );
+
+ signal STATE : STATES;
+
+ -- Event Write
+ type E_STATES is (E_IDLE,
+ E_READ_NEXT,
+ E_READ,
+ E_NEXT_INDEX,
+ E_END
+ );
+
+ signal E_STATE : E_STATES;
+
+ constant NUM_REGS : integer := 3;
+ type reg_addr_t is array(0 to NUM_REGS - 1) of std_logic_vector(15 downto 0);
+ constant reg_addr_start : reg_addr_t :=
+ (x"0000",
+ x"0100",
+ x"0080"
+ );
+ constant reg_addr_end : reg_addr_t :=
+ (x"002d",
+ x"0180",
+ x"0083"
+ );
+
+ signal index_ctr : unsigned(3 downto 0);
+ signal register_addr : unsigned(15 downto 0);
+ signal int_read_o : std_logic;
+ signal int_addr_o : std_logic_vector(15 downto 0);
+ signal fee_data_o : std_logic_vector(31 downto 0);
+ signal fee_data_write_o : std_logic;
+ signal event_write_done : std_logic;
+
+begin
+
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= TRIGGER_IN;
+ DEBUG_OUT(2) <= FAST_CLEAR_IN;
+ DEBUG_OUT(3) <= FEE_DATA_ALMOST_FULL_IN;
+ DEBUG_OUT(4) <= trigger_busy_o;
+ DEBUG_OUT(5) <= event_write_start;
+ DEBUG_OUT(6) <= event_write_done;
+ DEBUG_OUT(10 downto 7) <= index_ctr;
+ DEBUG_OUT(11) <= int_read_o;
+ DEBUG_OUT(12) <= INT_ACK_IN;
+ DEBUG_OUT(13) <= fee_data_write_o;
+ DEBUG_OUT(14) <= '0';
+ DEBUG_OUT(15) <= NXYTER_OFFLINE_IN;
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+
+ PROC_DATA_HANDLER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ event_write_start <= '0';
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ else
+ event_write_start <= '0';
+ trigger_busy_o <= '1';
+
+ if (FAST_CLEAR_IN = '1') then
+ STATE <= S_IDLE;
+ else
+ case STATE is
+ when S_IDLE =>
+ if (NXYTER_OFFLINE_IN = '1') then
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ elsif (TRIGGER_IN = '1') then
+ event_write_start <= '1';
+ STATE <= S_EVT_WRITE_WAIT;
+ else
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ end if;
+
+ when S_EVT_WRITE_WAIT =>
+ if (event_write_done = '0') then
+ STATE <= S_EVT_WRITE_WAIT;
+ else
+ STATE <= S_IDLE;
+ end if;
+
+ end case;
+ end if;
+ end if;
+ end if;
+ end process PROC_DATA_HANDLER;
+
+
+ PROC_WRITE_EVENT: process(CLK_IN)
+ variable index : integer := 0;
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ index_ctr <= (others => '0');
+ register_addr <= (others => '0');
+ int_read_o <= '0';
+ int_addr_o <= (others => '0');
+ fee_data_o <= (others => '0');
+ fee_data_write_o <= '0';
+ event_write_done <= '0';
+ E_STATE <= E_IDLE;
+ else
+ index := to_integer(index_ctr);
+ int_read_o <= '0';
+ int_addr_o <= (others => '0');
+ fee_data_o <= (others => '0');
+ fee_data_write_o <= '0';
+ event_write_done <= '0';
+
+ case E_STATE is
+ when E_IDLE =>
+ index_ctr <= (others => '0');
+ if (event_write_start = '1') then
+ E_STATE <= E_NEXT_INDEX;
+ else
+ E_STATE <= E_IDLE;
+ end if;
+
+ when E_READ_NEXT =>
+ if (register_addr <= unsigned(reg_addr_end(index))) then
+ int_addr_o <= register_addr;
+ int_read_o <= '1';
+ E_STATE <= E_READ;
+ else
+ index_ctr <= index_ctr + 1;
+ E_STATE <= E_NEXT_INDEX;
+ end if;
+
+ when E_READ =>
+ if (INT_ACK_IN = '1') then
+ fee_data_o(15 downto 0) <= INT_DATA_IN(15 downto 0);
+ fee_data_o(31 downto 16) <= register_addr;
+ fee_data_write_o <= '1';
+ register_addr <= register_addr + 1;
+ E_STATE <= E_READ_NEXT;
+ else
+ E_STATE <= E_READ;
+ end if;
+
+ when E_NEXT_INDEX =>
+ if (index_ctr < NUM_REGS) then
+ register_addr <= reg_addr_start(index);
+ E_STATE <= E_READ_NEXT;
+ else
+ E_STATE <= E_END;
+ end if;
+
+ when E_END =>
+ event_write_done <= '1';
+ E_STATE <= E_IDLE;
+
+ end case;
+ end if;
+ end if;
+ end process PROC_WRITE_EVENT;
+
+ -- Output Signals
+
+ TRIGGER_BUSY_OUT <= trigger_busy_o;
+ FEE_DATA_OUT <= fee_data_o;
+ FEE_DATA_WRITE_OUT <= fee_data_write_o;
+
+ INT_READ_OUT <= int_read_o;
+ INT_ADDR_OUT <= int_addr_o;
+
+end Behavioral;
end entity;
architecture Behavioral of nx_trigger_generator is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_GENERATOR";
-
- signal trigger_i : std_logic;
signal start_cycle : std_logic;
signal trigger_cycle_ctr : unsigned(7 downto 0);
- signal wait_timer_init : unsigned(15 downto 0);
+ signal wait_timer_start : std_logic;
+ signal wait_timer_init : unsigned(11 downto 0);
signal wait_timer_done : std_logic;
- signal wait_timer_done_i : std_logic;
signal trigger_o : std_logic;
signal ts_reset_o : std_logic;
signal testpulse_o : std_logic;
+ signal testpulse_o_b : std_logic;
+ signal testpulse_p : std_logic;
signal extern_trigger : std_logic;
type STATES is (S_IDLE,
signal testpulse_rate : unsigned(27 downto 0);
signal test_debug : std_logic;
+
+ -- Reset
+ signal RESET_NX_MAIN_CLK_IN : std_logic;
begin
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= '0';--TRIGGER_IN;
- DEBUG_OUT(2) <= '0';--trigger_i;
+ DEBUG_OUT(2) <= '0';
DEBUG_OUT(3) <= start_cycle;
- DEBUG_OUT(4) <= '0';--wait_timer_done_i;
+ DEBUG_OUT(4) <= '0';--wait_timer_done;
DEBUG_OUT(5) <= ts_reset_o;
- DEBUG_OUT(6) <= testpulse_o;
+ DEBUG_OUT(6) <= testpulse_o_b;
DEBUG_OUT(7) <= testpulse;
DEBUG_OUT(8) <= test_debug;
DEBUG_OUT(15 downto 9) <= (others => '0');
+
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
+ signal_async_trans_RESET_IN: signal_async_trans
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_NX_MAIN_CLK_IN
+ );
+
+ -----------------------------------------------------------------------------
PROC_TEST_DEBUG: process(CLK_IN)
begin
end process PROC_TEST_DEBUG;
-- Timer
- nx_timer_1: nx_timer
+ timer_1: timer
generic map (
- CTR_WIDTH => 16
+ CTR_WIDTH => 12
)
port map (
CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
+ wait_timer_init <= testpulse_length - 1;
-----------------------------------------------------------------------------
-- Generate Trigger
PROC_TESTPULSE_OUT: process(NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
- -- Relax timing by adding registers
- trigger_i <= TRIGGER_IN;
- wait_timer_done_i <= wait_timer_done;
-
- if (RESET_IN = '1') then
+ if (RESET_NX_MAIN_CLK_IN = '1') then
trigger_o <= '0';
testpulse_o <= '0';
+ testpulse_p <= '0';
ts_reset_o <= '0';
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
trigger_cycle_ctr <= (others => '0');
extern_trigger <= '0';
STATE <= S_IDLE;
else
trigger_o <= '0';
testpulse_o <= '0';
+ testpulse_p <= '0';
ts_reset_o <= '0';
- wait_timer_init <= (others => '0');
-
+ wait_timer_start <= '0';
+
case STATE is
when S_IDLE =>
- if (trigger_i = '1') then
+ if (TRIGGER_IN = '1') then
extern_trigger <= '1';
testpulse_o <= '1';
- if (testpulse_length > 1) then
- wait_timer_init(11 downto 0) <= testpulse_length - 2;
- wait_timer_init(15 downto 12) <= (others => '0');
+ testpulse_p <= '1';
+ if (testpulse_length > 0) then
+ wait_timer_start <= '1';
STATE <= S_WAIT_TESTPULSE_END;
else
STATE <= S_IDLE;
end if;
when S_WAIT_TESTPULSE_END =>
- if (wait_timer_done_i = '0') then
+ if (WAIT_TIMER_DONE = '0') then
testpulse_o <= '1';
STATE <= S_WAIT_TESTPULSE_END;
else
end if;
end process PROC_TESTPULSE_OUT;
- -- Transfer testpulse_o to CLK_IN Domain
- pulse_dtrans_1: pulse_dtrans
+ -- Transfer testpulse_p to CLK_IN Domain
+ pulse_dtrans_TESTPULSE: pulse_dtrans
generic map (
- CLK_RATIO => 4
+ CLK_RATIO => 6
)
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_IN,
- PULSE_A_IN => testpulse_o,
+ RESET_A_IN => RESET_NX_MAIN_CLK_IN,
+ PULSE_A_IN => testpulse_p,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
- PULSE_B_OUT => testpulse
+ PULSE_B_OUT => testpulse
);
PROC_CAL_RATES: process (CLK_IN)
rate_timer <= (others => '0');
else
if (rate_timer < x"5f5e100") then
- if ( testpulse = '1') then
+ if (testpulse = '1') then
testpulse_rate_t <= testpulse_rate_t + 1;
end if;
rate_timer <= rate_timer + 1;
)
port map (
CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
SIGNAL_A_IN => std_logic_vector(reg_testpulse_length),
unsigned(SIGNAL_OUT) => testpulse_length
);
-----------------------------------------------------------------------------
-- Output Signals
-----------------------------------------------------------------------------
+
+ -- Buffer for timing
+ testpulse_o_b <= testpulse_o when rising_edge(NX_MAIN_CLK_IN);
-- Trigger Output
TRIGGER_OUT <= trigger_o;
TS_RESET_OUT <= ts_reset_o;
- TESTPULSE_OUT <= testpulse_o;
+ TESTPULSE_OUT <= testpulse_o_b;
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
NX_MAIN_CLK_IN : in std_logic;
-
NXYTER_OFFLINE_IN : in std_logic;
--Input Triggers
TIMING_TRIGGER_IN : in std_logic; -- The raw timing Trigger Signal
LVL1_TRG_DATA_VALID_IN : in std_logic; -- Data Trigger is valid
LVL1_VALID_TIMING_TRG_IN : in std_logic; -- Timin Trigger is valid
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- calibration trigger w/o
- -- reference time
- LVL1_INVALID_TRG_IN : in std_logic; -- do fast clear
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- calib trigger w/o ref time
+ LVL1_INVALID_TRG_IN : in std_logic;
LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
VALID_TRIGGER_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_SETUP_OUT : out std_logic;
+ TRIGGER_STATUS_OUT : out std_logic;
FAST_CLEAR_OUT : out std_logic;
TRIGGER_BUSY_OUT : out std_logic;
end entity;
architecture Behavioral of nx_trigger_handler is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_HANDLER";
-- Timing Trigger Handler
constant NUM_FF : integer := 10;
signal timing_trigger_ff : std_logic_vector(NUM_FF - 1 downto 0);
signal timing_trigger_l : std_logic;
signal timing_trigger : std_logic;
- signal timing_trigger_i : std_logic;
signal timing_trigger_set : std_logic;
- signal timestamp_trigger : std_logic;
signal timestamp_trigger_o : std_logic;
signal invalid_timing_trigger_n : std_logic;
signal TS_STATE : TS_STATES;
signal ts_wait_timer_reset : std_logic;
- signal ts_wait_timer_reset_i : std_logic;
- signal ts_wait_timer_init : unsigned(7 downto 0);
+ signal ts_wait_timer_start : std_logic;
signal ts_wait_timer_done : std_logic;
- signal ts_wait_timer_done_i : std_logic;
-- Trigger Handler
signal valid_trigger_o : std_logic;
signal timing_trigger_o : std_logic;
- signal setup_trigger_o : std_logic;
+ signal status_trigger_o : std_logic;
signal fast_clear_o : std_logic;
signal trigger_busy_o : std_logic;
signal fee_data_o : std_logic_vector(31 downto 0);
signal fee_data_finished_o : std_logic;
signal fee_trg_release_o : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal send_testpulse_l : std_logic;
signal send_testpulse : std_logic;
type STATES is (S_IDLE,
signal trigger_testpulse_o : std_logic;
signal wait_timer_reset : std_logic;
- signal wait_timer_init : unsigned(11 downto 0);
+ signal wait_timer_start : std_logic;
signal wait_timer_done : std_logic;
-
- signal testpulse_delay : unsigned(11 downto 0);
- signal testpulse_enable : std_logic;
-- Rate Calculation
signal accepted_trigger_rate_t : unsigned(27 downto 0);
signal reg_testpulse_enable : std_logic;
signal accepted_trigger_rate : unsigned(27 downto 0);
signal invalid_t_trigger_ctr_clear : std_logic;
-
+
+ -- Reset
+ signal RESET_NX_MAIN_CLK_IN : std_logic;
+
begin
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= TIMING_TRIGGER_IN;
- DEBUG_OUT(2) <= invalid_timing_trigger; --timing_trigger_l;
+ DEBUG_OUT(2) <= invalid_timing_trigger;
DEBUG_OUT(3) <= LVL1_VALID_TIMING_TRG_IN;
DEBUG_OUT(4) <= LVL1_TRG_DATA_VALID_IN;
DEBUG_OUT(5) <= fee_data_write_o;
DEBUG_OUT(10) <= fee_data_finished_o;
DEBUG_OUT(11) <= fee_trg_release_o;
DEBUG_OUT(12) <= trigger_busy_o;
- DEBUG_OUT(13) <= timestamp_trigger;
+ DEBUG_OUT(13) <= timestamp_trigger_o;
DEBUG_OUT(14) <= send_testpulse;
DEBUG_OUT(15) <= trigger_testpulse_o;
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
+ signal_async_trans_RESET_IN: signal_async_trans
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ SIGNAL_A_IN => RESET_IN,
+ SIGNAL_OUT => RESET_NX_MAIN_CLK_IN
+ );
+
-----------------------------------------------------------------------------
-- Trigger Handler
-----------------------------------------------------------------------------
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
timing_trigger_ff_p(1) <= TIMING_TRIGGER_IN;
- if (RESET_IN = '1') then
+ if (RESET_NX_MAIN_CLK_IN = '1') then
timing_trigger_ff_p(0) <= '0';
timing_trigger_ff(NUM_FF - 1 downto 0) <= (others => '0');
timing_trigger_l <= '0';
level_to_pulse_1: level_to_pulse
port map (
CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
LEVEL_IN => timing_trigger_l,
PULSE_OUT => timing_trigger
);
-- Timer
- nx_timer_2: nx_timer
+ timer_static_2: timer_static
generic map (
- CTR_WIDTH => 8
+ CTR_WIDTH => 8,
+ CTR_END => 32 -- 128ns
)
port map (
CLK_IN => NX_MAIN_CLK_IN,
RESET_IN => ts_wait_timer_reset,
- TIMER_START_IN => ts_wait_timer_init,
+ TIMER_START_IN => ts_wait_timer_start,
TIMER_DONE_OUT => ts_wait_timer_done
);
PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
- timing_trigger_i <= timing_trigger;
- ts_wait_timer_done_i <= ts_wait_timer_done;
- ts_wait_timer_reset <= ts_wait_timer_reset_i;
- if (RESET_IN = '1' or fast_clear = '1') then
+ if (RESET_NX_MAIN_CLK_IN = '1') then
invalid_timing_trigger_n <= '1';
- ts_wait_timer_init <= (others => '0');
- ts_wait_timer_reset_i <= '1';
+ ts_wait_timer_start <= '0';
+ ts_wait_timer_reset <= '1';
send_testpulse <= '0';
- timestamp_trigger <= '0';
+ timestamp_trigger_o <= '0';
TS_STATE <= TS_IDLE;
else
invalid_timing_trigger_n <= '0';
- ts_wait_timer_init <= (others => '0');
- ts_wait_timer_reset_i <= '0';
+ ts_wait_timer_start <= '0';
+ ts_wait_timer_reset <= '0';
send_testpulse <= '0';
- timestamp_trigger <= '0';
-
- case TS_STATE is
- when TS_IDLE =>
- if (timing_trigger_i = '1') then
- if (trigger_busy = '0') then
- if (testpulse_enable = '1') then
- send_testpulse <= '1';
+ timestamp_trigger_o <= '0';
+
+ if (fast_clear = '1') then
+ ts_wait_timer_reset <= '1';
+ TS_STATE <= TS_IDLE;
+ else
+ case TS_STATE is
+ when TS_IDLE =>
+ -- Wait for Timing Trigger synced to NX_MAIN_CLK_DOMAIN
+ if (timing_trigger = '1') then
+ if (trigger_busy = '1') then
+ -- If busy is set --> Error
+ TS_STATE <= TS_INVALID_TRIGGER;
+ else
+ if (reg_testpulse_enable = '1') then
+ send_testpulse <= '1';
+ end if;
+ timestamp_trigger_o <= '1';
+ ts_wait_timer_start <= '1';
+ TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
end if;
- timestamp_trigger <= '1';
- ts_wait_timer_init <= x"20";
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
else
- TS_STATE <= TS_INVALID_TRIGGER;
+ TS_STATE <= TS_IDLE;
end if;
- else
- TS_STATE <= TS_IDLE;
- end if;
-
- when TS_WAIT_VALID_TIMING_TRIGGER =>
- if (trigger_busy = '1') then
- TS_STATE <= TS_WAIT_TRIGGER_END;
- else
- if (ts_wait_timer_done_i = '0') then
- ts_wait_timer_reset_i <= '1';
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
+
+ when TS_WAIT_VALID_TIMING_TRIGGER =>
+ -- Wait and test if CLK_IN Trigger Handler does accepted Trigger
+ if (trigger_busy = '1') then
+ -- Trigger has been accepted, stop timer and wait trigger end
+ ts_wait_timer_reset <= '1';
+ TS_STATE <= TS_WAIT_TRIGGER_END;
+ else
+ if (ts_wait_timer_done = '1') then
+ -- Timeout after 128ns --> Invalid Trigger Error
+ TS_STATE <= TS_INVALID_TRIGGER;
+ else
+ TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
+ end if;
+ end if;
+
+ when TS_INVALID_TRIGGER =>
+ invalid_timing_trigger_n <= '1';
+ TS_STATE <= TS_IDLE;
+
+ when TS_WAIT_TRIGGER_END =>
+ if (trigger_busy = '0') then
+ TS_STATE <= TS_IDLE;
else
- ts_wait_timer_reset_i <= '1';
- TS_STATE <= TS_INVALID_TRIGGER;
+ TS_STATE <= TS_WAIT_TRIGGER_END;
end if;
- end if;
-
- when TS_INVALID_TRIGGER =>
- invalid_timing_trigger_n <= '1';
- TS_STATE <= TS_IDLE;
-
- when TS_WAIT_TRIGGER_END =>
- if (trigger_busy = '0') then
- TS_STATE <= TS_IDLE;
- else
- TS_STATE <= TS_WAIT_TRIGGER_END;
- end if;
-
- end case;
+
+ end case;
+ end if;
end if;
end if;
end process PROC_TIMING_TRIGGER_HANDLER;
signal_async_trans_TRIGGER_BUSY: signal_async_trans
port map (
CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
SIGNAL_A_IN => trigger_busy_o,
SIGNAL_OUT => trigger_busy
);
- signal_async_trans_FAST_CLEAR: signal_async_trans
+ signal_async_to_pulse_FAST_CLEAR: signal_async_to_pulse
generic map (
- NUM_FF => 3
+ NUM_FF => 2
)
port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
- SIGNAL_A_IN => fast_clear_o,
- SIGNAL_OUT => fast_clear
+ CLK_IN => NX_MAIN_CLK_IN,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
+ PULSE_A_IN => fast_clear_o,
+ PULSE_OUT => fast_clear
);
pulse_dtrans_INVALID_TIMING_TRIGGER: pulse_dtrans
)
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_IN,
+ RESET_A_IN => RESET_NX_MAIN_CLK_IN,
PULSE_A_IN => invalid_timing_trigger_n,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
if (RESET_IN = '1') then
valid_trigger_o <= '0';
timing_trigger_o <= '0';
- setup_trigger_o <= '0';
+ status_trigger_o <= '0';
fee_data_finished_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
fast_clear_o <= '0';
trigger_busy_o <= '0';
- send_testpulse_l <= '0';
TRIGGER_TYPE <= T_UNDEF;
STATE <= S_IDLE;
else
valid_trigger_o <= '0';
timing_trigger_o <= '0';
- setup_trigger_o <= '0';
+ status_trigger_o <= '0';
fee_data_finished_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
fast_clear_o <= '0';
trigger_busy_o <= '1';
- send_testpulse_l <= '0';
if (LVL1_INVALID_TRG_IN = '1') then
-- There was no valid Timing Trigger at CTS, do a fast clear
when S_CTS_TRIGGER =>
valid_trigger_o <= '1';
timing_trigger_o <= '1';
- if (testpulse_enable = '1') then
- send_testpulse_l <= '1';
- end if;
STATE <= S_WAIT_TRG_DATA_VALID;
when S_WAIT_TRG_DATA_VALID =>
PROC_EVENT_DATA_MULTIPLEXER: process(TRIGGER_TYPE)
begin
case TRIGGER_TYPE is
- when T_UNDEF | T_IGNORE | T_INTERNAL | T_TIMING =>
+ when T_UNDEF | T_IGNORE | T_INTERNAL =>
fee_data_o <= (others => '0');
fee_data_write_o <= '0';
- --when T_TIMING =>
- -- fee_data_o <= FEE_DATA_0_IN;
- -- fee_data_write_o <= FEE_DATA_WRITE_0_IN;
+ when T_TIMING =>
+ fee_data_o <= FEE_DATA_0_IN;
+ fee_data_write_o <= FEE_DATA_WRITE_0_IN;
when T_SETUP =>
fee_data_o <= FEE_DATA_1_IN;
end case;
end process PROC_EVENT_DATA_MULTIPLEXER;
-
--- pulse_dtrans_4: pulse_dtrans
--- generic map (
--- CLK_RATIO => 2
--- )
--- port map (
--- CLK_A_IN => CLK_IN,
--- RESET_A_IN => RESET_IN,
--- PULSE_A_IN => send_testpulse_l,
--- CLK_B_IN => NX_MAIN_CLK_IN,
--- RESET_B_IN => RESET_IN,
--- PULSE_B_OUT => send_testpulse
--- );
-
- nx_timer_1: nx_timer
+ timer_1: timer
generic map (
CTR_WIDTH => 12
)
port map (
CLK_IN => NX_MAIN_CLK_IN,
RESET_IN => wait_timer_reset,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => reg_testpulse_delay,
TIMER_DONE_OUT => wait_timer_done
);
-
- signal_async_trans_TESTPULSE_ENABLE: signal_async_trans
- generic map (
- NUM_FF => 2
- )
- port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_IN,
- SIGNAL_A_IN => reg_testpulse_enable,
- SIGNAL_OUT => testpulse_enable
- );
- bus_async_trans_TESTPULSE_DELAY: bus_async_trans
- generic map (
- BUS_WIDTH => 12,
- NUM_FF => 2
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SIGNAL_A_IN => reg_testpulse_delay,
- SIGNAL_OUT => testpulse_delay
- );
-
PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
- if (RESET_IN = '1' or fast_clear = '1') then
- wait_timer_init <= (others => '0');
+ if (RESET_NX_MAIN_CLK_IN = '1') then
+ wait_timer_start <= '0';
wait_timer_reset <= '1';
trigger_testpulse_o <= '0';
T_STATE <= T_IDLE;
else
trigger_testpulse_o <= '0';
- wait_timer_init <= (others => '0');
+ wait_timer_start <= '0';
wait_timer_reset <= '0';
-
- case T_STATE is
- when T_IDLE =>
- if (send_testpulse = '1') then
- if (testpulse_delay > 0) then
- wait_timer_init <= testpulse_delay;
- T_STATE <= T_WAIT_TIMER;
+ if (fast_clear = '1') then
+ wait_timer_reset <= '1';
+ T_STATE <= T_IDLE;
+ else
+ case T_STATE is
+
+ when T_IDLE =>
+ if (send_testpulse = '1') then
+ if (reg_testpulse_delay > 0) then
+ wait_timer_start <= '1';
+ T_STATE <= T_WAIT_TIMER;
+ else
+ T_STATE <= T_SET_TESTPULSE;
+ end if;
+ else
+ T_STATE <= T_IDLE;
+ end if;
+
+ when T_WAIT_TIMER =>
+ if (wait_timer_done = '0') then
+ T_STATE <= T_WAIT_TIMER;
else
- T_STATE <= T_SET_TESTPULSE;
+ T_STATE <= T_SET_TESTPULSE;
end if;
- else
- T_STATE <= T_IDLE;
- end if;
-
- when T_WAIT_TIMER =>
- if (wait_timer_done = '0') then
- T_STATE <= T_WAIT_TIMER;
- else
- T_STATE <= T_SET_TESTPULSE;
- end if;
-
- when T_SET_TESTPULSE =>
- trigger_testpulse_o <= '1';
- T_STATE <= T_IDLE;
- end case;
+
+ when T_SET_TESTPULSE =>
+ trigger_testpulse_o <= '1';
+ T_STATE <= T_IDLE;
+ end case;
+ end if;
end if;
end if;
end process PROC_TESTPULSE_HANDLER;
-
+
PROC_CAL_RATES: process (CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
slv_ack_o <= '1';
when x"0001" =>
- if (unsigned(SLV_DATA_IN(11 downto 0)) > 1) then
- reg_testpulse_delay <=
- unsigned(SLV_DATA_IN(11 downto 0));
- else
- reg_testpulse_delay <= x"001";
- end if;
+ reg_testpulse_delay <=
+ unsigned(SLV_DATA_IN(11 downto 0));
slv_ack_o <= '1';
when x"0003" =>
-- Output Signals
-----------------------------------------------------------------------------
- timestamp_trigger_o <= timestamp_trigger;
-
-- Trigger Output
VALID_TRIGGER_OUT <= valid_trigger_o;
TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o;
TRIGGER_TIMING_OUT <= timing_trigger_o;
- TRIGGER_SETUP_OUT <= setup_trigger_o;
+ TRIGGER_STATUS_OUT <= status_trigger_o;
FAST_CLEAR_OUT <= fast_clear_o;
TRIGGER_BUSY_OUT <= trigger_busy_o;
signal store_to_fifo : std_logic;
signal trigger_busy_o : std_logic;
signal nomore_data_o : std_logic;
- signal wait_timer_init : unsigned(11 downto 0);
+ signal wait_timer_start : std_logic;
+ signal wait_timer_start_ns : std_logic;
signal wait_timer_init_ns : unsigned(19 downto 0);
signal token_return_last : std_logic;
signal token_return_first : std_logic;
DEBUG_OUT(15) <= nomore_data_o;
-- Timer
- nx_timer_1: nx_timer
+ timer_1: timer
generic map(
CTR_WIDTH => 12
)
port map (
CLK_IN => CLK_IN,
RESET_IN => timer_reset,
- TIMER_START_IN => wait_timer_init,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_END_IN => readout_time_max,
TIMER_DONE_OUT => wait_timer_done
);
- nx_timer_2: nx_timer
+ timer_2: timer
generic map(
CTR_WIDTH => 20,
STEP_SIZE => 10
port map (
CLK_IN => CLK_IN,
RESET_IN => timer_reset,
- TIMER_START_IN => wait_timer_init_ns,
+ TIMER_START_IN => wait_timer_start_ns,
+ TIMER_END_IN => wait_timer_init_ns,
TIMER_DONE_OUT => wait_timer_done_ns
);
store_to_fifo <= '0';
trigger_busy_o <= '0';
nomore_data_o <= '0';
- wait_timer_init <= (others => '0');
- wait_timer_init_ns <= (others => '0');
+ wait_timer_start <= '0';
+ wait_timer_start_ns <= '0';
wait_timer_reset_all <= '0';
min_val_time_expired <= '0';
t_data_o <= (others => '0');
STATE <= S_TEST_SELF_TRIGGER;
else
store_to_fifo <= '0';
- wait_timer_init <= (others => '0');
- wait_timer_init_ns <= (others => '0');
+ wait_timer_start <= '0';
+ wait_timer_start_ns <= '0';
wait_timer_reset_all <= '0';
trigger_busy_o <= '1';
nomore_data_o <= '0';
readout_mode <= readout_mode_r;
-- wait for data arrival and clear evt buffer
+ wait_timer_start_ns <= '1';
wait_timer_init_ns <= wait_for_data_time;
evt_buffer_clear_o <= '1';
STATE <= S_WAIT_DATA;
end if;
when S_PROCESS_START =>
- wait_timer_init <= readout_time_max;
+ wait_timer_start <= '1';
+ wait_timer_start_ns <= '1';
wait_timer_init_ns <= min_validation_time;
token_return_first <= '0';
ch_status_cmd_tr <= CS_RESET;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
CLK_ADCDAT_IN : in std_logic;
- RESTART_IN : in std_logic;
ADC0_SCLK_IN : in std_logic;
ADC0_SCLK_OUT : out std_logic;
ERROR_ADC0_OUT : out std_logic;
ERROR_ADC1_OUT : out std_logic;
+ DEBUG_IN : in std_logic_vector(3 downto 0);
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
);
end component;
-component fifo_44_data_delay
- port (
- Data : in std_logic_vector(43 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- AmEmptyThresh : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(43 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic
- );
-end component;
-
component fifo_32_data
port (
Data : in std_logic_vector(31 downto 0);
);
end component;
-component nx_calib_event
+component nx_status_event
generic (
BOARD_ID : std_logic_vector(1 downto 0));
port (
);
port (
CLK_IN : in std_logic;
- RESET_IN : in std_logic;
SIGNAL_A_IN : in std_logic;
SIGNAL_OUT : out std_logic
);
VALID_TRIGGER_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_SETUP_OUT : out std_logic;
+ TRIGGER_STATUS_OUT : out std_logic;
FAST_CLEAR_OUT : out std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TRIGGER_TESTPULSE_OUT : out std_logic;
-- Misc Tools
-------------------------------------------------------------------------------
-component nx_timer
+component timer
+ generic (
+ CTR_WIDTH : integer range 2 to 32;
+ STEP_SIZE : integer range 1 to 100
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMER_START_IN : in std_logic;
+ TIMER_END_IN : in unsigned(CTR_WIDTH - 1 downto 0);
+ TIMER_DONE_OUT : out std_logic
+ );
+end component;
+
+component timer_static
generic (
CTR_WIDTH : integer range 2 to 32;
- STEP_SIZE : integer
+ CTR_END : integer;
+ STEP_SIZE : integer range 1 to 100
);
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0);
+ TIMER_START_IN : in std_logic;
TIMER_DONE_OUT : out std_logic
);
end component;
-- Bus Handler
constant NUM_PORTS : integer := 13;
-
+
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0);
signal trigger : std_logic;
signal timestamp_trigger : std_logic;
signal trigger_timing : std_logic;
+ signal trigger_status : std_logic;
signal trigger_busy : std_logic;
signal fast_clear : std_logic;
signal fee_trg_release_o : std_logic;
signal error_data_receiver : std_logic;
-- Debug Handler
- constant DEBUG_NUM_PORTS : integer := 15;
+ constant DEBUG_NUM_PORTS : integer := 14;
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
- -- buffer
- signal nx_setup_data_f : std_logic_vector(31 downto 0);
- signal nx_setup_ack_f : std_logic;
- signal nx_setup_no_more_data_f : std_logic;
- signal nx_setup_unknown_addr_f : std_logic;
- signal nx_setup_data_ff : std_logic_vector(31 downto 0);
- signal nx_setup_ack_ff : std_logic;
- signal nx_setup_no_more_data_ff : std_logic;
- signal nx_setup_unknown_addr_ff : std_logic;
-
begin
-------------------------------------------------------------------------------
INT_DATA_OUT => int_data,
SLV_READ_IN => slv_read(9),
SLV_WRITE_IN => slv_write(9),
- SLV_DATA_OUT => nx_setup_data_f,
+ SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),
SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),
SLV_ADDR_IN => slv_addr(9*16+15 downto 9*16),
- SLV_ACK_OUT => nx_setup_ack_f,
- SLV_NO_MORE_DATA_OUT => nx_setup_no_more_data_f,
- SLV_UNKNOWN_ADDR_OUT => nx_setup_unknown_addr_f,
+ SLV_ACK_OUT => slv_ack(9),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(9),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9),
DEBUG_OUT => debug_line(1)
);
-
- PROC_NX_SETUP_BUFFER: process (CLK_IN, RESET_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- nx_setup_data_ff <= nx_setup_data_f;
- nx_setup_ack_ff <= nx_setup_ack_f;
- nx_setup_no_more_data_ff <= nx_setup_no_more_data_f;
- nx_setup_unknown_addr_ff <= nx_setup_unknown_addr_f;
-
- slv_data_rd(9*32+31 downto 9*32) <= nx_setup_data_ff;
- slv_ack(9) <= nx_setup_ack_ff;
- slv_no_more_data(9) <= nx_setup_no_more_data_ff;
- slv_unknown_addr(9) <= nx_setup_unknown_addr_ff;
- end if;
- end process PROC_NX_SETUP_BUFFER;
-------------------------------------------------------------------------------
-- I2C master block for accessing the nXyter
FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT,
FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT,
+
FEE_DATA_0_IN => fee_data_o_0,
FEE_DATA_WRITE_0_IN => fee_data_write_o_0,
FEE_DATA_1_IN => fee_data_o_1,
VALID_TRIGGER_OUT => trigger,
TIMESTAMP_TRIGGER_OUT => timestamp_trigger,
TRIGGER_TIMING_OUT => trigger_timing,
+ TRIGGER_STATUS_OUT => trigger_status,
FAST_CLEAR_OUT => fast_clear,
TRIGGER_BUSY_OUT => trigger_busy,
DEBUG_OUT => debug_line(11)
);
- nx_calib_event_1: nx_calib_event
+ nx_status_event_1: nx_status_event
generic map (
BOARD_ID => BOARD_ID
)
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
NXYTER_OFFLINE_IN => nxyter_offline,
- TRIGGER_IN => trigger_timing,
+ TRIGGER_IN => trigger_status,
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_evt_busy_1,
FEE_DATA_OUT => fee_data_o_1,
SLV_NO_MORE_DATA_OUT => slv_no_more_data(11),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11)
);
- debug_line(14)(0) <= CLK_IN;
- debug_line(14)(13 downto 1) <= slv_read;
- debug_line(14)(14) <= '0';
- debug_line(14)(15) <= '0';
+
-------------------------------------------------------------------------------
-- END
-------------------------------------------------------------------------------
end entity;
architecture Behavioral of pulse_delay is
+ signal start_timer_x : std_logic;
- signal start_timer_x : unsigned(23 downto 0);
-
- signal start_timer : unsigned(23 downto 0);
+ signal start_timer : std_logic;
signal timer_done : std_logic;
signal pulse_o : std_logic;
begin
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 24
+ CTR_WIDTH => 24,
+ CTR_END => (DELAY - 1)
)
port map (
CLK_IN => CLK_IN,
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- start_timer <= (others => '0');
+ start_timer <= '0';
STATE <= IDLE;
else
start_timer <= start_timer_x;
PULSE_IN,
timer_done
)
- constant TIMER_VALUE :
- unsigned(23 downto 0) := to_unsigned(DELAY - 1, 24);
-
+
begin
pulse_o <= '0';
case STATE is
when IDLE =>
if (PULSE_IN = '1') then
- start_timer_x <= TIMER_VALUE;
+ start_timer_x <= '1';
pulse_o <= '0';
NEXT_STATE <= WAIT_TIMER;
else
- start_timer_x <= (others => '0');
+ start_timer_x <= '0';
pulse_o <= '0';
NEXT_STATE <= IDLE;
end if;
when WAIT_TIMER =>
- start_timer_x <= (others => '0');
+ start_timer_x <= '0';
if (timer_done = '0') then
- pulse_o <= '0';
+ pulse_o <= '0';
NEXT_STATE <= WAIT_TIMER;
else
pulse_o <= '1';
entity pulse_to_level is
generic (
- NUM_CYCLES : integer range 2 to 15 := 4
+ NUM_CYCLES : integer range 2 to 15 := 4
);
port (
CLK_IN : in std_logic;
attribute HGROUP : string;
attribute HGROUP of Behavioral : architecture is "PULSE_TO_LEVEL";
- signal start_timer_x : unsigned(4 downto 0);
+ signal start_timer_x : std_logic;
- signal start_timer : unsigned(4 downto 0);
+ signal start_timer : std_logic;
signal timer_done : std_logic;
signal level_o : std_logic;
begin
- nx_timer_1: nx_timer
+ timer_static_1: timer_static
generic map (
- CTR_WIDTH => 5
+ CTR_WIDTH => 5,
+ CTR_END => (NUM_CYCLES - 1)
)
port map (
CLK_IN => CLK_IN,
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- start_timer <= (others => '0');
+ start_timer <= '0';
STATE <= IDLE;
else
start_timer <= start_timer_x;
when IDLE =>
if (PULSE_IN = '1') then
level_o <= '1';
- start_timer_x <= TIMER_VALUE;
+ start_timer_x <= '1';
NEXT_STATE <= WAIT_TIMER;
else
level_o <= '0';
- start_timer_x <= (others => '0');
+ start_timer_x <= '0';
NEXT_STATE <= IDLE;
end if;
when WAIT_TIMER =>
- start_timer_x <= (others => '0');
+ start_timer_x <= '0';
if (timer_done = '0') then
level_o <= '1';
NEXT_STATE <= WAIT_TIMER;
0x8505 : r/w johnson_counter_sync (2 Bit), do not touch, experts only register
0x8506 : r/w PLL ADC Sampling Clock DPHASE (4 Bit)
0x8507 : r/w PLL ADC Sampling Clock FINEDELB (4 Bit)
-
0x8508 : r current ADC FIFO value
-0x8509 : r/w Enable Test ADC Input Data Error Test
-0x850a : r ADC Input Data Error Counter (16 Bit)
- (only valid in case of 0x8509 is 1, see line above)
+0x8509 : r ADC Reset Counter
+0x850a : r Reserved
0x850b : r/w r: Nxyter Data Clock Status (1 = O.K.)
w: reset ADC Handler
0x850c : r/w r: Reset Handler Counter (16 Bit)
0x8512 : r Test ADC Value
0x8513 : r/w Debug Multiplexer:
0: no ADC Values, normal Debug
- 1: ADC Value Nxyter
- 2: ADC Value Testchannel
+ 1: ADC Handler adc_ad922** direct
+ 2: Testchannel handler, forget about it
3: ADC Reset Handler
-- NX Data Validate
-- Debug Multiplexer
0x8020 : r/w Select Debug Entity
- 0: nxyter_registers
+ 0: nx_control
1: nx_setup
2: nx_i2c_master
3: adc_spi_master
begin
if( rising_edge(CLK_IN) ) then
pulse_ff(NUM_FF - 1) <= PULSE_A_IN;
- if( RESET_IN = '1' ) then
- pulse_ff(NUM_FF - 2 downto 0) <= (others => '0');
- else
- for i in NUM_FF - 2 downto 0 loop
- pulse_ff(i) <= pulse_ff(i + 1);
- end loop;
- end if;
+ for i in NUM_FF - 2 downto 0 loop
+ pulse_ff(i) <= pulse_ff(i + 1);
+ end loop;
end if;
end process PROC_SYNC_PULSE;
entity signal_async_trans is
generic (
- NUM_FF : integer range 2 to 4 := 2
+ NUM_FF : integer range 2 to 5 := 2
);
port (
CLK_IN : in std_logic;
- RESET_IN : in std_logic;
SIGNAL_A_IN : in std_logic;
SIGNAL_OUT : out std_logic
);
end entity;
architecture Behavioral of signal_async_trans is
- attribute HGROUP : string;
- attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TRANS";
-
- signal signal_ff : std_logic_vector(NUM_FF - 1 downto 0);
- signal signal_o : std_logic;
+ type signal_ff_t is array(0 to NUM_FF - 1) of std_logic;
+
+ signal signal_ff : signal_ff_t;
begin
PROC_SYNC_SIGNAL: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
- signal_ff(NUM_FF - 1) <= SIGNAL_A_IN;
- if( RESET_IN = '1' ) then
- signal_ff(NUM_FF - 2 downto 0) <= (others => '0');
- else
- for i in NUM_FF - 2 downto 0 loop
- signal_ff(i) <= signal_ff(i + 1);
- end loop;
- end if;
+ signal_ff(NUM_FF - 1) <= SIGNAL_A_IN;
+ for i in NUM_FF - 2 downto 0 loop
+ signal_ff(i) <= signal_ff(i + 1);
+ end loop;
end if;
end process PROC_SYNC_SIGNAL;
- signal_o <= signal_ff(0);
--- Outpu Signals
- SIGNAL_OUT <= signal_o;
+-- Output Signals
+ SIGNAL_OUT <= signal_ff(0);
end Behavioral;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity nx_timer is
+entity timer is
generic (
CTR_WIDTH : integer range 2 to 32 := 12;
STEP_SIZE : integer range 1 to 100 := 1
);
port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
- TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0);
+ TIMER_START_IN : in std_logic;
+ TIMER_END_IN : in unsigned(CTR_WIDTH - 1 downto 0);
TIMER_DONE_OUT : out std_logic
);
end entity;
-architecture Behavioral of nx_timer is
+architecture Behavioral of timer is
attribute HGROUP : string;
attribute HGROUP of Behavioral : architecture is "NX_TIMER";
PROC_TIMER: process(STATE,
TIMER_START_IN,
+ TIMER_END_IN,
timer_ctr
)
begin
case STATE is
when S_IDLE =>
timer_done_o <= '0';
- if (TIMER_START_IN > 0) then
- timer_ctr_x <= TIMER_START_IN - 1;
+ if (TIMER_START_IN = '1') then
+ timer_ctr_x <= TIMER_END_IN - 1;
NEXT_STATE <= S_COUNT;
else
timer_ctr_x <= (others => '0');
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity timer_static is
+ generic (
+ CTR_WIDTH : integer range 2 to 32 := 12;
+ CTR_END : integer := 10;
+ STEP_SIZE : integer range 1 to 100 := 1
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ TIMER_START_IN : in std_logic;
+ TIMER_DONE_OUT : out std_logic
+ );
+end entity;
+
+architecture Behavioral of timer_static is
+ attribute HGROUP : string;
+ attribute HGROUP of Behavioral : architecture is "NX_TIMER_STATIC";
+
+ -- Timer
+ constant ctr_limit : unsigned(CTR_WIDTH - 1 downto 0)
+ := to_unsigned(CTR_END - 1, CTR_WIDTH);
+ signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0);
+
+ signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0);
+ signal timer_done_o : std_logic;
+
+ type STATES is (S_IDLE,
+ S_COUNT
+ );
+ signal STATE, NEXT_STATE : STATES;
+
+begin
+
+ PROC_TIMER_TRANSFER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ timer_ctr <= (others => '0');
+ STATE <= S_IDLE;
+ else
+ timer_ctr <= timer_ctr_x;
+ STATE <= NEXT_STATE;
+ end if;
+ end if;
+ end process PROC_TIMER_TRANSFER;
+
+ PROC_TIMER: process(STATE,
+ TIMER_START_IN,
+ timer_ctr
+ )
+ begin
+
+ case STATE is
+ when S_IDLE =>
+ timer_done_o <= '0';
+ if (TIMER_START_IN = '1') then
+ timer_ctr_x <= ctr_limit - 1;
+ NEXT_STATE <= S_COUNT;
+ else
+ timer_ctr_x <= (others => '0');
+ NEXT_STATE <= S_IDLE;
+ end if;
+
+ when S_COUNT =>
+ if (timer_ctr > to_unsigned(STEP_SIZE - 1, CTR_WIDTH)) then
+ timer_ctr_x <= timer_ctr - to_unsigned(STEP_SIZE, CTR_WIDTH);
+ timer_done_o <= '0';
+ NEXT_STATE <= S_COUNT;
+ else
+ timer_ctr_x <= (others => '0');
+ timer_done_o <= '1';
+ NEXT_STATE <= S_IDLE;
+ end if;
+
+ end case;
+
+ end process PROC_TIMER;
+
+ -----------------------------------------------------------------------------
+ -- Output Signals
+ -----------------------------------------------------------------------------
+
+ TIMER_DONE_OUT <= timer_done_o;
+
+end Behavioral;
add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd"
add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd"
add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
-add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd"
add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd"
add_file -vhdl -lib "work" "source/pulse_delay.vhd"
add_file -vhdl -lib "work" "source/gray_decoder.vhd"
add_file -vhdl -lib "work" "source/gray_encoder.vhd"
-add_file -vhdl -lib "work" "source/nx_timer.vhd"
+add_file -vhdl -lib "work" "source/timer.vhd"
+add_file -vhdl -lib "work" "source/timer_static.vhd"
add_file -vhdl -lib "work" "source/debug_multiplexer.vhd"
add_file -vhdl -lib "work" "source/fifo_44_data_delay_my.vhd"
add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
-add_file -vhdl -lib "work" "source/nx_calib_event.vhd"
+add_file -vhdl -lib "work" "source/nx_status_event.vhd"
add_file -vhdl -lib "work" "source/nx_control.vhd"
add_file -vhdl -lib "work" "source/nx_setup.vhd"
-trb3_periph_nx2.vhd
\ No newline at end of file
+trb3_periph_nx1.vhd
\ No newline at end of file
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
- FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz;
-
+ #FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz;
+
+
USE PRIMARY NET "nx_main_clk_c";
USE PRIMARY NET "clk_100_i_c";
USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+
+ USE PRIMARY2EDGE NET "clk_adc_dat_1";
+ #USE PRIMARY2EDGE NET "clk_adc_dat_2";
#################################################################
# Reset Nets
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-REGION "MEDIA_UPLINK" "R102C95D" 13 25;
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
#################################################################
# Relax some of the timing constraints
#################################################################
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 20 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_FAST_CLEAR*" 20 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_IINVALID_TIMING_TRIGGER*" 20 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TESTPULSE_ENABLE*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/bus_async_trans_TESTPULSE_DELAY*" 100 ns;
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_generator_*/bus_async_trans_TESTPULSE_LENGTH*" 100 ns;
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_to_pulse_TIMESTAMP_SYNC_IN*" 20 ns;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_p*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns;
+
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 20 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_control_*/nx_ts_reset_o" 10 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 10 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 20 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/reg_testpulse_length_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns;
+
+BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*";
+
+#SPI Interface
+REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
#################################################################
# Constraints for nxyter inputs
# look at .par and .twr.setup file for clocks
# and .mrp or errors
-#DEFINE PORT GROUP "NX1_CLK_IN" "NX1_DATA_CLK_*";
PROHIBIT PRIMARY NET "NX1_DATA_CLK_*";
PROHIBIT SECONDARY NET "NX1_DATA_CLK_*";
-#DEFINE PORT GROUP "NX1_CLK_IN" "NX1_DATA_CLK_*";
-PROHIBIT PRIMARY NET "NX2_DATA_CLK_*";
-PROHIBIT SECONDARY NET "NX2_DATA_CLK_*";
+#PROHIBIT PRIMARY NET "NX2_DATA_CLK_*";
+#PROHIBIT SECONDARY NET "NX2_DATA_CLK_*";
-DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_DATA_CLK_IN";
+DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_DATA_CLK_IN";
-DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_DATA_CLK_IN";
+#DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
+#INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_DATA_CLK_IN";
entity trb3_periph is
port(
--Clocks
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
architecture trb3_periph_arch of trb3_periph is
+ constant NUM_NXYTER : integer := 1;
+
-- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
attribute ODDRAPPS : string;
attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
signal trg_spike_detected_i : std_logic;
--Data channel
- signal fee_trg_release_i : std_logic_vector(2-1 downto 0);
- signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0);
- signal fee_data_i : std_logic_vector(2*32-1 downto 0);
- signal fee_data_write_i : std_logic_vector(2-1 downto 0);
- signal fee_data_finished_i : std_logic_vector(2-1 downto 0);
- signal fee_almost_full_i : std_logic_vector(2-1 downto 0);
+ signal fee_trg_release_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_trg_statusbits_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
+ signal fee_data_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
+ signal fee_data_write_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_data_finished_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_almost_full_i : std_logic_vector(NUM_NXYTER-1 downto 0);
--Slow Control channel
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 100,
TIMING_TRIGGER_RAW => c_YES,
+
--Configure data handler
- DATA_INTERFACE_NUMBER => 2,
+ DATA_INTERFACE_NUMBER => NUM_NXYTER,
DATA_BUFFER_DEPTH => 13, --13
DATA_BUFFER_WIDTH => 32,
DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
- --Response from FEE, i.e. nXyter #1
- FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1),
- FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
- FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32),
- FEE_DATA_WRITE_IN(1) => fee_data_write_i(1),
- FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1),
- FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1),
-
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
entity trb3_periph is
+ generic (
+ NUM_NXYTER : integer := 1;
+ );
port(
--Clocks
CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ #SYSCONFIG MCCLK_FREQ = 2.5;
+
+ #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+#All DQ groups from one bank are grouped.
+#All DQS are inserted in the DQ lines at position 6 and 7
+#DQ 6-9 are shifted to 8-11
+#Order per bank is kept, i.e. adjacent numbers have adjacent pins
+#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
+#even numbers are positive LVDS line, odd numbers are negative LVDS line
+#DQUL can be switched to 1.8V
+
+
+
+# nXyter 1
+
+LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
+LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
+LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
+#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
+
+LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36
+LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42
+LOCATE COMP "NX1_I2C_SCL_INOUT" SITE "R6"; #DQLL1_7 #44
+
+LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74
+LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78
+LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82
+LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86
+LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90
+LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94
+LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89
+
+LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
+LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
+LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
+
+LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50
+LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54
+LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58
+LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66
+LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70
+LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49
+LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53
+LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57
+
+
+#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
+#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
+#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
+
+IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
+IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
+IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
+
+IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+
+
+
+# nXyter 2
+
+#LOCATE COMP "NX2_ADC_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133
+#LOCATE COMP "NX2_RESET_OUT" SITE "W23"; #DQLR1_0 #169
+#LOCATE COMP "NX2_MAIN_CLK_OUT" SITE "AA26"; #DQLR1_4 #177
+#LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185
+#LOCATE COMP "NX2_DATA_CLK_IN" SITE "M23"; #DQSUR1_T #118
+##LOCATE COMP "NX2_DATA_CLK_IN" SITE "N23"; #DQUR2_2 #134
+#LOCATE COMP "ADDON_TRIGGER_OUT" SITE "N23"; #DQUR2_2 #134
+#
+#LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170
+#LOCATE COMP "NX2_I2C_SDA_INOUT" SITE "R26"; #DQLR2_1 #172
+#LOCATE COMP "NX2_I2C_REG_RESET_OUT" SITE "T25"; #DQLR2_2 #174
+#LOCATE COMP "NX2_I2C_SM_RESET_OUT" SITE "T24"; #DQLR2_3 #176
+#
+#LOCATE COMP "NX2_SPI_SDIO_INOUT" SITE "T26"; #DQLR2_4 #178
+#LOCATE COMP "NX2_SPI_SCLK_OUT" SITE "U26"; #DQLR2_5 #180
+#LOCATE COMP "NX2_SPI_CSB_OUT" SITE "U24"; #DQLR2_6 #186
+#
+#LOCATE COMP "NX2_ADC_D_IN" SITE "J23"; #DQUR0_0 #105
+#LOCATE COMP "NX2_ADC_A_IN" SITE "G26"; #DQUR0_2 #109
+#LOCATE COMP "NX2_ADC_DCLK_IN" SITE "F24"; #DQSUR0_T #113
+#LOCATE COMP "NX2_ADC_NX_IN" SITE "H26"; #DQUR0_4 #117
+#LOCATE COMP "NX2_ADC_B_IN" SITE "K23"; #DQUR0_6 #121
+#LOCATE COMP "NX2_ADC_FCLK_IN" SITE "F25"; #DQUR0_8 #125 #input only
+#
+#LOCATE COMP "NX2_TIMESTAMP_IN_0" SITE "H24"; #DQUR1_0 #106
+#LOCATE COMP "NX2_TIMESTAMP_IN_1" SITE "L20"; #DQUR1_2 #110
+#LOCATE COMP "NX2_TIMESTAMP_IN_2" SITE "K24"; #DQUR1_4 #114
+#LOCATE COMP "NX2_TIMESTAMP_IN_3" SITE "L24"; #DQUR1_6 #122
+#LOCATE COMP "NX2_TIMESTAMP_IN_4" SITE "M22"; #DQUR1_8 #126
+#LOCATE COMP "NX2_TIMESTAMP_IN_5" SITE "J26"; #DQUR2_0 #130
+#LOCATE COMP "NX2_TIMESTAMP_IN_6" SITE "K19"; #DQUR2_4 #138
+#LOCATE COMP "NX2_TIMESTAMP_IN_7" SITE "L25"; #DQUR2_6 #146
+#
+#
+##DEFINE PORT GROUP "LVDS_group3" "NX2_TIMESTAMP*" ;
+##IOBUF GROUP "LVDS_group3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#
+#
+##DEFINE PORT GROUP "LVDS_group4" "NX2_ADC*IN" ;
+##IOBUF GROUP "LVDS_group4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
+#
+#IOBUF PORT "ADDON_TRIGGER_OUT" IO_TYPE=LVDS25;
+#IOBUF PORT "NX2_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+#IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25;
+#IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25;
+#IOBUF PORT "NX2_RESET_OUT" IO_TYPE=LVDS25;
+#
+#IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+#IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+#IOBUF PORT "NX2_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+#IOBUF PORT "NX2_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+#
+#IOBUF PORT "NX2_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+#IOBUF PORT "NX2_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+#IOBUF PORT "NX2_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+
+
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+#LOCATE COMP "SUPPL" SITE "C14";
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
jspc29 / trb3.git / commitdiff