better AN

diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd
index 27d1af1506e24c41c30c7948435c838c300d87f3..f204a031e4df5ca2432ea13d6b6d411b2118b607 100644 (file)
--- a/gbe_trb/base/inserter.vhd
+++ b/gbe_trb/base/inserter.vhd
@@ -103,8 +103,8 @@ begin
   end process THE_SYNC_PROC;\r
 \r
   -- we have an /I/ candidate for dropping (in the input and in the first stage)\r
-  idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and\r
-                      (PHY_D_IN = x"50")            and (PHY_K_IN = '0')   and (PHY_CD_IN = '0')) \r
+  idle_x <= '1' when ((delay_q(7 downto 0) = x"bc")              and (delay_q(8) = '1') and (delay_q(9) = '0') and\r
+                      ((PHY_D_IN = x"50") or (PHY_D_IN = x"c5")) and (PHY_K_IN = '0')   and (PHY_CD_IN = '0')) \r
              else '0';\r
 \r
   -- insert counter\r

diff --git a/gbe_trb/base/parser.vhd b/gbe_trb/base/parser.vhd
index 4db66cf0bde654c55088f1d0fc746a062b19597d..5f993c5df121e81fa60ef01502b6d2af99041168 100644 (file)
--- a/gbe_trb/base/parser.vhd
+++ b/gbe_trb/base/parser.vhd
@@ -1,153 +1,143 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-
-entity parser is
-  port(
-    CLK           : in  std_logic;
-    RESET         : in  std_logic;
-    --
-    PHY_D_IN      : in  std_logic_vector(7 downto 0);
-    PHY_K_IN      : in  std_logic;
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity parser is\r
+  port(\r
+    CLK           : in  std_logic;\r
+    RESET         : in  std_logic;\r
+    --\r
+    PHY_D_IN      : in  std_logic_vector(7 downto 0);\r
+    PHY_K_IN      : in  std_logic;\r
     --\r
-    UNKNOWN_OUT   : out std_logic;
-    IDLE_OUT      : out std_logic;
-    CFG_OUT       : out std_logic
-  );
-end entity parser;
-
-architecture parser_arch of parser is
-
--- state machine signals
-  type state_t is (ST0, ST1, IDLE0, IDLE1, CFG0, CFG1, CFG2, CFG3, UK0, UK1);
-  signal STATE, NEXT_STATE    : state_t;
-
+    UNKNOWN_OUT   : out std_logic;\r
+    IDLE_OUT      : out std_logic;\r
+    CFG_OUT       : out std_logic\r
+  );\r
+end entity parser;\r
+\r
+architecture parser_arch of parser is\r
+\r
+-- state machine signals\r
+  type state_t is (ST0, ST1, IDLE0, IDLE1, CFG0, CFG1, CFG2, CFG3, UK0, UK1);\r
+  signal STATE, NEXT_STATE    : state_t;\r
+\r
 -- Signals\r
-  signal phy_d_q          : std_logic_vector(7 downto 0);
-  signal phy_d_qq         : std_logic_vector(7 downto 0);
-  signal phy_k_q          : std_logic;
-  signal phy_k_qq         : std_logic;
+  signal phy_d_q          : std_logic_vector(7 downto 0);\r
+  signal phy_d_qq         : std_logic_vector(7 downto 0);\r
+  signal phy_k_q          : std_logic;\r
+  signal phy_k_qq         : std_logic;\r
 \r
   signal idle_x           : std_logic;\r
   signal cfg_x            : std_logic;\r
   signal unknown_x        : std_logic;\r
-
-begin
+\r
+begin\r
 \r
   THE_SYNC_PROC: process( CLK )\r
   begin\r
     if( rising_edge(CLK) ) then\r
       phy_d_qq <= phy_d_q;\r
       phy_d_q  <= PHY_D_IN;\r
-      phy_k_qq <= phy_k_q;
-      phy_k_q  <= PHY_K_IN;
+      phy_k_qq <= phy_k_q;\r
+      phy_k_q  <= PHY_K_IN;\r
     end if;\r
   end process THE_SYNC_PROC;\r
-
-  -----------------------------------------------------------
-  -- statemachine: clocked process
-  -----------------------------------------------------------
-  THE_FSM: process( CLK )
-  begin
-    if( rising_edge(CLK) ) then
-      if( RESET = '1' ) then
-        STATE <= ST0;
-      else
-        STATE <= NEXT_STATE;
-      end if;
-    end if;
-  end process THE_FSM;
-\r
-  THE_STATE_TRANSITIONS: process( STATE, phy_d_qq, phy_d_q, phy_k_qq, phy_k_q )
-  begin
+\r
+  -----------------------------------------------------------\r
+  -- statemachine: clocked process\r
+  -----------------------------------------------------------\r
+  THE_FSM: process( CLK )\r
+  begin\r
+    if( rising_edge(CLK) ) then\r
+      if( RESET = '1' ) then\r
+        STATE <= ST0;\r
+      else\r
+        STATE <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process THE_FSM;\r
+\r
+  THE_STATE_TRANSITIONS: process( STATE, phy_d_qq, phy_d_q, phy_k_qq, phy_k_q )\r
+  begin\r
     idle_x    <= '0';\r
     cfg_x     <= '0';\r
     unknown_x <= '0';\r
-
-    case STATE is
+\r
+    case STATE is\r
 \r
       when ST0 =>\r
-        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then\r
+        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then\r
           NEXT_STATE <= IDLE0;\r
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then\r
-          NEXT_STATE <= CFG0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then\r
-          NEXT_STATE <= CFG0;
+        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= CFG0;\r
         else\r
           NEXT_STATE <= ST1;\r
         end if;\r
 \r
-      when ST1 =>
-        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
-          NEXT_STATE <= IDLE0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        else
-          NEXT_STATE <= ST0;
-        end if;
+      when ST1 =>\r
+        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= IDLE0;\r
+        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= CFG0;\r
+        else\r
+          NEXT_STATE <= ST0;\r
+        end if;\r
 \r
       when IDLE0 =>\r
         idle_x <= '1';\r
         NEXT_STATE <= IDLE1;\r
 \r
       when IDLE1 =>\r
-        idle_x <= '1';
-        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
-          NEXT_STATE <= IDLE0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        else
-          NEXT_STATE <= UK0;
-        end if;
+        idle_x <= '1';\r
+        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= IDLE0;\r
+        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= CFG0;\r
+        else\r
+          NEXT_STATE <= UK0;\r
+        end if;\r
 \r
       when CFG0 =>\r
         cfg_x <= '1';\r
         NEXT_STATE <= CFG1;\r
 \r
       when CFG1 =>\r
-        cfg_x <= '1';
-        NEXT_STATE <= CFG2;
+        cfg_x <= '1';\r
+        NEXT_STATE <= CFG2;\r
 \r
       when CFG2 =>\r
-        cfg_x <= '1';
-        NEXT_STATE <= CFG3;
+        cfg_x <= '1';\r
+        NEXT_STATE <= CFG3;\r
 \r
       when CFG3 =>\r
-        cfg_x <= '1';
-        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
-          NEXT_STATE <= IDLE0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        else
-          NEXT_STATE <= UK0;
-        end if;
+        cfg_x <= '1';\r
+        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= IDLE0;\r
+        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= CFG0;\r
+        else\r
+          NEXT_STATE <= UK0;\r
+        end if;\r
 \r
       when UK0 =>\r
         unknown_x <= '1';\r
         NEXT_STATE <= UK1;\r
 \r
-      when UK1 =>
-        unknown_x <= '1';
-        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
-          NEXT_STATE <= IDLE0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
-          NEXT_STATE <= CFG0;
-        else
-          NEXT_STATE <= UK0;
-        end if;
-\r
-      when others =>
-        NEXT_STATE <= ST0;
+      when UK1 =>\r
+        unknown_x <= '1';\r
+        if   ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= IDLE0;\r
+        elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then\r
+          NEXT_STATE <= CFG0;\r
+        else\r
+          NEXT_STATE <= UK0;\r
+        end if;\r
+\r
+      when others =>\r
+        NEXT_STATE <= ST0;\r
 \r
     end case;\r
 \r
@@ -156,5 +146,5 @@ begin
   IDLE_OUT    <= idle_x   when rising_edge(CLK);\r
   CFG_OUT     <= cfg_x    when rising_edge(CLK);\r
   UNKNOWN_OUT <= unknown_x when rising_edge(CLK);\r
-
-end architecture;
+\r
+end architecture;\r

diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd
index 48a4aac5727e858339f73ab9c5d02a963bae76b9..0e1cfaf5dd4a3a8b8eb1bdebbb50ddad95be0716 100644 (file)
--- a/gbe_trb/base/remover.vhd
+++ b/gbe_trb/base/remover.vhd
@@ -167,14 +167,14 @@ begin
         end if;\r
 \r
       when IDLE =>\r
-        if( (phy_k_fifo = '1') and (phy_d_fifo = x"bc") and (fifofull = '0')) then\r
+        if( (phy_k_fifo = '1') and (phy_d_fifo = x"bc") and (fifofull = '0') ) then\r
           NEXT_STATE <= ONE;\r
         else\r
           NEXT_STATE <= IDLE;\r
         end if;\r
 \r
       when ONE =>\r
-        if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then\r
+        if( (phy_k_fifo = '0') and ((phy_d_fifo = x"50") or (phy_d_fifo = x"c5")) ) then\r
           NEXT_STATE <= TWO;\r
           replace_k_x <= '1';\r
         else\r

diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
index 51b38faf50d6f1ed1a89de45de1be0e291ae6611..2a76be6300da5ff037f23ab45c43ccd93a192547 100644 (file)
--- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
@@ -554,7 +554,7 @@ begin
         sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_rx_data_src((i + 1) * 8 - 1 downto i * 8);
         sd_rx_kcntl_dst(i)                           <= sd_rx_kcntl_src(i);
         DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8)   <= (others => '0');
-        DLM_FOUND_OUT(i)                             <= 'i';
+        DLM_FOUND_OUT(i)                             <= '0';
       end generate NO_TRUDY_AND_EVE;
       ------------------------------------------------------------  
       ------------------------------------------------------------