--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity fee_signals is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ TEST_SIG_OUT : out std_logic_vector( 7 downto 0);
+ FEETEMP : inout std_logic_vector( 3 downto 0)
+ );
+end entity;
+
+
+
+architecture arch of fee_signals is
+
+signal timer_reg : std_logic_vector(11 downto 0) := x"3FF";
+signal select_reg, invert_reg : std_logic_vector(7 downto 0);
+
+type temp_arr is array(0 to 3) of std_logic_vector(11 downto 0);
+signal temps : temp_arr;
+
+signal timer : unsigned(11 downto 0);
+signal temp_i : std_logic_vector(11 downto 0);
+signal status_i : std_logic_vector(31 downto 0);
+
+signal onewire_in, onewire_out : std_logic;
+signal finished, lastread_q : std_logic;
+signal onewireselect : integer range 0 to 3;
+signal start : std_logic;
+
+begin
+
+PROC_REG : process begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+ start <= '0';
+
+ if BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(4 downto 0) = "00000" then
+ BUS_TX.data <= x"00" & invert_reg & x"00" & select_reg;
+ elsif BUS_RX.addr(4 downto 0) = "00001" then
+ BUS_TX.data <= x"00000" & timer_reg;
+ elsif BUS_RX.addr(4 downto 0) = "10000" then
+ BUS_TX.data <= x"00000" & temps(0);
+ elsif BUS_RX.addr(4 downto 0) = "10001" then
+ BUS_TX.data <= x"00000" & temps(1);
+ elsif BUS_RX.addr(4 downto 0) = "10010" then
+ BUS_TX.data <= x"00000" & temps(2);
+ elsif BUS_RX.addr(4 downto 0) = "10011" then
+ BUS_TX.data <= x"00000" & temps(3);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ end if;
+ if BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(4 downto 0) = "00000" then
+ select_reg <= BUS_RX.data(7 downto 0);
+ invert_reg <= BUS_RX.data(23 downto 16);
+ start <= '1';
+ elsif BUS_RX.addr(4 downto 0) = "00001" then
+ timer_reg <= BUS_RX.data(11 downto 0);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ end if;
+
+end process;
+
+THE_ONEWIRE : trb_net_onewire
+ generic map(
+ USEINOUT => c_NO
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ READOUT_ENABLE_IN => '1',
+
+ ONEWIRE_IN => onewire_in,
+ ONEWIRE_OUT => onewire_out,
+ MONITOR_OUT => open,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => open,
+ ADDR_OUT => open,
+ WRITE_OUT=> open,
+ TEMP_OUT => temp_i,
+ ID_OUT => open,
+ STAT => status_i
+ );
+
+
+PROC_ONEWIRE : process(onewire_out,onewireselect)
+begin
+ FEETEMP <= (others => 'Z');
+ if onewire_out = '0' then
+ FEETEMP(onewireselect) <= '0';
+ end if;
+end process;
+
+ onewire_in <= FEETEMP(onewireselect);
+
+PROC_ONEWIRESELECT : process begin
+ wait until rising_edge(CLK);
+ lastread_q <= status_i(6);
+ finished <= lastread_q and not status_i(6);
+
+ if finished = '1' then
+ temps(onewireselect) <= temp_i;
+ onewireselect <= onewireselect + 1;
+ end if;
+end process;
+
+PROC_TESTSIG : process begin
+ wait until rising_edge(CLK);
+ if start = '1' then
+ timer <= unsigned(timer_reg);
+ TEST_SIG_OUT <= not invert_reg;
+ end if;
+ if timer > 0 then
+ timer <= timer - 1 ;
+ else
+ TEST_SIG_OUT <= invert_reg;
+ end if;
+
+end process;
+
+end architecture;
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
+ --pinout to be used - don't forget to change config_compile.pl as well
+ -- 0: 32 Pin AddOn
+ -- 1: 4conn AddOn
+ -- 2: 2x KEL on board
+ -- 3: ADA AddOn (plus test on KEL)
+
+ constant PINOUT : integer := 3;
+
+--TDC settings
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 49; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
+ --ring buffer size: 32,64,96,128,dyn
+ constant TDC_DATA_FORMAT : integer := 0;
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 512; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
+ constant USE_CALIBRATION_200MHZ : integer := c_YES;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F373";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"73";
+
+--set to 0 for backplane serdes, set to 3 for front SFP serdes
+ constant SERDES_NUM : integer := 0;
+
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 48;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 52;
+
+ --trigger generation only on 'fast' channels from Padiwa
+ constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;
+
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ x"85",x"0a",
+ x"86",x"0a",
+ x"87",x"0a",
+ others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500B000"; --Change depening on pinout
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+ t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1));
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
jspc29 / trb3sc.git / commitdiff