hmmmm

diff --git a/base/code/adc_ad9222.vhd b/base/code/adc_ad9222.vhd
index 4e7bd2d6454758baf5c6aefee816b19ac2764c8c..077677f9be8be44b4762edd2820f7795b5463181 100644 (file)
--- a/base/code/adc_ad9222.vhd
+++ b/base/code/adc_ad9222.vhd
@@ -37,11 +37,11 @@ architecture adc_ad9222_arch of  adc_ad9222 is
 
 signal clk_data  : std_logic;
 
-signal data_in   : std_logic_vector(39 downto 0);
-signal data_int  : std_logic_vector(39 downto 0);
-signal fifo_empty : std_logic_vector(1 downto 0);
-signal fifo_full  : std_logic_vector(1 downto 0);
-signal valid_read : std_logic_vector(1 downto 0);
+signal data_in   : std_logic_vector(DEVICES*20-1 downto 0);
+signal data_int  : std_logic_vector(DEVICES*20-1 downto 0);
+signal fifo_empty : std_logic_vector(DEVICES-1 downto 0);
+signal fifo_full  : std_logic_vector(DEVICES-1 downto 0);
+signal valid_read : std_logic_vector(DEVICES-1 downto 0);
 
 type cdt_t is array(0 to DEVICES-1) of std_logic_vector(59 downto 0);
 signal cdt_data_in : cdt_t;

diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf
index 00f2264058687bdcc9108fa201442c4e9f72b73c..2275f7599de21062f90b78cc62d5df7ad0086997 100644 (file)
--- a/base/trb3_periph_nxyter.lpf
+++ b/base/trb3_periph_nxyter.lpf
@@ -76,7 +76,8 @@ LOCATE COMP  "TEST_LINE_13"  SITE "C10";
 LOCATE COMP  "TEST_LINE_14"  SITE "H10";
 LOCATE COMP  "TEST_LINE_15"  SITE "H11";
 DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+#IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
 
 #################################################################
 # Connection to AddOn
@@ -89,15 +90,20 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
 #even numbers are positive LVDS line, odd numbers are negative LVDS line
 #DQUL can be switched to 1.8V
 
-# nXyter
 
-LOCATE COMP  "NX1_I2C_SM_RESET_OUT"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP  "NX1_I2C_REG_RESET_OUT"  SITE "R3";     #DQLL1_5   #36
-LOCATE COMP  "NX1_I2C_SDA_INOUT"      SITE "R5";     #DQLL1_6   #42
-LOCATE COMP  "NX1_I2C_SCL_OUT"        SITE "R6";     #DQLL1_7   #44
+
+# nXyter 1
+
 LOCATE COMP  "NX1_TESTPULSE_OUT"      SITE "T7";     #DQLL1_8   #46
 LOCATE COMP  "NX1_CLK256A_OUT"        SITE "AB1";    #DQLL2_2   #29
 LOCATE COMP  "NX1_RESET_OUT"          SITE "V6";     #DQLL2_8   #45
+LOCATE COMP  "NX1_CLK128_IN"          SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP  "NX1_CLK128_IN"         SITE "K4";     #DQSUL2_T  #62 see DQUL3_8_OUTOFLANE
+
+LOCATE COMP  "NX1_I2C_SM_RESET_OUT"   SITE "P4";     #DQLL1_4   #34
+LOCATE COMP  "NX1_I2C_REG_RESET_OUT"  SITE "R3";     #DQLL1_5   #36
+LOCATE COMP  "NX1_I2C_SDA_INOUT"      SITE "R5";     #DQLL1_6   #42
+LOCATE COMP  "NX1_I2C_SCL_INOUT"      SITE "R6";     #DQLL1_7   #44
 
 LOCATE COMP  "NX1_ADC_D_IN"           SITE "B2";     #DQUL0_0   #74
 LOCATE COMP  "NX1_ADC_A_IN"           SITE "D4";     #DQUL0_2   #78
@@ -105,48 +111,129 @@ LOCATE COMP  "NX1_ADC_NX_IN"          SITE "C3";     #DQUL0_4   #82
 LOCATE COMP  "NX1_ADC_DCLK_IN"        SITE "G5";     #DQSUL0_T  #86
 LOCATE COMP  "NX1_ADC_B_IN"           SITE "E3";     #DQUL0_6   #90
 LOCATE COMP  "NX1_ADC_FCLK_IN"        SITE "H6";     #DQUL0_8   #94
-
+LOCATE COMP  "NX1_ADC_SC_CLK32_OUT"   SITE "H5";     #DQUL1_6   #89
 
 LOCATE COMP  "NX1_SPI_SDIO_INOUT"     SITE "G2";     #DQUL1_0   #73
 LOCATE COMP  "NX1_SPI_SCLK_OUT"       SITE "F2";     #DQUL1_2   #77
 LOCATE COMP  "NX1_SPI_CSB_OUT"        SITE "C2";     #DQUL1_4   #81
-LOCATE COMP  "NX1_ADC_SC_CLK32_OUT"   SITE "H5";     #DQUL1_6   #89
 
 LOCATE COMP  "NX1_TIMESTAMP_IN_0"     SITE "K2";     #DQUL2_0   #50
 LOCATE COMP  "NX1_TIMESTAMP_IN_1"     SITE "J4";     #DQUL2_2   #54
 LOCATE COMP  "NX1_TIMESTAMP_IN_2"     SITE "D1";     #DQUL2_4   #58
-#LOCATE COMP  "NX1_CLK128_IN"         SITE "K4";     #DQSUL2_T  #62 see DQUL3_8_OUTOFLANE
 LOCATE COMP  "NX1_TIMESTAMP_IN_3"     SITE "E1";     #DQUL2_6   #66
 LOCATE COMP  "NX1_TIMESTAMP_IN_4"     SITE "L5";     #DQUL2_8   #70
-
 LOCATE COMP  "NX1_TIMESTAMP_IN_5"     SITE "H2";     #DQUL3_0   #49
 LOCATE COMP  "NX1_TIMESTAMP_IN_6"     SITE "K3";     #DQUL3_2   #53
 LOCATE COMP  "NX1_TIMESTAMP_IN_7"     SITE "H1";     #DQUL3_4   #57
 
 
-DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP_IN_*" ;
-IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-DEFINE PORT GROUP "LVDS_group2" "NX1_ADC_*_IN" ;
-IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-IOBUF PORT "NX1_ADC_SC_CLK32_OUT"  IO_TYPE=IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_CLK128_IN"         IO_TYPE=IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-IOBUF PORT "NX1_TESTPULSE_OUT"     IO_TYPE=IO_TYPE=LVDS25;
-IOBUF PORT "NX1_CLK256A_OUT"       IO_TYPE=IO_TYPE=LVDS25;
-IOBUF PORT "NX1_RESET_OUT"         IO_TYPE=IO_TYPE=LVDS25;
+#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
+#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_0"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_1"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_2"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_3"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_4"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_5"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_6"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TIMESTAMP_IN_7"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
+#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_D_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_A_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_DCLK_IN"       IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_NX_IN"         IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_B_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_FCLK_IN"       IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_ADC_SC_CLK32_OUT"  IO_TYPE=LVDS25;
+
+IOBUF PORT "NX1_CLK128_IN"         IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX1_TESTPULSE_OUT"     IO_TYPE=LVDS25;
+IOBUF PORT "NX1_CLK256A_OUT"       IO_TYPE=LVDS25;
+IOBUF PORT "NX1_RESET_OUT"         IO_TYPE=LVDS25;
 
 IOBUF PORT "NX1_I2C_SM_RESET_OUT"  IO_TYPE=LVCMOS25 PULLMODE=NONE;
 IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_I2C_SDA_INOUT"     IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_I2C_SCL_OUT"       IO_TYPE=LVCMOS25 PULLMODE=NONE;
-
-IOBUF PORT "NX1_SPI_SDIO_INOUT"    IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_SPI_SCLK_OUT"      IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_SPI_CSB_OUT"       IO_TYPE=LVCMOS25 PULLMODE=NONE;
-
+IOBUF PORT "NX1_I2C_SDA_INOUT"     IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "NX1_I2C_SCL_INOUT"     IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+IOBUF PORT "NX1_SPI_SDIO_INOUT"    IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX1_SPI_SCLK_OUT"      IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX1_SPI_CSB_OUT"       IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+
+# nXyter 2
+
+LOCATE COMP  "NX2_ADC_SC_CLK32_OUT"    SITE "Y19";    #DQLR0_2   #133
+LOCATE COMP  "NX2_RESET_OUT"           SITE "W23";    #DQLR1_0   #169
+LOCATE COMP  "NX2_CLK256A_OUT"         SITE "AA26";   #DQLR1_4   #177
+LOCATE COMP  "NX2_TESTPULSE_OUT"       SITE "AA24";   #DQLR1_6   #185
+LOCATE COMP  "NX2_CLK128_IN"           SITE "M23";    #DQSUR1_T  #118
+#LOCATE COMP  "NX2_CLK128_IN"           SITE "N23";    #DQUR2_2   #134
+
+LOCATE COMP  "NX2_I2C_SCL_INOUT"       SITE "R25";    #DQLR2_0   #170
+LOCATE COMP  "NX2_I2C_SDA_INOUT"       SITE "R26";    #DQLR2_1   #172
+LOCATE COMP  "NX2_I2C_REG_RESET_OUT"   SITE "T25";    #DQLR2_2   #174
+LOCATE COMP  "NX2_I2C_SM_RESET_OUT"    SITE "T24";    #DQLR2_3   #176
+
+LOCATE COMP  "NX2_SPI_SDIO_INOUT"      SITE "T26";    #DQLR2_4   #178
+LOCATE COMP  "NX2_SPI_SCLK_OUT"        SITE "U26";    #DQLR2_5   #180
+LOCATE COMP  "NX2_SPI_CSB_OUT"         SITE "U24";    #DQLR2_6   #186
+
+LOCATE COMP  "NX2_ADC_D_IN"            SITE "J23";    #DQUR0_0   #105
+LOCATE COMP  "NX2_ADC_A_IN"            SITE "G26";    #DQUR0_2   #109
+LOCATE COMP  "NX2_ADC_DCLK_IN"         SITE "F24";    #DQSUR0_T  #113
+LOCATE COMP  "NX2_ADC_NX_IN"           SITE "H26";    #DQUR0_4   #117
+LOCATE COMP  "NX2_ADC_B_IN"            SITE "K23";    #DQUR0_6   #121
+LOCATE COMP  "NX2_ADC_FCLK_IN"         SITE "F25";    #DQUR0_8   #125  #input only
+
+LOCATE COMP  "NX2_TIMESTAMP_IN_0"      SITE "H24";    #DQUR1_0   #106
+LOCATE COMP  "NX2_TIMESTAMP_IN_1"      SITE "L20";    #DQUR1_2   #110
+LOCATE COMP  "NX2_TIMESTAMP_IN_2"      SITE "K24";    #DQUR1_4   #114
+LOCATE COMP  "NX2_TIMESTAMP_IN_3"      SITE "L24";    #DQUR1_6   #122
+LOCATE COMP  "NX2_TIMESTAMP_IN_4"      SITE "M22";    #DQUR1_8   #126
+LOCATE COMP  "NX2_TIMESTAMP_IN_5"      SITE "J26";    #DQUR2_0   #130
+LOCATE COMP  "NX2_TIMESTAMP_IN_6"      SITE "K19";    #DQUR2_4   #138
+LOCATE COMP  "NX2_TIMESTAMP_IN_7"      SITE "L25";    #DQUR2_6   #146
+
+
+#DEFINE PORT GROUP "LVDS_group3" "NX2_TIMESTAMP*" ;
+#IOBUF GROUP "LVDS_group3" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_0"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_1"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_2"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_3"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_4"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_5"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_6"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TIMESTAMP_IN_7"    IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+
+#DEFINE PORT GROUP "LVDS_group4" "NX2_ADC*IN" ;
+#IOBUF GROUP "LVDS_group4" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_D_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_A_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_DCLK_IN"       IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_NX_IN"         IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_B_IN"          IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_FCLK_IN"       IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_ADC_SC_CLK32_OUT"  IO_TYPE=LVDS25;
+
+IOBUF PORT "NX2_CLK128_IN"         IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "NX2_TESTPULSE_OUT"     IO_TYPE=LVDS25;
+IOBUF PORT "NX2_CLK256A_OUT"       IO_TYPE=LVDS25;
+IOBUF PORT "NX2_RESET_OUT"         IO_TYPE=LVDS25;
+
+IOBUF PORT "NX2_I2C_SM_RESET_OUT"  IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF PORT "NX2_I2C_SDA_INOUT"     IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "NX2_I2C_SCL_INOUT"     IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+IOBUF PORT "NX2_SPI_SDIO_INOUT"    IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX2_SPI_SCLK_OUT"      IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX2_SPI_CSB_OUT"       IO_TYPE=LVCMOS25 PULLMODE=UP;
 
 
 #################################################################
@@ -160,7 +247,7 @@ IOBUF PORT "NX1_SPI_CSB_OUT"       IO_TYPE=LVCMOS25 PULLMODE=NONE;
 #LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
 #LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
 #LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-LOCATE COMP  "NX1_CLK128_IN"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
+
 
 
 #################################################################