CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
-
--Additional IO
-- HDR_IO : inout std_logic_vector(10 downto 1);
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_GPIO : inout std_logic_vector( 3 downto 0);
-
--LED
LED_GREEN : out std_logic;
LED_YELLOW : out std_logic;
LED_WHITE : out std_logic_vector( 1 downto 0);
LED_SFP_GREEN : out std_logic_vector( 1 downto 0);
LED_SFP_RED : out std_logic_vector( 1 downto 0);
-
--SFP
SFP_LOS : in std_logic_vector( 1 downto 0);
SFP_MOD0 : in std_logic_vector( 1 downto 0);
SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
-
LED_HUB_LINKOK : out std_logic_vector(8 downto 1);
LED_HUB_RX : out std_logic_vector(8 downto 1);
LED_HUB_TX : out std_logic_vector(8 downto 1);
HUB_MOD2 : inout std_logic_vector(8 downto 1);
HUB_TXDIS : out std_logic_vector(8 downto 1);
HUB_LOS : in std_logic_vector(8 downto 1);
-
--Serdes switch
PCSSW_ENSMB : out std_logic;
PCSSW_EQ : out std_logic_vector( 3 downto 0);
PCSSW_PE : out std_logic_vector( 3 downto 0);
PCSSW : out std_logic_vector( 7 downto 0);
-
--ADC
ADC_CLK : out std_logic;
ADC_CS : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
-
--Flash, 1-wire, Reload
FLASH_CLK : out std_logic;
FLASH_CS : out std_logic;
FLASH_OUT : in std_logic;
PROGRAMN : out std_logic;
ENPIRION_CLOCK : out std_logic;
- TEMPSENS : inout std_logic;
-
+ TEMPSENS : inout std_logic
--Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
+-- TEST_LINE : out std_logic_vector(15 downto 0)
);
bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX;
signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx,
bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
-
-
+
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-- );
end generate;
-
gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
generic map(
- SERDES_NUM => 3,
SIM_MODE => 0,
IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE),
IS_WAP_ZERO => 1
MEDIA_INT2MED(2) => int2med(6),
MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
-- komma operation
--- RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
RX_DLM_OUT(0) => open,
RX_DLM_OUT(1) => open,
RX_DLM_OUT(2) => open,
RX_DLM_OUT(3) => rx_dlm_i,
- RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
- TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
- TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
- RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
- RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
- TX_RST_IN => '0', --: in std_logic;
- TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => x"00",
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
-- sync operation
WORD_SYNC_IN => word_sync_i,
WORD_SYNC_OUT => word_sync_i,
)
port map (
CLEAR => '0',
- LOCALCLK => clk_full_osc,
+ CLK_REF => clk_full_osc,
TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i,
TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i,
STATE_OUT => tx_reset_state
);
- --HDR_IO(10 downto 1) <= (others => '0');
- --HDR_IO(10) <= debug_i(17);
- --HDR_IO(9) <= debug_i(16);
- --HDR_IO(8) <= '0';
- --HDR_IO(7) <= '0';
- --HDR_IO(6) <= '0';
- --HDR_IO(5) <= '0';
- --HDR_IO(4) <= '0';
- --HDR_IO(3) <= '0';
- --HDR_IO(2) <= rx_dlm_i;
- --HDR_IO(1) <= '0';
-
--- TEST_LINE(11 downto 0) <= debug_i(11 downto 0);
--- TEST_LINE(15 downto 12) <= debug_i(19 downto 16);
--- TEST_LINE(15 downto 12) <= tx_reset_state;
-
--- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4_slave3
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
--- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(4),
--- MEDIA_MED2INT(1) => med2int(5),
--- MEDIA_MED2INT(2) => med2int(6),
--- MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
--- MEDIA_INT2MED(0) => int2med(4),
--- MEDIA_INT2MED(1) => int2med(5),
--- MEDIA_INT2MED(2) => int2med(6),
--- MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
--- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
--- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
--- SD_LOS_IN(0) => HUB_LOS(5),
--- SD_LOS_IN(1) => HUB_LOS(6),
--- SD_LOS_IN(2) => HUB_LOS(7),
--- SD_LOS_IN(3) => SFP_LOS(1),
--- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
--- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
--- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--- --Control Interface
--- BUS_RX => bussci2_rx,
--- BUS_TX => bussci2_tx,
--- -- Status and control port
--- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
-
---------------------------------------------------------------------------
-- PCSC 4 downlinks
---------------------------------------------------------------------------
THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS
generic map(
- SERDES_NUM => 3,
SIM_MODE => 0,
IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
IS_WAP_ZERO => 1
RESET => reset_i,
CLEAR => clear_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(2),
- MEDIA_MED2INT(1) => med2int(3),
- MEDIA_MED2INT(2) => med2int(0),
- MEDIA_MED2INT(3) => med2int(1),
- MEDIA_INT2MED(0) => int2med(2),
- MEDIA_INT2MED(1) => int2med(3),
- MEDIA_INT2MED(2) => int2med(0),
- MEDIA_INT2MED(3) => int2med(1),
+ MEDIA_MED2INT(0) => med2int(2),
+ MEDIA_MED2INT(1) => med2int(3),
+ MEDIA_MED2INT(2) => med2int(0),
+ MEDIA_MED2INT(3) => med2int(1),
+ MEDIA_INT2MED(0) => int2med(2),
+ MEDIA_INT2MED(1) => int2med(3),
+ MEDIA_INT2MED(2) => int2med(0),
+ MEDIA_INT2MED(3) => int2med(1),
-- komma operation
- RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
- RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
- TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
- TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
- RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
- RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
- TX_RST_IN => '0', --: in std_logic;
- TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_DLM_OUT => open,
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => x"00",
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
-- sync operation
WORD_SYNC_IN => word_sync_i,
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- GLOBAL_RESET_IN => '0',
- GLOBAL_RESET_OUT => master_reset_i,
+ GLOBAL_RESET_IN => master_reset_i,
+ GLOBAL_RESET_OUT => open,
TX_PLL_LOL_IN => tx_pll_lol_all_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
DEBUG_OUT => open
);
--- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
--- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(2),
--- MEDIA_MED2INT(1) => med2int(3),
--- MEDIA_MED2INT(2) => med2int(0),
--- MEDIA_MED2INT(3) => med2int(1),
--- MEDIA_INT2MED(0) => int2med(2),
--- MEDIA_INT2MED(1) => int2med(3),
--- MEDIA_INT2MED(2) => int2med(0),
--- MEDIA_INT2MED(3) => int2med(1),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => HUB_MOD0(3),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(4),
--- SD_PRSNT_N_IN(2) => HUB_MOD0(1),
--- SD_PRSNT_N_IN(3) => HUB_MOD0(2),
--- SD_LOS_IN(0) => HUB_LOS(3),
--- SD_LOS_IN(1) => HUB_LOS(4),
--- SD_LOS_IN(2) => HUB_LOS(1),
--- SD_LOS_IN(3) => HUB_LOS(2),
--- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
--- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
--- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
--- --Control Interface
--- BUS_RX => bussci3_rx,
--- BUS_TX => bussci3_tx,
--- -- Status and control port
--- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
-
---------------------------------------------------------------------------
-- PCSD GBE or 2 downlinks
---------------------------------------------------------------------------
gen_PCSD : if INCLUDE_GBE = c_NO generate
THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS
generic map(
- SERDES_NUM => 3,
SIM_MODE => 0,
IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED),
IS_WAP_ZERO => 1
RESET => reset_i,
CLEAR => clear_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(8),
- MEDIA_MED2INT(1) => med2int(7),
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => open,
- MEDIA_INT2MED(0) => int2med(8),
- MEDIA_INT2MED(1) => int2med(7),
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => open,
+ MEDIA_MED2INT(0) => med2int(8),
+ MEDIA_MED2INT(1) => med2int(7),
+ MEDIA_MED2INT(2) => open,
+ MEDIA_MED2INT(3) => open,
+ MEDIA_INT2MED(0) => int2med(8),
+ MEDIA_INT2MED(1) => int2med(7),
+ MEDIA_INT2MED(2) => open,
+ MEDIA_INT2MED(3) => open,
-- komma operation
- RX_DLM_OUT => open, --: out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active
- RX_DLM_WORD_OUT => open, --: out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered
- TX_DLM_IN => rx_dlm_i, --'0', --: in std_logic;
- TX_DLM_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
- RX_RST_OUT => open, --: out std_logic; -- RST received, one clock cycle active
- RX_RST_WORD_OUT => open, --: out std_logic_vector(7 downto 0); -- RST data byte, registered
- TX_RST_IN => '0', --: in std_logic;
- TX_RST_WORD_IN => x"00", --: in std_logic_vector(7 downto 0);
+ RX_DLM_OUT => open,
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => x"00",
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
-- sync operation
WORD_SYNC_IN => word_sync_i,
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- GLOBAL_RESET_IN => '0',
- GLOBAL_RESET_OUT => master_reset_i,
+ GLOBAL_RESET_IN => master_reset_i,
+ GLOBAL_RESET_OUT => open,
TX_PLL_LOL_IN => tx_pll_lol_all_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0", -- BUG
- --SFP Connection
-
+ --SFP Connection
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
SD_PRSNT_N_IN(1) => HUB_MOD0(8),
SD_PRSNT_N_IN(2) => '1',
);
end generate;
--- THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_4
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
--- IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(8),
--- MEDIA_MED2INT(1) => med2int(7),
--- MEDIA_INT2MED(0) => int2med(8),
--- MEDIA_INT2MED(1) => int2med(7),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(8),
--- SD_LOS_IN(0) => SFP_LOS(0),
--- SD_LOS_IN(1) => HUB_LOS(8),
--- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(8),
--- --Control Interface
--- BUS_RX => bussci4_rx,
--- BUS_TX => bussci4_tx,
--- -- Status and control port
--- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
-
---------------------------------------------------------------------------
-- GbE
---------------------------------------------------------------------------
busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write;
end generate;
-
gen_GBE : if INCLUDE_GBE = 1 generate
GBE : entity work.gbe_wrapper
generic map(
);
end generate;
-
---------------------------------------------------------------------------
-- Hub
---------------------------------------------------------------------------
gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate
-
THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
generic map(
HUB_USED_CHANNELS => (1,1,0,1),
gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate
-
THE_HUB : trb_net16_hub_base
generic map(
HUB_USED_CHANNELS => (1,1,0,1),
-- LED
---------------------------------------------------------------------------
--LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
- LED_GREEN <= debug_clock_reset(0);
- LED_ORANGE <= debug_clock_reset(1);
- LED_RED <= not sed_error_i;
- LED_YELLOW <= debug_clock_reset(2);
-
-
+ LED_GREEN <= not debug_i(11); -- LFD --debug_clock_reset(0);
+ LED_ORANGE <= not debug_i(10); -- LHD --debug_clock_reset(1);
+ LED_RED <= not debug_i(8); -- LRR --not sed_error_i;
+ LED_YELLOW <= not debug_i(7); -- LTR --debug_clock_reset(2);
gen_hub_leds : for i in 0 to 6 generate
LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9);
LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else
not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
'1';
-
--- TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
--- TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
--- TEST_LINE(2) <= clear_i;
--- TEST_LINE(3) <= reset_i;
--- TEST_LINE(4) <= time_counter(26);
--- TEST_LINE(5) <= BACK_GPIO(1);
--- TEST_LINE(6) <= sfp_txdis_i;
--- TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
-
end architecture;
jspc29 / trb3sc.git / commitdiff