------------------------------------------------------------------------------
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
-
+ constant EVENT_MAX_SIZE : integer := 1024; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+ constant FPGA_TYPE : integer := 3;
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
constant USE_200MHZOSCILLATOR : integer := c_YES;
constant TRIG_GEN_INPUT_NUM : integer := 64;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 64;
+
+ constant USE_GBE : integer := c_YES;
------------------------------------------------------------------------------
--End of design configuration
constant CLOCK_FREQUENCY : integer;
constant MEDIA_FREQUENCY : integer;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
-
+ constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
end;
t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
TOPNAME => "trb3sc_basic",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.8_x64',
-synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
+synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/',
#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
#Include only necessary lpf files #trb3sc_rj_bynumbers - for Hades trigger gen
pinout_file => 'trb3sc_rj_bynumbers', #name of pin-out file, if not equal TOPNAME
include_TDC => 0,
-include_GBE => 0,
+include_GBE => 1,
#Report settings
firefox_open => 0,
MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;
+
+FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
+FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/clk_125_rx_from_pcs[0]" 125 MHz;
+LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
#Basic Infrastructure
add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
-
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
add_file -vhdl -lib work "./trb3sc_basic.vhd"
#add_file -fpga_constraint "./synplify.fdc"
--READOUT
signal readout_rx : READOUT_RX;
- signal readout_tx : readout_tx_array_t(0 to 0);
+ signal readout_tx : readout_tx_array_t(0 to 1);
signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busrdo_rx, bus_master_out : CTRLBUS_RX;
signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busrdo_tx, bus_master_in : CTRLBUS_TX;
attribute syn_keep of bustc_rx : signal is true;
attribute syn_preserve of bustc_rx : signal is true;
- type state_t is (IDLE, WRITE, FINISH, BUSYEND);
- signal state : state_t;
- signal data_counter, data_amount : unsigned(15 downto 0) := (others => '0');
+
+
+ type uarr15 is array(0 to 7) of unsigned(15 downto 0);
+ signal data_counter : uarr15;
+ signal data_amount : unsigned(15 downto 0) := (others => '0');
begin
NET_CLK_FULL_IN => med2int(0).clk_full,
NET_CLK_HALF_IN => med2int(0).clk_half,
RESET_FROM_NET => med2int(0).stat_op(13),
-
+ SEND_RESET_IN => med2int(0).stat_op(15), --?
+
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
CTRL_DEBUG => open
);
- SFP_TX_DIS(0) <= '1';
+ SFP_TX_DIS(0) <= '0';
gen_sfp_con : if SERDES_NUM = 3 generate
sfp_los_i <= SFP_LOS(1);
sfp_prsnt_i <= SFP_MOD0(1);
THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
generic map (
ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
+ BROADCAST_BITMASK => BROADCAST_BITMASK,
REGIO_INIT_ENDPOINT_ID => x"0001",
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1,
+ DATA_INTERFACE_NUMBER => 2,
DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
DATA_BUFFER_WIDTH => 32,
DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**8
+ HEADER_BUFFER_FULL_THRESH => 2**8,
+ USE_GBE => USE_GBE
)
port map(
CLK => clk_sys,
RESET => reset_i,
CLK_EN => '1',
+ CLK_125 => CLK_SUPPL_PCLK,
+ CLEAR_N => GSR_N,
-- Media direction port
MEDIA_MED2INT => med2int(0),
end if;
end process;
+
+gen_RDO : for i in 0 to 1 generate
+ type state_t is (IDLE, WRITE, FINISH, BUSYEND);
+ signal state : state_t;
+begin
+
THE_RDO : process begin
wait until rising_edge(clk_sys);
- readout_tx(0).busy_release <= '0';
- readout_tx(0).data_write <= '0';
- readout_tx(0).data_finished <= '0';
+ readout_tx(i).busy_release <= '0';
+ readout_tx(i).data_write <= '0';
+ readout_tx(i).data_finished <= '0';
case state is
when IDLE =>
if readout_rx.valid_timing_trg = '1' or readout_rx.valid_notiming_trg = '1' then
state <= WRITE;
end if;
- if readout_rx.invalid_trg = '1' then
+ if readout_rx.invalid_trg = '1' or data_amount = 0 then
state <= FINISH;
end if;
- data_counter <= 0;
+ data_counter(i) <= 1;
when WRITE =>
- readout_tx(0).data <= timer.microsecond(15 downto 0) & std_logic_vector(data_counter);
- readout_tx(0).data_write <= '1';
- data_counter <= data_counter + 1;
- if data_counter = data_amount then
+ readout_tx(i).data <= timer.microsecond(15 downto 0) & std_logic_vector(data_counter(i));
+ readout_tx(i).data_write <= '1';
+ data_counter(i) <= data_counter(i) + 1;
+ if data_counter(i) = data_amount then
state <= FINISH;
end if;
when FINISH =>
state <= BUSYEND;
- readout_tx(0).data_finished <= '1';
+ readout_tx(i).data_finished <= '1';
when BUSYEND =>
state <= IDLE;
- readout_tx(0).busy_release <= '1';
+ readout_tx(i).busy_release <= '1';
end case;
end process;
-
+end generate;
end architecture;
jspc29 / trb3sc.git / commitdiff