entity med_ecp5_sfp_sync is
generic(
+ USE_NEW_ECP5_RESET : integer := c_YES;
SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_YES --select slave mode
);
signal rx_pcs_rst : std_logic;
signal rst_qd : std_logic;
signal serdes_rst_qd : std_logic;
+signal signal_detect_i : std_logic;
signal rx_los_low : std_logic;
signal lsm_status : std_logic;
serdes_sync_0_rx_cv_err(0) => rx_error,
serdes_sync_0_tx_idle_c => '0',
- serdes_sync_0_signal_detect_c => '0',
+ serdes_sync_0_signal_detect_c => signal_detect_i,
serdes_sync_0_rx_los_low_s => rx_los_low,
serdes_sync_0_lsm_status_s => lsm_status,
serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol,
serdes_sync_0_rsl_tx_rdy => tx_ready
);
end generate;
--- gen_pcs1 : if SERDES_NUM = 1 generate
--- THE_SERDES : entity work.pcs1
--- port map(
--- serdes_sync_0_hdinp => hdinp,
--- serdes_sync_0_hdinn => hdinn,
--- serdes_sync_0_hdoutp => hdoutp,
--- serdes_sync_0_hdoutn => hdoutn,
--- serdes_sync_0_rxrefclk => CLK_INTERNAL_FULL,
--- serdes_sync_0_rx_pclk => clk_rx_full,
--- serdes_sync_0_tx_pclk => clk_tx_full,
---
--- serdes_sync_0_txdata => tx_data,
--- serdes_sync_0_tx_k(0) => tx_k,
--- serdes_sync_0_tx_force_disp(0) => '0',
--- serdes_sync_0_tx_disp_sel(0) => '0',
--- serdes_sync_0_rxdata => rx_data,
--- serdes_sync_0_rx_k(0) => rx_k,
--- serdes_sync_0_rx_disp_err(0) => open,
--- serdes_sync_0_rx_cv_err(0) => rx_error,
---
--- serdes_sync_0_tx_idle_c => '0',
--- serdes_sync_0_signal_detect_c => '0',
--- serdes_sync_0_rx_los_low_s => rx_los_low,
--- serdes_sync_0_lsm_status_s => lsm_status,
--- serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol,
--- serdes_sync_0_rx_pcs_rst_c => rx_pcs_rst,
--- serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst,
--- serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst,
---
---
--- serdes_sync_0_sci_wrdata => sci_data_in_i,
--- serdes_sync_0_sci_rddata => sci_data_out_i,
--- serdes_sync_0_sci_addr => sci_addr_i,
--- serdes_sync_0_sci_en_dual => reset_n,
--- serdes_sync_0_sci_sel_dual => sci_ch_i(4),
--- serdes_sync_0_sci_en => reset_n,
--- serdes_sync_0_sci_sel => sci_ch_i(0),
--- serdes_sync_0_sci_rd => sci_read_i,
--- serdes_sync_0_sci_wrn => sci_write_i,
--- serdes_sync_0_sci_int => open,
---
--- serdes_sync_0_cyawstn => '0', --?
--- serdes_sync_0_rst_dual_c => rst_qd,
--- serdes_sync_0_serdes_rst_dual_c => '0',
--- serdes_sync_0_tx_pwrup_c => '1',
--- serdes_sync_0_rx_pwrup_c => '1',
--- serdes_sync_0_serdes_pdb => '1',
--- serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst,
---
--- serdes_sync_0_pll_refclki => CLK_REF_FULL,
--- serdes_sync_0_pll_lol => tx_pll_lol,
--- serdes_sync_0_rsl_disable => '1',
--- serdes_sync_0_rsl_rst => '0',
--- serdes_sync_0_rsl_rx_rdy => rx_ready,
--- serdes_sync_0_rsl_tx_rdy => tx_ready
--- );
--- end generate;
+
+
gen_pcs2 : if SERDES_NUM = 2 generate
THE_SERDES : entity work.pcs2
port map(
serdes_sync_0_rx_cv_err(0) => rx_error,
serdes_sync_0_tx_idle_c => '0',
- serdes_sync_0_signal_detect_c => '0',
+ serdes_sync_0_signal_detect_c => signal_detect_i,
serdes_sync_0_rx_los_low_s => rx_los_low,
serdes_sync_0_lsm_status_s => lsm_status,
serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol,
wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
else wa_position(15 downto 12) when SERDES_NUM = 3;
+ signal_detect_i <= '1' when USE_NEW_ECP5_RESET = 1 else '0';
+
THE_MED_CONTROL : entity work.med_sync_control
generic map(
+ USE_NEW_ECP5_RESET => USE_NEW_ECP5_RESET,
IS_SYNC_SLAVE => IS_SYNC_SLAVE,
IS_TX_RESET => 1
)
SFP_LOS => SD_LOS_IN,
TX_LOL => tx_pll_lol,
+ RX_CV => rx_error, -- NEW
+ RX_LSM => lsm_status, -- NEW
RX_CDR_LOL => rx_cdr_lol,
RX_LOS => rx_los_low,
WA_POSITION => wa_position_sel,
entity med_ecp5_sfp_sync_2 is
generic(
+ USE_NEW_ECP5_RESET : integer := c_YES;
DUAL : integer := 0; --which Dual to use
IS_SYNC_SLAVE : int_array_t(0 to 1) := (c_YES, c_NO) --select slave mode
);
signal rx_pcs_rst : std_logic_vector(1 downto 0);
signal rst_qd : std_logic_vector(1 downto 0);
signal serdes_rst_qd : std_logic_vector(1 downto 0);
+signal signal_detect_i : std_logic;
signal rx_los_low : std_logic_vector(1 downto 0);
signal lsm_status : std_logic_vector(1 downto 0);
-- clk_200_i <= clk_200_internal;
-- end generate;
+ signal_detect_i <= '1' when USE_NEW_ECP5_RESET = 1 else '0';
-------------------------------------------------
-- Serdes
serdes0_rxrefclk => CLK_INTERNAL_FULL,
serdes0_rx_serdes_rst_c => rx_serdes_rst(0),
serdes0_serdes_rst_dual_c => '0',
- serdes0_signal_detect_c => '0',
+ serdes0_signal_detect_c => signal_detect_i,
serdes0_txdata => tx_data(0),
serdes0_tx_disp_sel(0) => '0',
serdes0_tx_force_disp(0) => '0',
serdes0_rxrefclk => CLK_INTERNAL_FULL,
serdes0_rx_serdes_rst_c => rx_serdes_rst(0),
serdes0_serdes_rst_dual_c => '0',
- serdes0_signal_detect_c => '0',
+ serdes0_signal_detect_c => signal_detect_i,
serdes0_txdata => tx_data(0),
serdes0_tx_disp_sel(0) => '0',
serdes0_tx_force_disp(0) => '0',
gen_channels : for i in 0 to 1 generate
THE_MED_CONTROL : entity work.med_sync_control
generic map(
+ USE_NEW_ECP5_RESET => USE_NEW_ECP5_RESET,
IS_SYNC_SLAVE => IS_SYNC_SLAVE(i),
IS_TX_RESET => 1
)
SFP_LOS => SD_LOS_IN(i),
TX_LOL => tx_pll_lol,
+ RX_CV => rx_error(i), -- NEW
+ RX_LSM => lsm_status(i), -- NEW
RX_CDR_LOL => rx_cdr_lol(i),
RX_LOS => rx_los_low(i),
WA_POSITION => x"0",
entity med_sync_control is
generic(
+ USE_NEW_ECP5_RESET : integer := 0;
IS_SYNC_SLAVE : integer := 1;
IS_TX_RESET : integer := 1
);
SFP_LOS : in std_logic;
TX_LOL : in std_logic;
+ RX_CV : in std_logic := '0'; -- NEW
+ RX_LSM : in std_logic := '1'; -- NEW
RX_CDR_LOL : in std_logic;
RX_LOS : in std_logic;
WA_POSITION : in std_logic_vector(3 downto 0);
RX_SERDES_RST : out std_logic;
RX_PCS_RST : out std_logic;
QUAD_RST : out std_logic;
- TX_PCS_RST : out std_logic;
+ TX_PCS_RST : out std_logic; --sync to CLK_REF
MEDIA_MED2INT : out MED2INT;
MEDIA_INT2MED : in INT2MED;
signal rst_n_tx : std_logic;
signal finished_reset_rx : std_logic;
signal finished_reset_rx_q : std_logic;
+signal finished_reset_rx_qrx : std_logic;
signal finished_reset_tx : std_logic;
signal finished_reset_tx_q : std_logic;
-------------------------------------------------
-- Reset RX FSM
-------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => CLK_REF,
- TX_PLL_LOL_QD_S => TX_LOL,
- RX_SERDES_RST_CH_C => rx_serdes_rst_i,
- RX_CDR_LOL_CH_S => RX_CDR_LOL,
- RX_LOS_LOW_CH_S => RX_LOS,
- RX_PCS_RST_CH_C => rx_pcs_rst_i,
- WA_POSITION => wa_position_rx,
- NORMAL_OPERATION_OUT => finished_reset_rx,
- STATE_OUT => rx_fsm_state
- );
+gen_rx_fsm : if USE_NEW_ECP5_RESET = 0 generate
+ THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => rst_n,
+ RX_REFCLK => CLK_REF,
+ TX_PLL_LOL_QD_S => TX_LOL,
+ RX_SERDES_RST_CH_C => rx_serdes_rst_i,
+ RX_CDR_LOL_CH_S => RX_CDR_LOL,
+ RX_LOS_LOW_CH_S => RX_LOS,
+ RX_PCS_RST_CH_C => rx_pcs_rst_i,
+ WA_POSITION => wa_position_rx,
+ NORMAL_OPERATION_OUT => finished_reset_rx,
+ STATE_OUT => rx_fsm_state
+ );
+else generate
+ THE_MAIN_RX_RST: main_rx_reset_RS
+ port map(
+ CLEAR => CLEAR, --CLEAR, -- should work
+ CLK_REF => CLK_REF, -- ok
+ CDR_LOL_IN => RX_CDR_LOL, -- ok
+ CV_IN => RX_CV, -- ok
+ LSM_IN => RX_LSM, -- ok
+ LOS_IN => RX_LOS, -- ok
+ WAP_ZERO_IN => '1', -- not needed
+ -- outputs
+ WAP_REQ_OUT => open, -- not needed
+ RX_SERDES_RST_OUT => rx_serdes_rst_i, -- ok -- CLK_REF based
+ RX_PCS_RST_OUT => rx_pcs_rst_i, -- ok -- CLK_REF based
+ LINK_RX_READY_OUT => finished_reset_rx, -- should work -- CLK_REF based
+ STATE_OUT => rx_fsm_state
+ );
+end generate;
-- crossing the abbyss
THE_ABBYSS_PROC: process( CLK_RXI )
-------------------------------------------------
-- Reset TX FSM
-------------------------------------------------
-THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n_tx,
- TX_REFCLK => CLK_REF,
- TX_PLL_LOL_QD_S => TX_LOL,
- RST_QD_C => quad_rst_i,
- TX_PCS_RST_CH_C => tx_pcs_rst_i,
- NORMAL_OPERATION_OUT => finished_reset_tx,
- STATE_OUT => tx_fsm_state
+
+gen_tx_fsm : if USE_NEW_ECP5_RESET = 0 generate
+
+ THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => rst_n_tx,
+ TX_REFCLK => CLK_REF,
+ TX_PLL_LOL_QD_S => TX_LOL,
+ RST_QD_C => quad_rst_i,
+ TX_PCS_RST_CH_C => tx_pcs_rst_i,
+ NORMAL_OPERATION_OUT => finished_reset_tx,
+ STATE_OUT => tx_fsm_state
+ );
+else generate
+ THE_MAIN_TX_RST: main_tx_reset_RS
+ port map (
+ CLEAR => CLEAR, --CLEAR, -- should work
+ CLK_REF => CLK_REF, -- should work
+ TX_PLL_LOL_IN => TX_LOL, -- ok
+ TX_CLOCK_AVAIL_IN => '1', -- not needed
+ TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, -- ok
+ SYNC_TX_QUAD_OUT => open,
+ LINK_TX_READY_OUT => finished_reset_tx, -- should work
+ STATE_OUT => open
);
+ quad_rst_i <= '0';
+end generate;
-- may also need sync?
TX_PCS_RST <= tx_pcs_rst_i;
LINK_RESET_FIN_RX : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
D_IN(0) => finished_reset_rx,
D_OUT(0) => finished_reset_rx_q);
-
+LINK_RESET_FIN_RX_2: signal_sync port map(RESET => '0',CLK0 => CLK_RXI, CLK1 => CLK_RXI,
+ D_IN(0) => finished_reset_rx,
+ D_OUT(0) => finished_reset_rx_qrx);
+
START_TIMER_PROC : process( CLK_SYS )
begin
if( rising_edge(CLK_SYS) ) then
SEND_LINK_RESET_OUT => send_link_reset_i,
MAKE_RESET_OUT => make_link_reset_i,
RX_ALLOW_IN => rx_allow,
- RX_RESET_FINISHED => finished_reset_rx,
+ RX_RESET_FINISHED => finished_reset_rx_qrx,
GOT_LINK_READY => got_link_ready_i,
DEBUG_OUT => DEBUG_RX_CONTROL,
sd_los_i <= SFP_LOS when rising_edge(CLK_SYS);
media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS);
-media_med2int_i.stat_op(14) <= '0';
+media_med2int_i.stat_op(14) <= not (rx_allow and tx_allow); --'0';
media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset
media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm;
media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx;
);
end component;
+component main_tx_reset_RS is
+ port(
+ CLEAR : in std_logic; -- async reset, active high, should not be used!
+ CLK_REF : in std_logic; -- usually local oscillator sourced
+ TX_PLL_LOL_IN : in std_logic; -- externally or'ed
+ TX_CLOCK_AVAIL_IN : in std_logic; -- suitable TX clock available
+ TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset
+ SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0
+ LINK_TX_READY_OUT : out std_logic; -- TX lane can use used now
+ STATE_OUT : out std_logic_vector(3 downto 0)
+ );
+end component;
+component main_rx_reset_RS is
+ port (
+ CLEAR : in std_logic; -- do not use
+ CLK_REF : in std_logic; -- usually local oscillator sourced
+ CDR_LOL_IN : in std_logic;
+ CV_IN : in std_logic;
+ LSM_IN : in std_logic;
+ LOS_IN : in std_logic;
+ WAP_ZERO_IN : in std_logic;
+ -- outputs
+ WAP_REQ_OUT : out std_logic;
+ RX_SERDES_RST_OUT : out std_logic;
+ RX_PCS_RST_OUT : out std_logic;
+ LINK_RX_READY_OUT : out std_logic;
+ STATE_OUT : out std_logic_vector(3 downto 0)
+ );
+end component;
end package;
jspc29 / trbnet.git / commitdiff