--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 2.5;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+#All DQ groups from one bank are grouped.
+#All DQS are inserted in the DQ lines at position 6 and 7
+#DQ 6-9 are shifted to 8-11
+#Order per bank is kept, i.e. adjacent numbers have adjacent pins
+#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
+#even numbers are positive LVDS line, odd numbers are negative LVDS line
+#DQUL can be switched to 1.8V
+
+LOCATE COMP "DQLL_0" SITE "P1"; #DQLL0_0 #1
+LOCATE COMP "DQLL_1" SITE "P2"; #DQLL0_1 #3
+LOCATE COMP "DQLL_2" SITE "T2"; #DQLL0_2 #5
+LOCATE COMP "DQLL_3" SITE "U3"; #DQLL0_3 #7
+LOCATE COMP "DQLL_4" SITE "R1"; #DQLL0_4 #9
+LOCATE COMP "DQLL_5" SITE "R2"; #DQLL0_5 #11
+LOCATE COMP "DQLL_6" SITE "N3"; #DQSLL0_T #13
+LOCATE COMP "DQLL_7" SITE "P3"; #DQSLL0_C #15
+LOCATE COMP "DQLL_8" SITE "P5"; #DQLL0_6 #17
+LOCATE COMP "DQLL_9" SITE "P6"; #DQLL0_7 #19
+LOCATE COMP "DQLL_10" SITE "N5"; #DQLL0_8 #21
+LOCATE COMP "DQLL_11" SITE "N6"; #DQLL0_9 #23
+
+LOCATE COMP "DQLL_12" SITE "V1"; #DQLL1_0 #26
+LOCATE COMP "DQLL_13" SITE "U2"; #DQLL1_1 #28
+LOCATE COMP "DQLL_14" SITE "T1"; #DQLL1_2 #30
+LOCATE COMP "DQLL_15" SITE "U1"; #DQLL1_3 #32
+LOCATE COMP "DQLL_16" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "DQLL_17" SITE "R3"; #DQLL1_5 #36
+LOCATE COMP "DQLL_18" SITE "T3"; #DQSLL1_T #38
+LOCATE COMP "DQLL_19" SITE "R4"; #DQSLL1_C #40
+LOCATE COMP "DQLL_20" SITE "R5"; #DQLL1_6 #42
+LOCATE COMP "DQLL_21" SITE "R6"; #DQLL1_7 #44
+LOCATE COMP "DQLL_22" SITE "T7"; #DQLL1_8 #46
+LOCATE COMP "DQLL_23" SITE "T8"; #DQLL1_9 #48
+
+LOCATE COMP "DQLL_24" SITE "AC2"; #DQLL2_0 #25
+LOCATE COMP "DQLL_25" SITE "AC3"; #DQLL2_1 #27
+LOCATE COMP "DQLL_26" SITE "AB1"; #DQLL2_2 #29
+LOCATE COMP "DQLL_27" SITE "AC1"; #DQLL2_3 #31
+LOCATE COMP "DQLL_28" SITE "AA1"; #DQLL2_4 #33
+LOCATE COMP "DQLL_29" SITE "AA2"; #DQLL2_5 #35
+LOCATE COMP "DQLL_30" SITE "W7"; #DQLL2_T #37 #should be DQSLL2
+LOCATE COMP "DQLL_31" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
+LOCATE COMP "DQLL_32" SITE "Y5"; #DQLL2_6 #41
+LOCATE COMP "DQLL_33" SITE "AA5"; #DQLL2_7 #43
+LOCATE COMP "DQLL_34" SITE "V6"; #DQLL2_8 #45
+LOCATE COMP "DQLL_35" SITE "V7"; #DQLL2_9 #47
+
+LOCATE COMP "DQLL_36" SITE "AD1"; #DQLL3_0 #2
+LOCATE COMP "DQLL_37" SITE "AD2"; #DQLL3_1 #4
+LOCATE COMP "DQLL_38" SITE "AB5"; #DQLL3_2 #6
+LOCATE COMP "DQLL_39" SITE "AB6"; #DQLL3_3 #8
+LOCATE COMP "DQLL_40" SITE "AB3"; #DQLL3_4 #10
+LOCATE COMP "DQLL_41" SITE "AB4"; #DQLL3_5 #12
+LOCATE COMP "DQLL_42" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
+LOCATE COMP "DQLL_43" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "DQLL_44" SITE "AA3"; #DQLL3_6 #18
+LOCATE COMP "DQLL_45" SITE "AA4"; #DQLL3_7 #20
+LOCATE COMP "DQLL_46" SITE "W8"; #DQLL3_8 #22
+LOCATE COMP "DQLL_47" SITE "W9"; #DQLL3_9 #24
+
+LOCATE COMP "DQLR_0" SITE "AC26"; #DQLR0_0 #129
+LOCATE COMP "DQLR_1" SITE "AC25"; #DQLR0_1 #131
+LOCATE COMP "DQLR_2" SITE "Y19"; #DQLR0_2 #133
+LOCATE COMP "DQLR_3" SITE "Y20"; #DQLR0_3 #135
+LOCATE COMP "DQLR_4" SITE "AB24"; #DQLR0_4 #137
+LOCATE COMP "DQLR_5" SITE "AC24"; #DQLR0_5 #139
+LOCATE COMP "DQLR_6" SITE "Y22"; #DQSLR0_T #141
+LOCATE COMP "DQLR_7" SITE "AA22"; #DQSLR0_C #143
+LOCATE COMP "DQLR_8" SITE "AD24"; #DQLR0_6 #145
+LOCATE COMP "DQLR_9" SITE "AE24"; #DQLR0_7 #147
+LOCATE COMP "DQLR_10" SITE "AE25"; #DQLR0_8 #149
+LOCATE COMP "DQLR_11" SITE "AF24"; #DQLR0_9 #151
+
+LOCATE COMP "DQLR_12" SITE "W23"; #DQLR1_0 #169
+LOCATE COMP "DQLR_13" SITE "W22"; #DQLR1_1 #171
+LOCATE COMP "DQLR_14" SITE "AA25"; #DQLR1_2 #173
+LOCATE COMP "DQLR_15" SITE "Y24"; #DQLR1_3 #175
+LOCATE COMP "DQLR_16" SITE "AA26"; #DQLR1_4 #177
+LOCATE COMP "DQLR_17" SITE "AB26"; #DQLR1_5 #179
+LOCATE COMP "DQLR_18" SITE "W21"; #DQSLR1_T #181
+LOCATE COMP "DQLR_19" SITE "W20"; #DQSLR1_C #183
+LOCATE COMP "DQLR_20" SITE "AA24"; #DQLR1_6 #185
+LOCATE COMP "DQLR_21" SITE "AA23"; #DQLR1_7 #187
+LOCATE COMP "DQLR_22" SITE "AD26"; #DQLR1_8 #189
+LOCATE COMP "DQLR_23" SITE "AD25"; #DQLR1_9 #191
+
+LOCATE COMP "DQLR_24" SITE "R25"; #DQLR2_0 #170
+LOCATE COMP "DQLR_25" SITE "R26"; #DQLR2_1 #172
+LOCATE COMP "DQLR_26" SITE "T25"; #DQLR2_2 #174
+LOCATE COMP "DQLR_27" SITE "T24"; #DQLR2_3 #176
+LOCATE COMP "DQLR_28" SITE "T26"; #DQLR2_4 #178
+LOCATE COMP "DQLR_29" SITE "U26"; #DQLR2_5 #180
+LOCATE COMP "DQLR_30" SITE "V21"; #DQSLR2_T #182
+LOCATE COMP "DQLR_31" SITE "V22"; #DQSLR2_C #184
+LOCATE COMP "DQLR_32" SITE "U24"; #DQLR2_6 #186
+LOCATE COMP "DQLR_33" SITE "V24"; #DQLR2_7 #188
+LOCATE COMP "DQLR_34" SITE "U23"; #DQLR2_8 #190
+LOCATE COMP "DQLR_35" SITE "U22"; #DQLR2_9 #192
+
+LOCATE COMP "DQUL_0" SITE "B2"; #DQUL0_0 #74
+LOCATE COMP "DQUL_1" SITE "B3"; #DQUL0_1 #76
+LOCATE COMP "DQUL_2" SITE "D4"; #DQUL0_2 #78
+LOCATE COMP "DQUL_3" SITE "E4"; #DQUL0_3 #80
+LOCATE COMP "DQUL_4" SITE "C3"; #DQUL0_4 #82
+LOCATE COMP "DQUL_5" SITE "D3"; #DQUL0_5 #84
+LOCATE COMP "DQUL_6" SITE "G5"; #DQSUL0_T #86
+LOCATE COMP "DQUL_7" SITE "G6"; #DQSUL0_C #88
+LOCATE COMP "DQUL_8" SITE "E3"; #DQUL0_6 #90
+LOCATE COMP "DQUL_9" SITE "F4"; #DQUL0_7 #92
+LOCATE COMP "DQUL_10" SITE "H6"; #DQUL0_8 #94
+LOCATE COMP "DQUL_11" SITE "J6"; #DQUL0_9 #96
+
+LOCATE COMP "DQUL_12" SITE "G2"; #DQUL1_0 #73
+LOCATE COMP "DQUL_13" SITE "G3"; #DQUL1_1 #75
+LOCATE COMP "DQUL_14" SITE "F2"; #DQUL1_2 #77
+LOCATE COMP "DQUL_15" SITE "F3"; #DQUL1_3 #79
+LOCATE COMP "DQUL_16" SITE "C2"; #DQUL1_4 #81
+LOCATE COMP "DQUL_17" SITE "D2"; #DQUL1_5 #83
+LOCATE COMP "DQUL_18" SITE "K7"; #DQSUL1_T #85
+LOCATE COMP "DQUL_19" SITE "K6"; #DQSUL1_C #87
+LOCATE COMP "DQUL_20" SITE "H5"; #DQUL1_6 #89
+LOCATE COMP "DQUL_21" SITE "J5"; #DQUL1_7 #91
+LOCATE COMP "DQUL_22" SITE "K8"; #DQUL1_8 #93
+LOCATE COMP "DQUL_23" SITE "J7"; #DQUL1_9 #95
+
+LOCATE COMP "DQUL_24" SITE "K2"; #DQUL2_0 #50
+LOCATE COMP "DQUL_25" SITE "K1"; #DQUL2_1 #52
+LOCATE COMP "DQUL_26" SITE "J4"; #DQUL2_2 #54
+LOCATE COMP "DQUL_27" SITE "J3"; #DQUL2_3 #56
+LOCATE COMP "DQUL_28" SITE "D1"; #DQUL2_4 #58
+LOCATE COMP "DQUL_29" SITE "C1"; #DQUL2_5 #60
+LOCATE COMP "DQUL_30" SITE "K4"; #DQSUL2_T #62
+LOCATE COMP "DQUL_31" SITE "K5"; #DQSUL2_C #64
+LOCATE COMP "DQUL_32" SITE "E1"; #DQUL2_6 #66
+LOCATE COMP "DQUL_33" SITE "F1"; #DQUL2_7 #68
+LOCATE COMP "DQUL_34" SITE "L5"; #DQUL2_8 #70
+LOCATE COMP "DQUL_35" SITE "L6"; #DQUL2_9 #72
+
+LOCATE COMP "DQUL_36" SITE "H2"; #DQUL3_0 #49
+LOCATE COMP "DQUL_37" SITE "G1"; #DQUL3_1 #51
+LOCATE COMP "DQUL_38" SITE "K3"; #DQUL3_2 #53
+LOCATE COMP "DQUL_39" SITE "L3"; #DQUL3_3 #55
+LOCATE COMP "DQUL_40" SITE "H1"; #DQUL3_4 #57
+LOCATE COMP "DQUL_41" SITE "J1"; #DQUL3_5 #59
+LOCATE COMP "DQUL_42" SITE "M5"; #DQSUL3_T #61
+LOCATE COMP "DQUL_43" SITE "M6"; #DQSUL3_C #63
+LOCATE COMP "DQUL_44" SITE "L2"; #DQUL3_6 #65
+LOCATE COMP "DQUL_45" SITE "L1"; #DQUL3_7 #67
+
+
+LOCATE COMP "DQUR_0" SITE "J23"; #DQUR0_0 #105
+LOCATE COMP "DQUR_1" SITE "H23"; #DQUR0_1 #107
+LOCATE COMP "DQUR_2" SITE "G26"; #DQUR0_2 #109
+LOCATE COMP "DQUR_3" SITE "F26"; #DQUR0_3 #111
+LOCATE COMP "DQUR_4" SITE "F24"; #DQSUR0_T #113
+LOCATE COMP "DQUR_5" SITE "G24"; #DQSUR0_C #115
+LOCATE COMP "DQUR_6" SITE "H26"; #DQUR0_4 #117
+LOCATE COMP "DQUR_7" SITE "H25"; #DQUR0_5 #119
+LOCATE COMP "DQUR_8" SITE "K23"; #DQUR0_6 #121
+LOCATE COMP "DQUR_9" SITE "K22"; #DQUR0_7 #123
+# LOCATE COMP "DQUR_10" SITE "F25"; #DQUR0_8 #125 #input only
+# LOCATE COMP "DQUR_11" SITE "E26"; #DQUR0_9 #127 #input only
+
+LOCATE COMP "DQUR_10" SITE "H24"; #DQUR1_0 #106
+LOCATE COMP "DQUR_11" SITE "G25"; #DQUR1_1 #108
+LOCATE COMP "DQUR_12" SITE "L20"; #DQUR1_2 #110
+LOCATE COMP "DQUR_13" SITE "M21"; #DQUR1_3 #112
+LOCATE COMP "DQUR_14" SITE "K24"; #DQUR1_4 #114
+LOCATE COMP "DQUR_15" SITE "J24"; #DQUR1_5 #116
+LOCATE COMP "DQUR_16" SITE "M23"; #DQSUR1_T #118
+LOCATE COMP "DQUR_17" SITE "M24"; #DQSUR1_C #120
+LOCATE COMP "DQUR_18" SITE "L24"; #DQUR1_6 #122
+LOCATE COMP "DQUR_19" SITE "K25"; #DQUR1_7 #124
+LOCATE COMP "DQUR_20" SITE "M22"; #DQUR1_8 #126
+LOCATE COMP "DQUR_21" SITE "N21"; #DQUR1_9 #128
+LOCATE COMP "DQUR_22" SITE "J26"; #DQUR2_0 #130
+LOCATE COMP "DQUR_23" SITE "K26"; #DQUR2_1 #132
+LOCATE COMP "DQUR_24" SITE "N23"; #DQUR2_2 #134
+LOCATE COMP "DQUR_25" SITE "N22"; #DQUR2_3 #136
+LOCATE COMP "DQUR_26" SITE "K19"; #DQUR2_4 #138
+LOCATE COMP "DQUR_27" SITE "L19"; #DQUR2_5 #140
+LOCATE COMP "DQUR_28" SITE "P23"; #DQSUR2_T #142
+LOCATE COMP "DQUR_29" SITE "R22"; #DQSUR2_C #144
+LOCATE COMP "DQUR_30" SITE "L25"; #DQUR2_6 #146
+LOCATE COMP "DQUR_31" SITE "L26"; #DQUR2_7 #148
+LOCATE COMP "DQUR_32" SITE "P21"; #DQUR2_8 #150
+LOCATE COMP "DQUR_33" SITE "P22"; #DQUR2_9 #152
+
+DEFINE PORT GROUP "DQ_group" "DQ*" ;
+IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14";
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd"
-- INT_CHANNELS => (0,1,3,3,3,3,3,3),
USE_ONEWIRE => c_YES,
COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- HARDWARE_VERSION => x"91000000",
+ HARDWARE_VERSION => x"91003200",
INIT_ENDPOINT_ID => x"0000",
INIT_ADDRESS => x"F300",
USE_VAR_ENDPOINT_ID => c_YES,
# Basic Settings
#################################################################
- SYSCONFIG MCCLK_FREQ = 2.5;
+ SYSCONFIG MCCLK_FREQ = 20;
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "trb3_periph"; #Name of top-level entity
+my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+
+
+
+
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+# execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "trb3_periph"; #Name of top-level entity
+my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+
+
+
+
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+# execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+
+
+
+- change compile_munich.pl to contain correct paths to tools
+- link ../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt to ./workdir
+
+- change ../base/trb3_periph_nxyter.lpf to the pin names used for the nxyter addon (starting from line 92), remove all DQ* signals
+- add the signal names for the nxyter addon in the entity declaration of the top-level trb3_periph.vhd
+
+- add your vhdl files to trb3_periph_prj
+- Edit trb3_periph_constraints.lpf to contain the correct names of clock nets & pins - see the two comments in the second block.
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 11
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+
+
+
+
-- HIer meine register.....
-------------------------------------------------------------------------
--Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
+-- BUS_READ_ENABLE_OUT(2) => spimem_read_en,
+-- BUS_WRITE_ENABLE_OUT(2) => spimem_write_en,
+-- BUS_DATA_OUT(2*32+31 downto 2*32) => spimem_data_in,
+-- BUS_ADDR_OUT(2*16+5 downto 2*16) => spimem_addr,
+-- BUS_ADDR_OUT(2*16+15 downto 2*16+6) => open,
+-- BUS_TIMEOUT_OUT(2) => open,
+-- BUS_DATA_IN(2*32+31 downto 2*32) => spimem_data_out,
+-- BUS_DATAREADY_IN(2) => spimem_ack,
+-- BUS_WRITE_ACK_IN(2) => spimem_ack,
+-- BUS_NO_MORE_DATA_IN(2) => '0',
+-- BUS_UNKNOWN_ADDR_IN(2) => '0',
STAT_DEBUG => open
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 200 MHz;
+
+#Put the names of your DCO inputs here:
+ FREQUENCY PORT MADC1_DCO 360 MHz;
+ FREQUENCY PORT MADC2_DCO 360 MHz;
+
+#Change the next two lines to the clk_fast signal of the ADC
+ USE PRIMARY2EDGE NET "THE_ADC/clk_fast";
+ USE PRIMARY NET "THE_ADC/clk_fast";
+
+ USE PRIMARY NET "CLK_PCLK_LEFT";
+ USE PRIMARY NET "CLK_PCLK_LEFT_c";
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+
+
+#################################################################
+# Relax some of the timing constraints
+#################################################################
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
\ No newline at end of file
+++ /dev/null
-#List of all serial numbers for TRB3. Five entries for each board!
-
-# Serial # Unique ID
-########################################
-
- 0015 0x5f000002e2f93b28
- 0010 0xda000002e2e34f28
- 0011 0xf9000002e3039928
- 0012 0x91000002e2cd5228
- 0013 0x48000002e2e36028
-
- 0025 0x08000002e2e22b28
- 0020 0xa6000002e2e2df28
- 0021 0x51000002e2e22828
- 0022 0x72000002e2eb4628
- 0023 0xb0000002e311b928
-
- 0035 0x8f000002e312df28
- 0030 0xb8000002e312de28
- 0031 0x89000002e312ea28
- 0032 0x55000002e31f5b28
- 0033 0x0c000002e31f5828
-
- 0055 0x1e000002e30d6828
- 0050 0x23000002e303a828
- 0051 0xec000002e2cd5e28
- 0052 0xf2000002e312d328
- 0053 0xd3000002e30d7128
-
- 0075 0x9500000347f24328
- 0070 0x4300000348258728
- 0071 #no communication to FPGA
- 0072 0x98000003482ab428
- 0073 0x0e00000348180d28
-
-
-
-
- 0085 0x0f0000034822f028
- 0080 0xeb000003480eae28 #flash programming?
- 0081 0x91000003481be628
- 0082 0x59000003481b5c28
- 0083 0x57000003480ed128
-
-
- 0095 0x2500000347f25628
- 0090 0xe800000347f24f28
- 0091 0x5b000003481b4f28
- 0092 0xbf0000034822e528
- 0093 0x3700000348231428
-
-
- 0115 0x90000002e30db528 # new production from Visatronic
- 0110 0x58000003481bd928
- 0111 0x96000003480d8928
- 0112 0x7b000002e30db028
- 0113 0x31000002e30dbd28
-
- 0125 0x12000002e2d98d28
- 0120 0xcf000003480d8a28
- 0121 0x99000002e30e5728
- 0122 0x4e000002e2e24c28
- 0123 0x6a000002e2e24328
-
- 0135 0x8d00000337dfe828
- 0130 0xaf00000338095428
- 0131 0x2a00000338095328
- 0132 0x3900000338095d28
- 0133 0x6000000338095e28
-
-
- 0140 0x5100000337e59428
- 0141 0x9c00000337e58d28
- 0142 0xc600000337e51828
- 0143 0x1f00000337e5bf28
- 0145 0x4600000337e5bc28
-
- 0150 0x180000033829fa28
- 0151 0x9e00000338296b28
- 0152 0x0800000337e59728
- 0153 0x4900000337e12428
- 0155 0xc100000337e5a828
-
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
SERDES_INT_TX : out std_logic_vector(3 downto 0);
SERDES_INT_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+-- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+-- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
--Inter-FPGA Communication
FPGA5_COMM : inout std_logic_vector(11 downto 0);
--Bit 0/1 input, serial link RX active
THE_TDC : TDC
generic map (
+<<<<<<< trb3_periph.vhd
+ CHANNEL_NUMBER => 17, -- Number of TDC channels
+=======
CHANNEL_NUMBER => 65, -- Number of TDC channels
+>>>>>>> 1.3
STATUS_REG_NR => REGIO_NUM_STAT_REGS,
CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
port map (
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+<<<<<<< trb3_periph.vhd
+ HIT_IN => hit_in_i(16 downto 1), -- Channel start signals
+=======
HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
+>>>>>>> 1.3
TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
--
#create full lpf file
system("cp $BasePath/".$TOPNAME."_mainz.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+system("cat srcjan/".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
#set -e
my $tpmap = $TOPNAME . "_map" ;
system("mv $TOPNAME.ncd guidefile.ncd");
+<<<<<<< compile_periph_frankfurt.pl
+#-g guidefile.ncd
$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+=======
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+>>>>>>> 1.2
execute($c);
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-#add_file -vhdl -lib "work" "source/trb3_periph.vhd"
-
-#add_file -vhdl -lib "work" "source/Adder_304.vhd"
-#add_file -vhdl -lib "work" "source/bit_sync.vhd"
-#add_file -vhdl -lib "work" "source/Channel.vhd"
-#add_file -vhdl -lib "work" "source/ddr_off.vhd"
-#add_file -vhdl -lib "work" "source/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd"
-#add_file -vhdl -lib "work" "source/MB_SPI.vhd"
-#add_file -vhdl -lib "work" "source/pll_100_in_5_out.vhd"
-#add_file -vhdl -lib "work" "source/pll_100_in_40_out.vhd"
-#add_file -vhdl -lib "work" "source/Reference_channel.vhd"
-#add_file -vhdl -lib "work" "source/ROM_encoder_4.vhd"
-#add_file -vhdl -lib "work" "source/ROM_FIFO.vhd"
-#add_file -vhdl -lib "work" "source/TDC.vhd"
-#add_file -vhdl -lib "work" "source/up_counter.vhd"
-
-
-add_file -vhdl -lib "work" "trb3_periph.vhd"
-
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Adder_304.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/bit_sync.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Reference_channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/TDC.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/up_counter.vhd"
+
+
+add_file -vhdl -lib "work" "srcjan/trb3_periph.vhd"
+add_file -vhdl -lib "work" "srcjan/Adder_304.vhd"
+add_file -vhdl -lib "work" "srcjan/bit_sync.vhd"
+add_file -vhdl -lib "work" "srcjan/Channel.vhd"
+add_file -vhdl -lib "work" "srcjan/Channel_200.vhd"
+add_file -vhdl -lib "work" "srcjan/Encoder_304_Bit.vhd"
+add_file -vhdl -lib "work" "srcjan/FIFO_32x32_OutReg.vhd"
+add_file -vhdl -lib "work" "srcjan/Reference_channel.vhd"
+add_file -vhdl -lib "work" "srcjan/ROM_encoder_3.vhd"
+add_file -vhdl -lib "work" "srcjan/ROM_FIFO.vhd"
+add_file -vhdl -lib "work" "srcjan/TDC.vhd"
+add_file -vhdl -lib "work" "srcjan/up_counter.vhd"
jspc29 / trb3.git / commitdiff