+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-
-entity Adder_288 is
- port (CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(287 downto 0);
- DataB : in std_logic_vector(287 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(287 downto 0)
- );
-end Adder_288;
-
-architecture Structure of Adder_288 is
-
--- internal signal declarations
- signal r0_sum : std_logic_vector(287 downto 0);
- signal tsum : std_logic_vector(287 downto 0);
- signal co : std_logic_vector(143 downto 0);
- signal scuba_vlo : std_logic;
-
--- local component declarations
- component FADD2B
- port (A0 : in std_logic;
- A1 : in std_logic;
- B0 : in std_logic;
- B1 : in std_logic;
- CI : in std_logic;
- COUT : out std_logic;
- S0 : out std_logic;
- S1 : out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D : in std_logic;
- SP : in std_logic;
- CK : in std_logic;
- CD : in std_logic;
- Q : out std_logic);
- end component;
- component VLO
- port (Z : out std_logic);
- end component;
-
- attribute GSR : string;
- attribute GSR of FF_287 : label is "ENABLED";
- attribute GSR of FF_286 : label is "ENABLED";
- attribute GSR of FF_285 : label is "ENABLED";
- attribute GSR of FF_284 : label is "ENABLED";
- attribute GSR of FF_283 : label is "ENABLED";
- attribute GSR of FF_282 : label is "ENABLED";
- attribute GSR of FF_281 : label is "ENABLED";
- attribute GSR of FF_280 : label is "ENABLED";
- attribute GSR of FF_279 : label is "ENABLED";
- attribute GSR of FF_278 : label is "ENABLED";
- attribute GSR of FF_277 : label is "ENABLED";
- attribute GSR of FF_276 : label is "ENABLED";
- attribute GSR of FF_275 : label is "ENABLED";
- attribute GSR of FF_274 : label is "ENABLED";
- attribute GSR of FF_273 : label is "ENABLED";
- attribute GSR of FF_272 : label is "ENABLED";
- attribute GSR of FF_271 : label is "ENABLED";
- attribute GSR of FF_270 : label is "ENABLED";
- attribute GSR of FF_269 : label is "ENABLED";
- attribute GSR of FF_268 : label is "ENABLED";
- attribute GSR of FF_267 : label is "ENABLED";
- attribute GSR of FF_266 : label is "ENABLED";
- attribute GSR of FF_265 : label is "ENABLED";
- attribute GSR of FF_264 : label is "ENABLED";
- attribute GSR of FF_263 : label is "ENABLED";
- attribute GSR of FF_262 : label is "ENABLED";
- attribute GSR of FF_261 : label is "ENABLED";
- attribute GSR of FF_260 : label is "ENABLED";
- attribute GSR of FF_259 : label is "ENABLED";
- attribute GSR of FF_258 : label is "ENABLED";
- attribute GSR of FF_257 : label is "ENABLED";
- attribute GSR of FF_256 : label is "ENABLED";
- attribute GSR of FF_255 : label is "ENABLED";
- attribute GSR of FF_254 : label is "ENABLED";
- attribute GSR of FF_253 : label is "ENABLED";
- attribute GSR of FF_252 : label is "ENABLED";
- attribute GSR of FF_251 : label is "ENABLED";
- attribute GSR of FF_250 : label is "ENABLED";
- attribute GSR of FF_249 : label is "ENABLED";
- attribute GSR of FF_248 : label is "ENABLED";
- attribute GSR of FF_247 : label is "ENABLED";
- attribute GSR of FF_246 : label is "ENABLED";
- attribute GSR of FF_245 : label is "ENABLED";
- attribute GSR of FF_244 : label is "ENABLED";
- attribute GSR of FF_243 : label is "ENABLED";
- attribute GSR of FF_242 : label is "ENABLED";
- attribute GSR of FF_241 : label is "ENABLED";
- attribute GSR of FF_240 : label is "ENABLED";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
-
- -- component instantiation statements
- FF_287 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(287));
- FF_286 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(286));
- FF_285 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(285));
- FF_284 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(284));
- FF_283 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(283));
- FF_282 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(282));
- FF_281 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(281));
- FF_280 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(280));
- FF_279 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(279));
- FF_278 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(278));
- FF_277 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(277));
- FF_276 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(276));
- FF_275 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(275));
- FF_274 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(274));
- FF_273 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(273));
- FF_272 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(272));
- FF_271 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(271));
- FF_270 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(270));
- FF_269 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(269));
- FF_268 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(268));
- FF_267 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(267));
- FF_266 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(266));
- FF_265 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(265));
- FF_264 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(264));
- FF_263 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(263));
- FF_262 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(262));
- FF_261 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(261));
- FF_260 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(260));
- FF_259 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(259));
- FF_258 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(258));
- FF_257 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(257));
- FF_256 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(256));
- FF_255 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(255));
- FF_254 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(254));
- FF_253 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(253));
- FF_252 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(252));
- FF_251 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(251));
- FF_250 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(250));
- FF_249 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(249));
- FF_248 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(248));
- FF_247 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(247));
- FF_246 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(246));
- FF_245 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(245));
- FF_244 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(244));
- FF_243 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(243));
- FF_242 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(242));
- FF_241 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(241));
- FF_240 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(240));
- FF_239 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(239));
- FF_238 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(238));
- FF_237 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(237));
- FF_236 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(236));
- FF_235 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(235));
- FF_234 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(234));
- FF_233 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(233));
- FF_232 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(232));
- FF_231 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(231));
- FF_230 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(230));
- FF_229 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(229));
- FF_228 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(228));
- FF_227 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(227));
- FF_226 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(226));
- FF_225 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(225));
- FF_224 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(224));
- FF_223 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(223));
- FF_222 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(222));
- FF_221 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(221));
- FF_220 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(220));
- FF_219 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(219));
- FF_218 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(218));
- FF_217 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(217));
- FF_216 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(216));
- FF_215 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(215));
- FF_214 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(214));
- FF_213 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(213));
- FF_212 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(212));
- FF_211 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(211));
- FF_210 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(210));
- FF_209 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(209));
- FF_208 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(208));
- FF_207 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(207));
- FF_206 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(206));
- FF_205 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(205));
- FF_204 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(204));
- FF_203 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(203));
- FF_202 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(202));
- FF_201 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(201));
- FF_200 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(200));
- FF_199 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(199));
- FF_198 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(198));
- FF_197 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(197));
- FF_196 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(196));
- FF_195 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(195));
- FF_194 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(194));
- FF_193 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(193));
- FF_192 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(192));
- FF_191 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(191));
- FF_190 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(190));
- FF_189 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(189));
- FF_188 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(188));
- FF_187 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(187));
- FF_186 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(186));
- FF_185 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(185));
- FF_184 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(184));
- FF_183 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(183));
- FF_182 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(182));
- FF_181 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(181));
- FF_180 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(180));
- FF_179 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(179));
- FF_178 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(178));
- FF_177 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(177));
- FF_176 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(176));
- FF_175 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(175));
- FF_174 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(174));
- FF_173 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(173));
- FF_172 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(172));
- FF_171 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(171));
- FF_170 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(170));
- FF_169 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(169));
- FF_168 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(168));
- FF_167 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(167));
- FF_166 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(166));
- FF_165 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(165));
- FF_164 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(164));
- FF_163 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(163));
- FF_162 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(162));
- FF_161 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(161));
- FF_160 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(160));
- FF_159 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(159));
- FF_158 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(158));
- FF_157 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(157));
- FF_156 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(156));
- FF_155 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(155));
- FF_154 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(154));
- FF_153 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(153));
- FF_152 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(152));
- FF_151 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(151));
- FF_150 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(150));
- FF_149 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(149));
- FF_148 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(148));
- FF_147 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(147));
- FF_146 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(146));
- FF_145 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(145));
- FF_144 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(144));
- FF_143 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(143));
- FF_142 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(142));
- FF_141 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(141));
- FF_140 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(140));
- FF_139 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(139));
- FF_138 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(138));
- FF_137 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(137));
- FF_136 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(136));
- FF_135 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(135));
- FF_134 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(134));
- FF_133 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(133));
- FF_132 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(132));
- FF_131 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(131));
- FF_130 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(130));
- FF_129 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(129));
- FF_128 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(128));
- FF_127 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(127));
- FF_126 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(126));
- FF_125 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(125));
- FF_124 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(124));
- FF_123 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(123));
- FF_122 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(122));
- FF_121 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(121));
- FF_120 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(120));
- FF_119 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(119));
- FF_118 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(118));
- FF_117 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(117));
- FF_116 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(116));
- FF_115 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(115));
- FF_114 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(114));
- FF_113 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(113));
- FF_112 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(112));
- FF_111 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(111));
- FF_110 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(110));
- FF_109 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(109));
- FF_108 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(108));
- FF_107 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(107));
- FF_106 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(106));
- FF_105 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(105));
- FF_104 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(104));
- FF_103 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(103));
- FF_102 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(102));
- FF_101 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(101));
- FF_100 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(100));
- FF_99 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(99));
- FF_98 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(98));
- FF_97 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(97));
- FF_96 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(96));
- FF_95 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(95));
- FF_94 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(94));
- FF_93 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(93));
- FF_92 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(92));
- FF_91 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(91));
- FF_90 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(90));
- FF_89 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(89));
- FF_88 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(88));
- FF_87 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(87));
- FF_86 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(86));
- FF_85 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(85));
- FF_84 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(84));
- FF_83 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(83));
- FF_82 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(82));
- FF_81 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(81));
- FF_80 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(80));
- FF_79 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(79));
- FF_78 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(78));
- FF_77 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(77));
- FF_76 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(76));
- FF_75 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(75));
- FF_74 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(74));
- FF_73 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(73));
- FF_72 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(72));
- FF_71 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(71));
- FF_70 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(70));
- FF_69 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(69));
- FF_68 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(68));
- FF_67 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(67));
- FF_66 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(66));
- FF_65 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(65));
- FF_64 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(64));
- FF_63 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(63));
- FF_62 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(62));
- FF_61 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(61));
- FF_60 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(60));
- FF_59 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(59));
- FF_58 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(58));
- FF_57 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(57));
- FF_56 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(56));
- FF_55 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(55));
- FF_54 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(54));
- FF_53 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(53));
- FF_52 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(52));
- FF_51 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(51));
- FF_50 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(50));
- FF_49 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(49));
- FF_48 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(48));
- FF_47 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(47));
- FF_46 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(46));
- FF_45 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(45));
- FF_44 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(44));
- FF_43 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(43));
- FF_42 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(42));
- FF_41 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(41));
- FF_40 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(40));
- FF_39 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(39));
- FF_38 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(38));
- FF_37 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(37));
- FF_36 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(36));
- FF_35 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(35));
- FF_34 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(34));
- FF_33 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(33));
- FF_32 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(32));
- FF_31 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(31));
- FF_30 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(30));
- FF_29 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(29));
- FF_28 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(28));
- FF_27 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(27));
- FF_26 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(26));
- FF_25 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(25));
- FF_24 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(24));
- FF_23 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(23));
- FF_22 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(22));
- FF_21 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(21));
- FF_20 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(20));
- FF_19 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(19));
- FF_18 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(18));
- FF_17 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(17));
- FF_16 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(16));
- FF_15 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(15));
- FF_14 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(14));
- FF_13 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(13));
- FF_12 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(12));
- FF_11 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(11));
- FF_10 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(10));
- FF_9 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(9));
- FF_8 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(8));
- FF_7 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(7));
- FF_6 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(6));
- FF_5 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(5));
- FF_4 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(4));
- FF_3 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(3));
- FF_2 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(2));
- FF_1 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(1));
- FF_0 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(0));
-
- GEN_0_ADD : FADD2B
- port map (A0 => DataA(0),
- A1 => DataA(1),
- B0 => DataB(0),
- B1 => DataB(1),
- CI => scuba_vlo,
- COUT => co(0),
- S0 => tsum(0),
- S1 => tsum(1));
-
- GEN : for i in 1 to 143 generate
- ADD : FADD2B
- port map (A0 => DataA(2*i),
- A1 => DataA(2*i+1),
- B0 => DataB(2*i),
- B1 => DataB(2*i+1),
- CI => co(i-1),
- COUT => co(i),
- S0 => tsum(2*i),
- S1 => tsum(2*i+1));
- end generate GEN;
-
- scuba_vlo_inst : VLO
- port map (Z => scuba_vlo);
-
- Result <= r0_sum;
-
-end Structure;
-
-
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of Adder_288 is
- for Structure
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-
-entity Adder_320 is
- port (CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(319 downto 0);
- DataB : in std_logic_vector(319 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(319 downto 0)
- );
-end Adder_320;
-
-architecture Structure of Adder_320 is
-
--- internal signal declarations
- signal r0_sum : std_logic_vector(319 downto 0);
- signal tsum : std_logic_vector(319 downto 0);
- signal co : std_logic_vector(159 downto 0);
- signal scuba_vlo : std_logic;
-
--- local component declarations
- component FADD2B
- port (A0 : in std_logic;
- A1 : in std_logic;
- B0 : in std_logic;
- B1 : in std_logic;
- CI : in std_logic;
- COUT : out std_logic;
- S0 : out std_logic;
- S1 : out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D : in std_logic;
- SP : in std_logic;
- CK : in std_logic;
- CD : in std_logic;
- Q : out std_logic);
- end component;
- component VLO
- port (Z : out std_logic);
- end component;
-
- attribute GSR : string;
- attribute GSR of FF_319 : label is "ENABLED";
- attribute GSR of FF_318 : label is "ENABLED";
- attribute GSR of FF_317 : label is "ENABLED";
- attribute GSR of FF_316 : label is "ENABLED";
- attribute GSR of FF_315 : label is "ENABLED";
- attribute GSR of FF_314 : label is "ENABLED";
- attribute GSR of FF_313 : label is "ENABLED";
- attribute GSR of FF_312 : label is "ENABLED";
- attribute GSR of FF_311 : label is "ENABLED";
- attribute GSR of FF_310 : label is "ENABLED";
- attribute GSR of FF_309 : label is "ENABLED";
- attribute GSR of FF_308 : label is "ENABLED";
- attribute GSR of FF_307 : label is "ENABLED";
- attribute GSR of FF_306 : label is "ENABLED";
- attribute GSR of FF_305 : label is "ENABLED";
- attribute GSR of FF_304 : label is "ENABLED";
- attribute GSR of FF_303 : label is "ENABLED";
- attribute GSR of FF_302 : label is "ENABLED";
- attribute GSR of FF_301 : label is "ENABLED";
- attribute GSR of FF_300 : label is "ENABLED";
- attribute GSR of FF_299 : label is "ENABLED";
- attribute GSR of FF_298 : label is "ENABLED";
- attribute GSR of FF_297 : label is "ENABLED";
- attribute GSR of FF_296 : label is "ENABLED";
- attribute GSR of FF_295 : label is "ENABLED";
- attribute GSR of FF_294 : label is "ENABLED";
- attribute GSR of FF_293 : label is "ENABLED";
- attribute GSR of FF_292 : label is "ENABLED";
- attribute GSR of FF_291 : label is "ENABLED";
- attribute GSR of FF_290 : label is "ENABLED";
- attribute GSR of FF_289 : label is "ENABLED";
- attribute GSR of FF_288 : label is "ENABLED";
- attribute GSR of FF_287 : label is "ENABLED";
- attribute GSR of FF_286 : label is "ENABLED";
- attribute GSR of FF_285 : label is "ENABLED";
- attribute GSR of FF_284 : label is "ENABLED";
- attribute GSR of FF_283 : label is "ENABLED";
- attribute GSR of FF_282 : label is "ENABLED";
- attribute GSR of FF_281 : label is "ENABLED";
- attribute GSR of FF_280 : label is "ENABLED";
- attribute GSR of FF_279 : label is "ENABLED";
- attribute GSR of FF_278 : label is "ENABLED";
- attribute GSR of FF_277 : label is "ENABLED";
- attribute GSR of FF_276 : label is "ENABLED";
- attribute GSR of FF_275 : label is "ENABLED";
- attribute GSR of FF_274 : label is "ENABLED";
- attribute GSR of FF_273 : label is "ENABLED";
- attribute GSR of FF_272 : label is "ENABLED";
- attribute GSR of FF_271 : label is "ENABLED";
- attribute GSR of FF_270 : label is "ENABLED";
- attribute GSR of FF_269 : label is "ENABLED";
- attribute GSR of FF_268 : label is "ENABLED";
- attribute GSR of FF_267 : label is "ENABLED";
- attribute GSR of FF_266 : label is "ENABLED";
- attribute GSR of FF_265 : label is "ENABLED";
- attribute GSR of FF_264 : label is "ENABLED";
- attribute GSR of FF_263 : label is "ENABLED";
- attribute GSR of FF_262 : label is "ENABLED";
- attribute GSR of FF_261 : label is "ENABLED";
- attribute GSR of FF_260 : label is "ENABLED";
- attribute GSR of FF_259 : label is "ENABLED";
- attribute GSR of FF_258 : label is "ENABLED";
- attribute GSR of FF_257 : label is "ENABLED";
- attribute GSR of FF_256 : label is "ENABLED";
- attribute GSR of FF_255 : label is "ENABLED";
- attribute GSR of FF_254 : label is "ENABLED";
- attribute GSR of FF_253 : label is "ENABLED";
- attribute GSR of FF_252 : label is "ENABLED";
- attribute GSR of FF_251 : label is "ENABLED";
- attribute GSR of FF_250 : label is "ENABLED";
- attribute GSR of FF_249 : label is "ENABLED";
- attribute GSR of FF_248 : label is "ENABLED";
- attribute GSR of FF_247 : label is "ENABLED";
- attribute GSR of FF_246 : label is "ENABLED";
- attribute GSR of FF_245 : label is "ENABLED";
- attribute GSR of FF_244 : label is "ENABLED";
- attribute GSR of FF_243 : label is "ENABLED";
- attribute GSR of FF_242 : label is "ENABLED";
- attribute GSR of FF_241 : label is "ENABLED";
- attribute GSR of FF_240 : label is "ENABLED";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- FF_319 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(319), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(319));
- FF_318 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(318), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(318));
- FF_317 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(317), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(317));
- FF_316 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(316), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(316));
- FF_315 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(315), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(315));
- FF_314 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(314), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(314));
- FF_313 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(313), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(313));
- FF_312 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(312), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(312));
- FF_311 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(311), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(311));
- FF_310 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(310), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(310));
- FF_309 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(309), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(309));
- FF_308 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(308), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(308));
- FF_307 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(307), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(307));
- FF_306 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(306), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(306));
- FF_305 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(305), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(305));
- FF_304 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(304), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(304));
- FF_303 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(303), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(303));
- FF_302 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(302), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(302));
- FF_301 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(301), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(301));
- FF_300 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(300), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(300));
- FF_299 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(299), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(299));
- FF_298 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(298), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(298));
- FF_297 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(297), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(297));
- FF_296 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(296), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(296));
- FF_295 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(295), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(295));
- FF_294 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(294), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(294));
- FF_293 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(293), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(293));
- FF_292 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(292), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(292));
- FF_291 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(291), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(291));
- FF_290 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(290), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(290));
- FF_289 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(289), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(289));
- FF_288 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(288), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(288));
- -- component instantiation statements
- FF_287 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(287));
- FF_286 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(286));
- FF_285 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(285));
- FF_284 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(284));
- FF_283 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(283));
- FF_282 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(282));
- FF_281 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(281));
- FF_280 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(280));
- FF_279 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(279));
- FF_278 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(278));
- FF_277 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(277));
- FF_276 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(276));
- FF_275 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(275));
- FF_274 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(274));
- FF_273 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(273));
- FF_272 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(272));
- FF_271 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(271));
- FF_270 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(270));
- FF_269 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(269));
- FF_268 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(268));
- FF_267 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(267));
- FF_266 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(266));
- FF_265 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(265));
- FF_264 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(264));
- FF_263 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(263));
- FF_262 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(262));
- FF_261 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(261));
- FF_260 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(260));
- FF_259 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(259));
- FF_258 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(258));
- FF_257 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(257));
- FF_256 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(256));
- FF_255 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(255));
- FF_254 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(254));
- FF_253 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(253));
- FF_252 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(252));
- FF_251 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(251));
- FF_250 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(250));
- FF_249 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(249));
- FF_248 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(248));
- FF_247 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(247));
- FF_246 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(246));
- FF_245 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(245));
- FF_244 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(244));
- FF_243 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(243));
- FF_242 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(242));
- FF_241 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(241));
- FF_240 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(240));
- FF_239 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(239));
- FF_238 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(238));
- FF_237 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(237));
- FF_236 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(236));
- FF_235 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(235));
- FF_234 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(234));
- FF_233 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(233));
- FF_232 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(232));
- FF_231 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(231));
- FF_230 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(230));
- FF_229 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(229));
- FF_228 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(228));
- FF_227 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(227));
- FF_226 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(226));
- FF_225 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(225));
- FF_224 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(224));
- FF_223 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(223));
- FF_222 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(222));
- FF_221 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(221));
- FF_220 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(220));
- FF_219 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(219));
- FF_218 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(218));
- FF_217 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(217));
- FF_216 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(216));
- FF_215 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(215));
- FF_214 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(214));
- FF_213 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(213));
- FF_212 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(212));
- FF_211 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(211));
- FF_210 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(210));
- FF_209 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(209));
- FF_208 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(208));
- FF_207 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(207));
- FF_206 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(206));
- FF_205 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(205));
- FF_204 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(204));
- FF_203 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(203));
- FF_202 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(202));
- FF_201 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(201));
- FF_200 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(200));
- FF_199 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(199));
- FF_198 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(198));
- FF_197 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(197));
- FF_196 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(196));
- FF_195 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(195));
- FF_194 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(194));
- FF_193 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(193));
- FF_192 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(192));
- FF_191 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(191));
- FF_190 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(190));
- FF_189 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(189));
- FF_188 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(188));
- FF_187 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(187));
- FF_186 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(186));
- FF_185 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(185));
- FF_184 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(184));
- FF_183 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(183));
- FF_182 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(182));
- FF_181 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(181));
- FF_180 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(180));
- FF_179 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(179));
- FF_178 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(178));
- FF_177 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(177));
- FF_176 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(176));
- FF_175 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(175));
- FF_174 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(174));
- FF_173 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(173));
- FF_172 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(172));
- FF_171 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(171));
- FF_170 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(170));
- FF_169 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(169));
- FF_168 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(168));
- FF_167 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(167));
- FF_166 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(166));
- FF_165 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(165));
- FF_164 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(164));
- FF_163 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(163));
- FF_162 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(162));
- FF_161 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(161));
- FF_160 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(160));
- FF_159 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(159));
- FF_158 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(158));
- FF_157 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(157));
- FF_156 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(156));
- FF_155 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(155));
- FF_154 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(154));
- FF_153 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(153));
- FF_152 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(152));
- FF_151 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(151));
- FF_150 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(150));
- FF_149 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(149));
- FF_148 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(148));
- FF_147 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(147));
- FF_146 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(146));
- FF_145 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(145));
- FF_144 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(144));
- FF_143 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(143));
- FF_142 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(142));
- FF_141 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(141));
- FF_140 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(140));
- FF_139 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(139));
- FF_138 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(138));
- FF_137 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(137));
- FF_136 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(136));
- FF_135 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(135));
- FF_134 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(134));
- FF_133 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(133));
- FF_132 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(132));
- FF_131 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(131));
- FF_130 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(130));
- FF_129 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(129));
- FF_128 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(128));
- FF_127 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(127));
- FF_126 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(126));
- FF_125 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(125));
- FF_124 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(124));
- FF_123 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(123));
- FF_122 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(122));
- FF_121 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(121));
- FF_120 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(120));
- FF_119 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(119));
- FF_118 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(118));
- FF_117 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(117));
- FF_116 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(116));
- FF_115 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(115));
- FF_114 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(114));
- FF_113 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(113));
- FF_112 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(112));
- FF_111 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(111));
- FF_110 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(110));
- FF_109 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(109));
- FF_108 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(108));
- FF_107 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(107));
- FF_106 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(106));
- FF_105 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(105));
- FF_104 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(104));
- FF_103 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(103));
- FF_102 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(102));
- FF_101 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(101));
- FF_100 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(100));
- FF_99 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(99));
- FF_98 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(98));
- FF_97 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(97));
- FF_96 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(96));
- FF_95 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(95));
- FF_94 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(94));
- FF_93 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(93));
- FF_92 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(92));
- FF_91 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(91));
- FF_90 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(90));
- FF_89 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(89));
- FF_88 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(88));
- FF_87 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(87));
- FF_86 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(86));
- FF_85 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(85));
- FF_84 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(84));
- FF_83 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(83));
- FF_82 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(82));
- FF_81 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(81));
- FF_80 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(80));
- FF_79 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(79));
- FF_78 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(78));
- FF_77 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(77));
- FF_76 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(76));
- FF_75 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(75));
- FF_74 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(74));
- FF_73 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(73));
- FF_72 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(72));
- FF_71 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(71));
- FF_70 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(70));
- FF_69 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(69));
- FF_68 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(68));
- FF_67 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(67));
- FF_66 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(66));
- FF_65 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(65));
- FF_64 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(64));
- FF_63 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(63));
- FF_62 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(62));
- FF_61 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(61));
- FF_60 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(60));
- FF_59 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(59));
- FF_58 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(58));
- FF_57 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(57));
- FF_56 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(56));
- FF_55 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(55));
- FF_54 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(54));
- FF_53 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(53));
- FF_52 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(52));
- FF_51 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(51));
- FF_50 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(50));
- FF_49 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(49));
- FF_48 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(48));
- FF_47 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(47));
- FF_46 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(46));
- FF_45 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(45));
- FF_44 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(44));
- FF_43 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(43));
- FF_42 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(42));
- FF_41 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(41));
- FF_40 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(40));
- FF_39 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(39));
- FF_38 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(38));
- FF_37 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(37));
- FF_36 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(36));
- FF_35 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(35));
- FF_34 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(34));
- FF_33 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(33));
- FF_32 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(32));
- FF_31 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(31));
- FF_30 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(30));
- FF_29 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(29));
- FF_28 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(28));
- FF_27 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(27));
- FF_26 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(26));
- FF_25 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(25));
- FF_24 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(24));
- FF_23 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(23));
- FF_22 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(22));
- FF_21 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(21));
- FF_20 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(20));
- FF_19 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(19));
- FF_18 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(18));
- FF_17 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(17));
- FF_16 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(16));
- FF_15 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(15));
- FF_14 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(14));
- FF_13 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(13));
- FF_12 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(12));
- FF_11 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(11));
- FF_10 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(10));
- FF_9 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(9));
- FF_8 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(8));
- FF_7 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(7));
- FF_6 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(6));
- FF_5 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(5));
- FF_4 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(4));
- FF_3 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(3));
- FF_2 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(2));
- FF_1 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(1));
- FF_0 : FD1P3DX
- -- synopsys translate_off
- generic map (GSR => "ENABLED")
- -- synopsys translate_on
- port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(0));
-
- GEN_0_ADD : FADD2B
- port map (A0 => DataA(0),
- A1 => DataA(1),
- B0 => DataB(0),
- B1 => DataB(1),
- CI => scuba_vlo,
- COUT => co(0),
- S0 => tsum(0),
- S1 => tsum(1));
-
- GEN : for i in 1 to 159 generate
- ADD : FADD2B
- port map (A0 => DataA(2*i),
- A1 => DataA(2*i+1),
- B0 => DataB(2*i),
- B1 => DataB(2*i+1),
- CI => co(i-1),
- COUT => co(i),
- S0 => tsum(2*i),
- S1 => tsum(2*i+1));
- end generate GEN;
-
- scuba_vlo_inst : VLO
- port map (Z => scuba_vlo);
-
- Result <= r0_sum;
-
-end Structure;
-
-
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of Adder_320 is
- for Structure
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_arith.all;
-
-library synplify;
-use synplify.attributes.all;
-
-entity Channel is
-
- generic (
- CHANNEL_ID : integer range 0 to 15);
- port (
- RESET : in std_logic;
- CLK : in std_logic;
---
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(15 downto 0)
---
--- Channel_DEBUG_01 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_02 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_03 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_04 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_05 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_06 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_07 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_08 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_09 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_10 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_11 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_12 : out std_logic_vector(31 downto 0)
- );
-
-end Channel;
-
-architecture Channel of Channel is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Adder_288
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(287 downto 0);
- DataB : in std_logic_vector(287 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(287 downto 0));
- end component;
---
- component Encoder_288_Bit
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_INPUT : in std_logic;
- THERMO_CODE_INPUT : in std_logic_vector(287 downto 0);
- FINISHED_OUTPUT : out std_logic;
- BINARY_CODE_OUTPUT : out std_logic_vector(9 downto 0));
- end component;
---
- component FIFO_32x512_Oreg
- port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
---
- component ORCALUT4
- generic(
- INIT : bit_vector);
- port (
- A, B, C, D : in std_logic;
- Z : out std_logic);
- end component;
-
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
-
- signal clk_i : std_logic;
- signal rst_i : std_logic;
- signal data_a_i : std_logic_vector(287 downto 0);
- signal data_b_i : std_logic_vector(287 downto 0);
- signal result_i : std_logic_vector(287 downto 0);
- signal result_reg : std_logic_vector(287 downto 0);
- signal thermo_code_i : std_logic_vector(287 downto 0);
- signal hit_in_i : std_logic;
- signal hit_detect_i : std_logic;
- signal result_2_reg : std_logic;
- signal coarse_cntr_i : std_logic_vector(15 downto 0);
- signal hit_time_stamp_i : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg2 : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg3 : std_logic_vector(15 downto 0);
- signal fine_counter_i : std_logic_vector(9 downto 0);
- signal encoder_start_i : std_logic;
- signal fifo_data_out_i : std_logic_vector(31 downto 0);
- signal fifo_data_in_i : std_logic_vector(31 downto 0);
- signal fifo_empty_i : std_logic;
- signal fifo_full_i : std_logic;
- signal fifo_wr_en_i : std_logic;
- signal fifo_rd_en_i : std_logic;
-
--------------------------------------------------------------------------------
-
-begin
-
- clk_i <= CLK;
- rst_i <= RESET;
- fifo_rd_en_i <= READ_EN_IN;
- coarse_cntr_i <= COARSE_COUNTER_IN;
-
--- -- purpose: Generates a pulse out of the hit signal on order to prevent second transition in the hit signal
--- Hit_Trigger : process (HIT_IN, hit_trig_reset_i, rst_i)
--- begin
--- if rst_i = '1' or hit_trig_reset_i = '1' then
--- hit_in_i <= '0';
--- elsif rising_edge(HIT_IN) then
--- hit_in_i <= '1';
--- end if;
--- end process Hit_Trigger;
-
- hit_in_i <= HIT_IN;
-
--- --purpose: Tapped Delay Line 288 (Carry Chain) with wave launcher (21)
--- FC : Adder_288
--- port map (
--- CLK => clk_i,
--- RESET => rst_i,
--- DataA => data_a_i,
--- DataB => data_b_i,
--- ClkEn => '1',
--- Result => result_i);
--- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFF";
--- data_b_i <= x"0000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"0000" & "00" & hit_buf;
-
- -- purpose: Tapped Delay Line 288 (Carry Chain)
- FC : Adder_288
- port map (
- CLK => clk_i,
- RESET => rst_i,
- DataA => data_a_i,
- DataB => data_b_i,
- ClkEn => '1',
- Result => result_i);
- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- data_b_i <= x"00000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Registers the hit detection bit
- Hit_Register : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- result_2_reg <= '0';
- else
- result_2_reg <= result_i(2);
- end if;
- end if;
- end process Hit_Register;
-
- --purpose: Detects the hit
- Hit_Detect : process (result_2_reg, result_i)
- begin
- hit_detect_i <= (not result_2_reg) and result_i(2);
- end process Hit_Detect;
-
- --purpose: Double Synchroniser
- Double_Syncroniser : process (clk_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- result_reg <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- elsif hit_detect_i = '1' then --or hit_trig_reset_i = '1' then
- result_reg <= result_i;
- end if;
- end if;
- end process Double_Syncroniser;
-
--- Channel_DEBUG_01(0) <= result_reg(287);
-
- --purpose: Start Encoder and captures the time stamp of the hit
- Start_Encoder : process (clk_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- encoder_start_i <= '0';
- hit_time_stamp_i <= (others => '0');
- hit_time_stamp_reg <= (others => '0');
- hit_time_stamp_reg2 <= (others => '0');
- hit_time_stamp_reg3 <= (others => '0');
- elsif hit_detect_i = '1' then
- encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-1;
- else
- encoder_start_i <= '0';
- hit_time_stamp_reg <= hit_time_stamp_i;
- hit_time_stamp_reg2 <= hit_time_stamp_reg;
- hit_time_stamp_reg3 <= hit_time_stamp_reg2;
- end if;
- end if;
- end process Start_Encoder;
-
- --purpose: Encoder
- Encoder : Encoder_288_Bit
- port map (
- RESET => rst_i,
- CLK => clk_i,
- START_INPUT => encoder_start_i,
- THERMO_CODE_INPUT => result_reg,
- FINISHED_OUTPUT => fifo_wr_en_i,
- BINARY_CODE_OUTPUT => fine_counter_i);
-
- thermo_code_i <= "11" & result_reg(287 downto 2);
--- hit_trig_reset_i <= fifo_wr_en_i;
-
- FIFO : FIFO_32x512_Oreg
- port map (
- Data => fifo_data_in_i,
- WrClock => clk_i,
- RdClock => clk_i,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
- Reset => rst_i,
- RPReset => rst_i,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i);
- fifo_data_in_i(31 downto 26) <= conv_std_logic_vector(CHANNEL_ID, 6);
- fifo_data_in_i(25 downto 10) <= hit_time_stamp_reg3; --hit_time_stamp_i;
- fifo_data_in_i(9 downto 0) <= fine_counter_i;
-
- Register_Outputs : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- end if;
- end if;
- end process Register_Outputs;
-
-
-
--- GEN_TDL_FIFOS : for i in 0 to FIFO_NR-1 generate
--- --purpose: TEST FIFO
--- FIFO : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(i),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => encoder_start_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(i),
--- Empty => open,
--- Full => open);
--- data_in(i) <= result_reg(32*(i+1)-1 downto i*32);
--- end generate GEN_TDL_FIFOS;
-
--- --purpose: TEST FIFO
--- FIFO_36 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(9),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => encoder_start_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(9),
--- Empty => open,
--- Full => open);
-----
--- --purpose: TEST FIFO
--- FIFO_37 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(10),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => wr_en_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(10),
--- Empty => open,
--- Full => open);
-----
--- --purpose: TEST FIFO
--- FIFO_38 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(11),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => wr_en_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(11),
--- Empty => open,
--- Full => open);
---
-
- --data_in(9) <= x"deadface";
- --data_in(10) <= "00" & x"00000" & fine_counter_i(9 downto 0);
- --data_in(11) <= x"facedead";
-
- --Channel_DEBUG_01 <= data_out(0);
- --Channel_DEBUG_02 <= data_out(1);
- --Channel_DEBUG_03 <= data_out(2);
- --Channel_DEBUG_04 <= data_out(3);
- --Channel_DEBUG_05 <= data_out(4);
- --Channel_DEBUG_06 <= data_out(5);
- --Channel_DEBUG_07 <= data_out(6);
- --Channel_DEBUG_08 <= data_out(7);
- --Channel_DEBUG_09 <= data_out(8);
- --Channel_DEBUG_10 <= data_out(9);
- --Channel_DEBUG_11 <= data_out(10);
- --Channel_DEBUG_12 <= data_out(11);
-
-
-end Channel;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_arith.all;
-
-library synplify;
-use synplify.attributes.all;
-
-entity Channel is
-
- generic (
- CHANNEL_ID : integer range 0 to 15);
- port (
- RESET : in std_logic;
- CLK : in std_logic;
---
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(15 downto 0)
---
--- Channel_DEBUG_01 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_02 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_03 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_04 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_05 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_06 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_07 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_08 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_09 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_10 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_11 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_12 : out std_logic_vector(31 downto 0)
- );
-
-end Channel;
-
-architecture Channel of Channel is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Adder_320
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(319 downto 0);
- DataB : in std_logic_vector(319 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(319 downto 0));
- end component;
-
--- component Adder_288
--- port (
--- CLK : in std_logic;
--- RESET : in std_logic;
--- DataA : in std_logic_vector(287 downto 0);
--- DataB : in std_logic_vector(287 downto 0);
--- ClkEn : in std_logic;
--- Result : out std_logic_vector(287 downto 0));
--- end component;
---
- component Encoder_320_Bit
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_INPUT : in std_logic;
- THERMO_CODE_INPUT : in std_logic_vector(319 downto 0);
- FINISHED_OUTPUT : out std_logic;
- BINARY_CODE_OUTPUT : out std_logic_vector(9 downto 0));
- end component;
-
--- component Encoder_288_Bit
--- port (
--- RESET : in std_logic;
--- CLK : in std_logic;
--- START_INPUT : in std_logic;
--- THERMO_CODE_INPUT : in std_logic_vector(287 downto 0);
--- FINISHED_OUTPUT : out std_logic;
--- BINARY_CODE_OUTPUT : out std_logic_vector(9 downto 0));
--- end component;
---
- component FIFO_32x512_NOreg
- port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
---
- component ORCALUT4
- generic(
- INIT : bit_vector);
- port (
- A, B, C, D : in std_logic;
- Z : out std_logic);
- end component;
-
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
-
- signal clk_i : std_logic;
- signal rst_i : std_logic;
- signal data_a_i : std_logic_vector(319 downto 0);
- signal data_b_i : std_logic_vector(319 downto 0);
- signal result_i : std_logic_vector(319 downto 0);
- signal result_reg : std_logic_vector(319 downto 0);
- signal thermo_code_i : std_logic_vector(319 downto 0);
- signal hit_in_i : std_logic;
- signal hit_detect_i : std_logic;
- signal result_2_reg : std_logic;
- signal coarse_cntr_i : std_logic_vector(15 downto 0);
- signal hit_time_stamp_i : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg2 : std_logic_vector(15 downto 0);
- signal hit_time_stamp_reg3 : std_logic_vector(15 downto 0);
- signal fine_counter_i : std_logic_vector(9 downto 0);
- signal encoder_start_i : std_logic;
- signal fifo_data_out_i : std_logic_vector(31 downto 0);
- signal fifo_data_in_i : std_logic_vector(31 downto 0);
- signal fifo_empty_i : std_logic;
- signal fifo_full_i : std_logic;
- signal fifo_wr_en_i : std_logic;
- signal fifo_rd_en_i : std_logic;
-
- signal hit_buf : std_logic;
- attribute syn_keep of hit_buf : signal is true;
- attribute syn_keep of hit_in_i : signal is true;
- attribute NOMERGE : string;
- attribute NOMERGE of hit_buf : signal is "true";
-
--------------------------------------------------------------------------------
-
-begin
-
- clk_i <= CLK;
- rst_i <= RESET;
- fifo_rd_en_i <= READ_EN_IN;
- coarse_cntr_i <= COARSE_COUNTER_IN;
-
--- -- purpose: Generates a pulse out of the hit signal on order to prevent second transition in the hit signal
--- Hit_Trigger : process (HIT_IN, hit_trig_reset_i, rst_i)
--- begin
--- if rst_i = '1' or hit_trig_reset_i = '1' then
--- hit_in_i <= '0';
--- elsif rising_edge(HIT_IN) then
--- hit_in_i <= '1';
--- end if;
--- end process Hit_Trigger;
-
- hit_in_i <= HIT_IN;
- hit_buf <= not hit_in_i;
-
- --purpose: Tapped Delay Line 320 (Carry Chain) with wave launcher (21)
- FC : Adder_320
- port map (
- CLK => clk_i,
- RESET => rst_i,
- DataA => data_a_i,
- DataB => data_b_i,
- ClkEn => '1',
- Result => result_i);
- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFF";
- data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"0000" & "00" & hit_buf;
-
--- --purpose: Tapped Delay Line 288 (Carry Chain) with wave launcher (21)
--- FC : Adder_288
--- port map (
--- CLK => clk_i,
--- RESET => rst_i,
--- DataA => data_a_i,
--- DataB => data_b_i,
--- ClkEn => '1',
--- Result => result_i);
--- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFF";
--- data_b_i <= x"0000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"0000" & "00" & hit_buf;
-
- --purpose: Tapped Delay Line 288 (Carry Chain)
--- FC : Adder_288
--- port map (
--- CLK => clk_i,
--- RESET => rst_i,
--- DataA => data_a_i,
--- DataB => data_b_i,
--- ClkEn => '1',
--- Result => result_i);
--- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
--- data_b_i <= x"00000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Registers the hit detection bit
- Hit_Register : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- result_2_reg <= '0';
- else
- result_2_reg <= result_i(2);
- end if;
- end if;
- end process Hit_Register;
-
- --purpose: Detects the hit
- Hit_Detect : process (result_2_reg, result_i)
- begin
- hit_detect_i <= (not result_2_reg) and result_i(2);
- end process Hit_Detect;
-
- --purpose: Double Synchroniser
- Double_Syncroniser : process (clk_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- result_reg <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- elsif hit_detect_i = '1' then --or hit_trig_reset_i = '1' then
- result_reg <= result_i;
- end if;
- end if;
- end process Double_Syncroniser;
-
--- Channel_DEBUG_01(0) <= result_reg(319);
-
- --purpose: Start Encoder and captures the time stamp of the hit
- Start_Encoder : process (clk_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- encoder_start_i <= '0';
- hit_time_stamp_i <= (others => '0');
- hit_time_stamp_reg <= (others => '0');
- hit_time_stamp_reg2 <= (others => '0');
- hit_time_stamp_reg3 <= (others => '0');
- elsif hit_detect_i = '1' then
- encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-1;
- else
- encoder_start_i <= '0';
- hit_time_stamp_reg <= hit_time_stamp_i;
- hit_time_stamp_reg2 <= hit_time_stamp_reg;
- hit_time_stamp_reg3 <= hit_time_stamp_reg2;
- end if;
- end if;
- end process Start_Encoder;
-
- --purpose: Encoder
- Encoder : Encoder_320_Bit
- port map (
- RESET => rst_i,
- CLK => clk_i,
- START_INPUT => encoder_start_i,
- THERMO_CODE_INPUT => result_reg,
- FINISHED_OUTPUT => fifo_wr_en_i,
- BINARY_CODE_OUTPUT => fine_counter_i);
-
--- --purpose: Encoder
--- Encoder : Encoder_288_Bit
--- port map (
--- RESET => rst_i,
--- CLK => clk_i,
--- START_INPUT => encoder_start_i,
--- THERMO_CODE_INPUT => result_reg,
--- FINISHED_OUTPUT => fifo_wr_en_i,
--- BINARY_CODE_OUTPUT => fine_counter_i);
-
- thermo_code_i <= "11" & result_reg(319 downto 2);
--- hit_trig_reset_i <= fifo_wr_en_i;
-
- THE_FIFO : FIFO_32x512_NOreg
- port map (
- Data => fifo_data_in_i,
- WrClock => clk_i,
- RdClock => clk_i,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
- Reset => rst_i,
- RPReset => rst_i,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i);
- fifo_data_in_i(31 downto 26) <= conv_std_logic_vector(CHANNEL_ID, 6);
- fifo_data_in_i(25 downto 10) <= hit_time_stamp_reg3; --hit_time_stamp_i;
- fifo_data_in_i(9 downto 0) <= fine_counter_i;
-
- Register_Outputs : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- end if;
- end if;
- end process Register_Outputs;
-
-
-
--- GEN_TDL_FIFOS : for i in 0 to FIFO_NR-1 generate
--- --purpose: TEST FIFO
--- FIFO : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(i),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => encoder_start_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(i),
--- Empty => open,
--- Full => open);
--- data_in(i) <= result_reg(32*(i+1)-1 downto i*32);
--- end generate GEN_TDL_FIFOS;
-
--- --purpose: TEST FIFO
--- FIFO_36 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(9),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => encoder_start_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(9),
--- Empty => open,
--- Full => open);
-----
--- --purpose: TEST FIFO
--- FIFO_37 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(10),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => wr_en_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(10),
--- Empty => open,
--- Full => open);
-----
--- --purpose: TEST FIFO
--- FIFO_38 : FIFO_DC_32_512 --FIFO_DC_34_512
--- port map (
--- Data => data_in(11),
--- WrClock => clk_i,
--- RdClock => clk_i,
--- WrEn => wr_en_i,
--- RdEn => fifo_rd_en_i,
--- Reset => rst_i,
--- RPReset => rst_i,
--- Q => data_out(11),
--- Empty => open,
--- Full => open);
---
-
- --data_in(9) <= x"deadface";
- --data_in(10) <= "00" & x"00000" & fine_counter_i(9 downto 0);
- --data_in(11) <= x"facedead";
-
- --Channel_DEBUG_01 <= data_out(0);
- --Channel_DEBUG_02 <= data_out(1);
- --Channel_DEBUG_03 <= data_out(2);
- --Channel_DEBUG_04 <= data_out(3);
- --Channel_DEBUG_05 <= data_out(4);
- --Channel_DEBUG_06 <= data_out(5);
- --Channel_DEBUG_07 <= data_out(6);
- --Channel_DEBUG_08 <= data_out(7);
- --Channel_DEBUG_09 <= data_out(8);
- --Channel_DEBUG_10 <= data_out(9);
- --Channel_DEBUG_11 <= data_out(10);
- --Channel_DEBUG_12 <= data_out(11);
-
-
-end Channel;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.all;
---use ieee.std_logic_arith.all;
---use ieee.numeric_std.all;
-
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity Encoder_288_Bit is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_INPUT : in std_logic;
- THERMO_CODE_INPUT : in std_logic_vector(287 downto 0);
- FINISHED_OUTPUT : out std_logic;
- BINARY_CODE_OUTPUT : out std_logic_vector(9 downto 0));
-end Encoder_288_Bit;
-
-architecture Encoder_288_Bit of Encoder_288_Bit is
-
- -- component definitions
- component up_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
- end component;
---
- component ORCALUT4
- generic(
- INIT : bit_vector);
- port (
- A, B, C, D : in std_logic;
- Z : out std_logic);
- end component;
-
- -- signal declerations
- signal clk_i : std_logic;
- signal rst_i : std_logic;
- signal start_input_i : std_logic;
- signal thermo_code_i : std_logic_vector(287 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- signal P_lut : std_logic_vector(17 downto 0);
- signal P_one : std_logic_vector(17 downto 0);
- signal mux_control : std_logic_vector(4 downto 0);
- signal interval_i : std_logic_vector(17 downto 0);
- signal interval_tmp : std_logic_vector(17 downto 0);
- signal interval_bc : std_logic_vector(14 downto 0);
- signal interval_bc_norm : std_logic_vector(14 downto 0);
- signal interval_bc_bbl : std_logic_vector(14 downto 0);
- signal interval_binary : std_logic_vector(3 downto 0);
- signal counter_reset_i : std_logic;
- signal counter_up_i : std_logic;
- signal counter_out_i : std_logic_vector(2 downto 0);
- signal binary_code_f : std_logic_vector(8 downto 0);
- signal binary_code_r : std_logic_vector(8 downto 0);
- signal edge_type_i : std_logic; -- 0 => 0-1 edge, 1 => 1-0 edge
-
-begin
-
- clk_i <= CLK;
- rst_i <= RESET;
- start_input_i <= START_INPUT;
- thermo_code_i <= THERMO_CODE_INPUT;
-
- --Component instantiations
-
- Process_Counter : up_counter
- generic map (
- NUMBER_OF_BITS => 3)
- port map (
- CLK => clk_i,
- RESET => counter_reset_i,
- COUNT_OUT => counter_out_i,
- UP_IN => counter_up_i);
-
- Interval_Determination_First : ORCALUT4
- generic map (INIT => X"A815")
- port map (A => '1', B => '1', C => thermo_code_i(0), D => edge_type_i,
- Z => P_lut(0));
---
- Interval_Determination : for i in 1 to 17 generate
- U : ORCALUT4
- generic map (INIT => X"A815")
- port map (A => thermo_code_i(16*i-2), B => thermo_code_i(16*i-1), C => thermo_code_i(16*i), D => edge_type_i,
- Z => P_lut(i));
- end generate Interval_Determination;
--------------------------------------------------------------------------------
-
- Change_Edge_Type : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' or counter_out_i = "111" then
- edge_type_i <= '0';
- elsif counter_out_i = "001" then
- edge_type_i <= '1';
- end if;
- end if;
- end process Change_Edge_Type;
- Gen_P_one : for i in 0 to 16 generate
- P_one(i) <= P_lut(i) and (not P_lut(i+1));
- end generate Gen_P_one;
-
- P_one_assign : process (edge_type_i, P_lut)
- begin
- if edge_type_i = '0' then
- P_one(17) <= P_lut(17);
- else
- P_one(17) <= '0';
- end if;
- end process P_one_assign;
-
- Interval_Number_to_Binary : process (clk_i, rst_i)
- begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary
- -- code for the control of the MUX.
- if rising_edge(clk_i) then
- if rst_i = '1' then
- mux_control <= (others => '0');
- else
- mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or
- P_one(12) or P_one(14) or P_one(16);
- mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or
- P_one(13) or P_one(14) or P_one(17);
- mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14);
- mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14);
- mux_control(4) <= P_one(15) or P_one(16) or P_one(17);
- end if;
- end if;
- end process Interval_Number_to_Binary;
-
- Interval_Selection : process (mux_control, thermo_code_i, edge_type_i)
- begin -- The interval with the 0-1 transition is selected.
- case mux_control is
- when "00001" => interval_tmp <= thermo_code_i(16 downto 0) & edge_type_i;
- when "00010" => interval_tmp <= thermo_code_i(32 downto 15);
- when "00011" => interval_tmp <= thermo_code_i(48 downto 31);
- when "00100" => interval_tmp <= thermo_code_i(64 downto 47);
- when "00101" => interval_tmp <= thermo_code_i(80 downto 63);
- when "00110" => interval_tmp <= thermo_code_i(96 downto 79);
- when "00111" => interval_tmp <= thermo_code_i(112 downto 95);
- when "01000" => interval_tmp <= thermo_code_i(128 downto 111);
- when "01001" => interval_tmp <= thermo_code_i(144 downto 127);
- when "01010" => interval_tmp <= thermo_code_i(160 downto 143);
- when "01011" => interval_tmp <= thermo_code_i(176 downto 159);
- when "01100" => interval_tmp <= thermo_code_i(192 downto 175);
- when "01101" => interval_tmp <= thermo_code_i(208 downto 191);
- when "01110" => interval_tmp <= thermo_code_i(224 downto 207);
- when "01111" => interval_tmp <= thermo_code_i(240 downto 223);
- when "10000" => interval_tmp <= thermo_code_i(256 downto 239);
- when "10001" => interval_tmp <= thermo_code_i(272 downto 255);
- when "10010" => interval_tmp <= (not edge_type_i) & thermo_code_i(287 downto 271);
- when others => interval_tmp <= (others => '1');
- end case;
- end process Interval_Selection;
-
- Assign_Interval : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_i <= (others => '1');
- elsif edge_type_i = '0' then
- interval_i <= interval_tmp;
- else
- interval_i <= not interval_tmp;
- end if;
- end if;
- end process Assign_Interval;
-
- Bubble_Correction_Normal : process (interval_bc_norm, interval_i)
- begin -- The bubble correction is done by detecting the "100" code pattern
- interval_bc_norm(0) <= interval_i(3) and interval_i(2) and not(interval_i(1)) and not(interval_i(0));
- interval_bc_norm(1) <= interval_i(4) and interval_i(3) and not(interval_i(2)) and not(interval_i(1));
- interval_bc_norm(2) <= interval_i(5) and interval_i(4) and not(interval_i(3)) and not(interval_i(2));
- interval_bc_norm(3) <= interval_i(6) and interval_i(5) and not(interval_i(4)) and not(interval_i(3));
- interval_bc_norm(4) <= interval_i(7) and interval_i(6) and not(interval_i(5)) and not(interval_i(4));
- interval_bc_norm(5) <= interval_i(8) and interval_i(7) and not(interval_i(6)) and not(interval_i(5));
- interval_bc_norm(6) <= interval_i(9) and interval_i(8) and not(interval_i(7)) and not(interval_i(6));
- interval_bc_norm(7) <= interval_i(10) and interval_i(9) and not(interval_i(8)) and not(interval_i(7));
- interval_bc_norm(8) <= interval_i(11) and interval_i(10) and not(interval_i(9)) and not(interval_i(8));
- interval_bc_norm(9) <= interval_i(12) and interval_i(11) and not(interval_i(10)) and not(interval_i(9));
- interval_bc_norm(10) <= interval_i(13) and interval_i(12) and not(interval_i(11)) and not(interval_i(10));
- interval_bc_norm(11) <= interval_i(14) and interval_i(13) and not(interval_i(12)) and not(interval_i(11));
- interval_bc_norm(12) <= interval_i(15) and interval_i(14) and not(interval_i(13)) and not(interval_i(12));
- interval_bc_norm(13) <= interval_i(16) and interval_i(15) and not(interval_i(14)) and not(interval_i(13));
- interval_bc_norm(14) <= interval_i(17) and interval_i(16) and not(interval_i(15)) and not(interval_i(14));
- end process Bubble_Correction_Normal;
-
- Bubble_Correction_Bubble : process (interval_bc_bbl, interval_i)
- begin -- The bubble correction is done by detecting the "100" code pattern
- interval_bc_bbl(0) <= interval_i(3) and not(interval_i(2)) and interval_i(1) and not(interval_i(0));
- interval_bc_bbl(1) <= interval_i(4) and not(interval_i(3)) and interval_i(2) and not(interval_i(1));
- interval_bc_bbl(2) <= interval_i(5) and not(interval_i(4)) and interval_i(3) and not(interval_i(2));
- interval_bc_bbl(3) <= interval_i(6) and not(interval_i(5)) and interval_i(4) and not(interval_i(3));
- interval_bc_bbl(4) <= interval_i(7) and not(interval_i(6)) and interval_i(5) and not(interval_i(4));
- interval_bc_bbl(5) <= interval_i(8) and not(interval_i(7)) and interval_i(6) and not(interval_i(5));
- interval_bc_bbl(6) <= interval_i(9) and not(interval_i(8)) and interval_i(7) and not(interval_i(6));
- interval_bc_bbl(7) <= interval_i(10) and not(interval_i(9)) and interval_i(8) and not(interval_i(7));
- interval_bc_bbl(8) <= interval_i(11) and not(interval_i(10)) and interval_i(9) and not(interval_i(8));
- interval_bc_bbl(9) <= interval_i(12) and not(interval_i(11)) and interval_i(10) and not(interval_i(9));
- interval_bc_bbl(10) <= interval_i(13) and not(interval_i(12)) and interval_i(11) and not(interval_i(10));
- interval_bc_bbl(11) <= interval_i(14) and not(interval_i(13)) and interval_i(12) and not(interval_i(11));
- interval_bc_bbl(12) <= interval_i(15) and not(interval_i(14)) and interval_i(13) and not(interval_i(12));
- interval_bc_bbl(13) <= interval_i(16) and not(interval_i(15)) and interval_i(14) and not(interval_i(13));
- interval_bc_bbl(14) <= interval_i(17) and not(interval_i(16)) and interval_i(15) and not(interval_i(14));
- end process Bubble_Correction_Bubble;
-
- interval_bc <= interval_bc_bbl or interval_bc_norm;
-
- Interval_Decoding : process (clk_i, rst_i)
- begin -- The decoding of the bubble corrected 1-of-N code is done by the OR gates
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_binary <= (others => '0');
- else
- interval_binary(0) <= interval_bc(0) or interval_bc(2) or interval_bc(4) or interval_bc(6) or
- interval_bc(8) or interval_bc(10) or interval_bc(12) or interval_bc(14);
- interval_binary(1) <= interval_bc(1) or interval_bc(2) or interval_bc(5) or interval_bc(6) or
- interval_bc(9) or interval_bc(10) or interval_bc(13) or interval_bc(14);
- interval_binary(2) <= interval_bc(3) or interval_bc(4) or interval_bc(5) or interval_bc(6) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- interval_binary(3) <= interval_bc(7) or interval_bc(8) or interval_bc(9) or interval_bc(10) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- end if;
- end if;
- end process Interval_Decoding;
-
- Binary_Code_Calculation : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- binary_code_f <= (others => '0');
- binary_code_r <= (others => '0');
- BINARY_CODE_OUTPUT <= (others => '0');
- FINISHED_OUTPUT <= '0';
- elsif counter_out_i = "010" then
- binary_code_f <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "101" then
- binary_code_r <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "110" then
- BINARY_CODE_OUTPUT <= std_logic_vector(to_unsigned((to_integer(unsigned(binary_code_r)) + to_integer(unsigned(binary_code_f))), 10));
- FINISHED_OUTPUT <= '1';
- else
- BINARY_CODE_OUTPUT <= (others => '0');
- FINISHED_OUTPUT <= '0';
- end if;
- end if;
- end process Binary_Code_Calculation;
-
- Counter_Countrol : process (clk_i, rst_i)
- begin -- The control of the "counter_up_i" signal
- if rising_edge(clk_i) then
- if rst_i = '1' then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- elsif start_input_i = '1' then
- counter_up_i <= '1';
- elsif counter_out_i = "110" then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- else
- counter_reset_i <= '0';
- end if;
- end if;
- end process Counter_Countrol;
-
-end Encoder_288_Bit;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.all;
---use ieee.std_logic_arith.all;
---use ieee.numeric_std.all;
-
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity Encoder_320_Bit is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_INPUT : in std_logic;
- THERMO_CODE_INPUT : in std_logic_vector(319 downto 0);
- FINISHED_OUTPUT : out std_logic;
- BINARY_CODE_OUTPUT : out std_logic_vector(9 downto 0));
-end Encoder_320_Bit;
-
-architecture Encoder_320_Bit of Encoder_320_Bit is
-
- -- component definitions
- component up_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
- end component;
---
- component ORCALUT4
- generic(
- INIT : bit_vector);
- port (
- A, B, C, D : in std_logic;
- Z : out std_logic);
- end component;
-
- -- signal declerations
- signal clk_i : std_logic;
- signal rst_i : std_logic;
- signal start_input_i : std_logic;
- signal thermo_code_i : std_logic_vector(319 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- signal P_lut : std_logic_vector(19 downto 0);
- signal P_one : std_logic_vector(19 downto 0);
- signal mux_control : std_logic_vector(4 downto 0);
- signal interval_tmp : std_logic_vector(17 downto 0);
- signal interval_i : std_logic_vector(17 downto 0);
- signal interval_bc : std_logic_vector(14 downto 0);
- signal interval_bc_norm : std_logic_vector(14 downto 0);
- signal interval_bc_bbl : std_logic_vector(14 downto 0);
- signal interval_binary : std_logic_vector(3 downto 0);
- signal counter_reset_i : std_logic;
- signal counter_up_i : std_logic;
- signal counter_out_i : std_logic_vector(2 downto 0);
- signal binary_code_f : std_logic_vector(8 downto 0);
- signal binary_code_r : std_logic_vector(8 downto 0);
- signal edge_type_i : std_logic; -- 0 => 0-1 edge, 1 => 1-0 edge
-
-begin
-
- clk_i <= CLK;
- rst_i <= RESET;
- start_input_i <= START_INPUT;
- thermo_code_i <= THERMO_CODE_INPUT;
-
- --Component instantiations
-
- Process_Counter : up_counter
- generic map (
- NUMBER_OF_BITS => 3)
- port map (
- CLK => clk_i,
- RESET => counter_reset_i,
- COUNT_OUT => counter_out_i,
- UP_IN => counter_up_i);
-
- Interval_Determination_First : ORCALUT4
- generic map (INIT => X"A815")
- port map (A => '1', B => '1', C => thermo_code_i(0), D => edge_type_i,
- Z => P_lut(0));
---
- Interval_Determination : for i in 1 to 19 generate
- U : ORCALUT4
- generic map (INIT => X"A815")
- port map (A => thermo_code_i(16*i-2), B => thermo_code_i(16*i-1), C => thermo_code_i(16*i), D => edge_type_i,
- Z => P_lut(i));
- end generate Interval_Determination;
--------------------------------------------------------------------------------
-
- Change_Edge_Type : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' or counter_out_i = "111" then
- edge_type_i <= '0';
- elsif counter_out_i = "001" then
- edge_type_i <= '1';
- end if;
- end if;
- end process Change_Edge_Type;
-
- Gen_P_one : for i in 0 to 18 generate
- P_one(i) <= P_lut(i) and (not P_lut(i+1));
- end generate Gen_P_one;
-
- P_one_assign : process (edge_type_i, P_lut)
- begin
- if edge_type_i = '0' then
- P_one(19) <= P_lut(19);
- else
- P_one(19) <= '0';
- end if;
- end process P_one_assign;
-
- Interval_Number_to_Binary : process (clk_i, rst_i)
- begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary
- -- code for the control of the MUX.
- if rising_edge(clk_i) then
- if rst_i = '1' then
- mux_control <= (others => '0');
- else
- mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or
- P_one(12) or P_one(14) or P_one(16) or P_one(18);
- mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or
- P_one(13) or P_one(14) or P_one(17) or P_one(18);
- mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14) or P_one(19);
- mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14);
- mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19);
- end if;
- end if;
- end process Interval_Number_to_Binary;
-
- Interval_Selection : process (mux_control, thermo_code_i, edge_type_i)
- begin -- The interval with the 0-1 transition is selected.
- case mux_control is
- when "00001" => interval_tmp <= thermo_code_i(16 downto 0) & edge_type_i;
- when "00010" => interval_tmp <= thermo_code_i(32 downto 15);
- when "00011" => interval_tmp <= thermo_code_i(48 downto 31);
- when "00100" => interval_tmp <= thermo_code_i(64 downto 47);
- when "00101" => interval_tmp <= thermo_code_i(80 downto 63);
- when "00110" => interval_tmp <= thermo_code_i(96 downto 79);
- when "00111" => interval_tmp <= thermo_code_i(112 downto 95);
- when "01000" => interval_tmp <= thermo_code_i(128 downto 111);
- when "01001" => interval_tmp <= thermo_code_i(144 downto 127);
- when "01010" => interval_tmp <= thermo_code_i(160 downto 143);
- when "01011" => interval_tmp <= thermo_code_i(176 downto 159);
- when "01100" => interval_tmp <= thermo_code_i(192 downto 175);
- when "01101" => interval_tmp <= thermo_code_i(208 downto 191);
- when "01110" => interval_tmp <= thermo_code_i(224 downto 207);
- when "01111" => interval_tmp <= thermo_code_i(240 downto 223);
- when "10000" => interval_tmp <= thermo_code_i(256 downto 239);
- when "10001" => interval_tmp <= thermo_code_i(272 downto 255);
- when "10010" => interval_tmp <= thermo_code_i(288 downto 271);
- when "10011" => interval_tmp <= thermo_code_i(304 downto 287);
- when "10100" => interval_tmp <= (not edge_type_i) & thermo_code_i(319 downto 303);
- when others => interval_tmp <= (others => '1');
- end case;
- end process Interval_Selection;
-
- Assign_Interval : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_i <= (others => '1');
- elsif edge_type_i = '0' then
- interval_i <= interval_tmp;
- else
- interval_i <= not interval_tmp;
- end if;
- end if;
- end process Assign_Interval;
-
- Bubble_Correction_Normal : process (interval_bc_norm, interval_i)
- begin -- The bubble correction is done by detecting the "1100" code pattern
- interval_bc_norm(0) <= interval_i(3) and interval_i(2) and not(interval_i(1)) and not(interval_i(0));
- interval_bc_norm(1) <= interval_i(4) and interval_i(3) and not(interval_i(2)) and not(interval_i(1));
- interval_bc_norm(2) <= interval_i(5) and interval_i(4) and not(interval_i(3)) and not(interval_i(2));
- interval_bc_norm(3) <= interval_i(6) and interval_i(5) and not(interval_i(4)) and not(interval_i(3));
- interval_bc_norm(4) <= interval_i(7) and interval_i(6) and not(interval_i(5)) and not(interval_i(4));
- interval_bc_norm(5) <= interval_i(8) and interval_i(7) and not(interval_i(6)) and not(interval_i(5));
- interval_bc_norm(6) <= interval_i(9) and interval_i(8) and not(interval_i(7)) and not(interval_i(6));
- interval_bc_norm(7) <= interval_i(10) and interval_i(9) and not(interval_i(8)) and not(interval_i(7));
- interval_bc_norm(8) <= interval_i(11) and interval_i(10) and not(interval_i(9)) and not(interval_i(8));
- interval_bc_norm(9) <= interval_i(12) and interval_i(11) and not(interval_i(10)) and not(interval_i(9));
- interval_bc_norm(10) <= interval_i(13) and interval_i(12) and not(interval_i(11)) and not(interval_i(10));
- interval_bc_norm(11) <= interval_i(14) and interval_i(13) and not(interval_i(12)) and not(interval_i(11));
- interval_bc_norm(12) <= interval_i(15) and interval_i(14) and not(interval_i(13)) and not(interval_i(12));
- interval_bc_norm(13) <= interval_i(16) and interval_i(15) and not(interval_i(14)) and not(interval_i(13));
- interval_bc_norm(14) <= interval_i(17) and interval_i(16) and not(interval_i(15)) and not(interval_i(14));
- end process Bubble_Correction_Normal;
-
- Bubble_Correction_Bubble : process (interval_bc_bbl, interval_i)
- begin -- The bubble correction is done by detecting the "1010" code pattern
- interval_bc_bbl(0) <= interval_i(3) and not(interval_i(2)) and interval_i(1) and not(interval_i(0));
- interval_bc_bbl(1) <= interval_i(4) and not(interval_i(3)) and interval_i(2) and not(interval_i(1));
- interval_bc_bbl(2) <= interval_i(5) and not(interval_i(4)) and interval_i(3) and not(interval_i(2));
- interval_bc_bbl(3) <= interval_i(6) and not(interval_i(5)) and interval_i(4) and not(interval_i(3));
- interval_bc_bbl(4) <= interval_i(7) and not(interval_i(6)) and interval_i(5) and not(interval_i(4));
- interval_bc_bbl(5) <= interval_i(8) and not(interval_i(7)) and interval_i(6) and not(interval_i(5));
- interval_bc_bbl(6) <= interval_i(9) and not(interval_i(8)) and interval_i(7) and not(interval_i(6));
- interval_bc_bbl(7) <= interval_i(10) and not(interval_i(9)) and interval_i(8) and not(interval_i(7));
- interval_bc_bbl(8) <= interval_i(11) and not(interval_i(10)) and interval_i(9) and not(interval_i(8));
- interval_bc_bbl(9) <= interval_i(12) and not(interval_i(11)) and interval_i(10) and not(interval_i(9));
- interval_bc_bbl(10) <= interval_i(13) and not(interval_i(12)) and interval_i(11) and not(interval_i(10));
- interval_bc_bbl(11) <= interval_i(14) and not(interval_i(13)) and interval_i(12) and not(interval_i(11));
- interval_bc_bbl(12) <= interval_i(15) and not(interval_i(14)) and interval_i(13) and not(interval_i(12));
- interval_bc_bbl(13) <= interval_i(16) and not(interval_i(15)) and interval_i(14) and not(interval_i(13));
- interval_bc_bbl(14) <= interval_i(17) and not(interval_i(16)) and interval_i(15) and not(interval_i(14));
- end process Bubble_Correction_Bubble;
-
- interval_bc <= interval_bc_bbl or interval_bc_norm;
-
- Interval_Decoding : process (clk_i, rst_i)
- begin -- The decoding of the bubble corrected 1-of-N code is done by the OR gates
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_binary <= (others => '0');
- else
- interval_binary(0) <= interval_bc(0) or interval_bc(2) or interval_bc(4) or interval_bc(6) or
- interval_bc(8) or interval_bc(10) or interval_bc(12) or interval_bc(14);
- interval_binary(1) <= interval_bc(1) or interval_bc(2) or interval_bc(5) or interval_bc(6) or
- interval_bc(9) or interval_bc(10) or interval_bc(13) or interval_bc(14);
- interval_binary(2) <= interval_bc(3) or interval_bc(4) or interval_bc(5) or interval_bc(6) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- interval_binary(3) <= interval_bc(7) or interval_bc(8) or interval_bc(9) or interval_bc(10) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- end if;
- end if;
- end process Interval_Decoding;
-
- Binary_Code_Calculation : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- binary_code_f <= (others => '0');
- binary_code_r <= (others => '0');
- BINARY_CODE_OUTPUT <= (others => '0');
- FINISHED_OUTPUT <= '0';
- elsif counter_out_i = "010" then
- binary_code_f <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "101" then
- binary_code_r <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "110" then
- BINARY_CODE_OUTPUT <= std_logic_vector(to_unsigned((to_integer(unsigned(binary_code_r)) + to_integer(unsigned(binary_code_f))), 10));
- FINISHED_OUTPUT <= '1';
- else
- BINARY_CODE_OUTPUT <= (others => '0');
- FINISHED_OUTPUT <= '0';
- end if;
- end if;
- end process Binary_Code_Calculation;
-
- Counter_Countrol : process (clk_i, rst_i)
- begin -- The control of the "counter_up_i" signal
- if rising_edge(clk_i) then
- if rst_i = '1' then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- elsif start_input_i = '1' then
- counter_up_i <= '1';
- elsif counter_out_i = "110" then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- else
- counter_reset_i <= '0';
- end if;
- end if;
- end process Counter_Countrol;
-
-end Encoder_320_Bit;
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
--- Module Version: 5.0
---/opt/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 00 -rp 1100 -addr_width 8 -data_width 4 -num_rows 256 -resetmode SYNC -memfile /home/cahit/Projects/TDC/IPExpress_Modules/ROM_FIFO_Mask/ROM_FIFO_0/rom0_mem_file.mem -memformat hex -cascade -1 -e
-
--- Fri May 27 11:15:53 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity ROM_FIFO is
- port (
- Address: in std_logic_vector(7 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(3 downto 0));
-end ROM_FIFO;
-
-architecture Structure of ROM_FIFO is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute INITVAL_3F : string;
- attribute INITVAL_3E : string;
- attribute INITVAL_3D : string;
- attribute INITVAL_3C : string;
- attribute INITVAL_3B : string;
- attribute INITVAL_3A : string;
- attribute INITVAL_39 : string;
- attribute INITVAL_38 : string;
- attribute INITVAL_37 : string;
- attribute INITVAL_36 : string;
- attribute INITVAL_35 : string;
- attribute INITVAL_34 : string;
- attribute INITVAL_33 : string;
- attribute INITVAL_32 : string;
- attribute INITVAL_31 : string;
- attribute INITVAL_30 : string;
- attribute INITVAL_2F : string;
- attribute INITVAL_2E : string;
- attribute INITVAL_2D : string;
- attribute INITVAL_2C : string;
- attribute INITVAL_2B : string;
- attribute INITVAL_2A : string;
- attribute INITVAL_29 : string;
- attribute INITVAL_28 : string;
- attribute INITVAL_27 : string;
- attribute INITVAL_26 : string;
- attribute INITVAL_25 : string;
- attribute INITVAL_24 : string;
- attribute INITVAL_23 : string;
- attribute INITVAL_22 : string;
- attribute INITVAL_21 : string;
- attribute INITVAL_20 : string;
- attribute INITVAL_1F : string;
- attribute INITVAL_1E : string;
- attribute INITVAL_1D : string;
- attribute INITVAL_1C : string;
- attribute INITVAL_1B : string;
- attribute INITVAL_1A : string;
- attribute INITVAL_19 : string;
- attribute INITVAL_18 : string;
- attribute INITVAL_17 : string;
- attribute INITVAL_16 : string;
- attribute INITVAL_15 : string;
- attribute INITVAL_14 : string;
- attribute INITVAL_13 : string;
- attribute INITVAL_12 : string;
- attribute INITVAL_11 : string;
- attribute INITVAL_10 : string;
- attribute INITVAL_0F : string;
- attribute INITVAL_0E : string;
- attribute INITVAL_0D : string;
- attribute INITVAL_0C : string;
- attribute INITVAL_0B : string;
- attribute INITVAL_0A : string;
- attribute INITVAL_09 : string;
- attribute INITVAL_08 : string;
- attribute INITVAL_07 : string;
- attribute INITVAL_06 : string;
- attribute INITVAL_05 : string;
- attribute INITVAL_04 : string;
- attribute INITVAL_03 : string;
- attribute INITVAL_02 : string;
- attribute INITVAL_01 : string;
- attribute INITVAL_00 : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute GSR : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute MEM_LPC_FILE of ROM_FIFO_0_0_0 : label is "ROM_FIFO.lpc";
- attribute MEM_INIT_FILE of ROM_FIFO_0_0_0 : label is "rom0_mem_file.mem";
- attribute INITVAL_3F of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3E of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3D of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3C of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3B of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_3A of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_39 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_38 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_37 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_36 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_35 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_34 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_33 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_32 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_31 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_30 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2F of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2E of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2D of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2C of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2B of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_2A of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_29 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_28 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_27 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_26 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_25 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_24 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_23 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_22 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_21 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_20 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1F of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1E of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1D of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1C of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1B of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_1A of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_19 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_18 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_17 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_16 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_15 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_14 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_13 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_12 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_11 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_10 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0F of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0E of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0D of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0C of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0B of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0A of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_09 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_08 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_07 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_06 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_05 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_04 of ROM_FIFO_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_03 of ROM_FIFO_0_0_0 : label is "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010";
- attribute INITVAL_02 of ROM_FIFO_0_0_0 : label is "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010";
- attribute INITVAL_01 of ROM_FIFO_0_0_0 : label is "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010";
- attribute INITVAL_00 of ROM_FIFO_0_0_0 : label is "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010";
- attribute CSDECODE_B of ROM_FIFO_0_0_0 : label is "0b111";
- attribute CSDECODE_A of ROM_FIFO_0_0_0 : label is "0b000";
- attribute WRITEMODE_B of ROM_FIFO_0_0_0 : label is "NORMAL";
- attribute WRITEMODE_A of ROM_FIFO_0_0_0 : label is "NORMAL";
- attribute GSR of ROM_FIFO_0_0_0 : label is "DISABLED";
- attribute RESETMODE of ROM_FIFO_0_0_0 : label is "SYNC";
- attribute REGMODE_B of ROM_FIFO_0_0_0 : label is "NOREG";
- attribute REGMODE_A of ROM_FIFO_0_0_0 : label is "NOREG";
- attribute DATA_WIDTH_B of ROM_FIFO_0_0_0 : label is "4";
- attribute DATA_WIDTH_A of ROM_FIFO_0_0_0 : label is "4";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ROM_FIFO_0_0_0: DP16KB
- -- synopsys translate_off
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_02=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_01=> "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_00=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- CSDECODE_B=> "111", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- -- synopsys translate_on
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>Address(0),
- ADA3=>Address(1), ADA4=>Address(2), ADA5=>Address(3),
- ADA6=>Address(4), ADA7=>Address(5), ADA8=>Address(6),
- ADA9=>Address(7), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn,
- CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo,
- ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo,
- ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo,
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>scuba_vhi,
- CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>scuba_vlo,
- DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>open, DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of ROM_FIFO is
- for Structure
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use IEEE.NUMERIC_STD.all;
-use STD.TEXTIO.all;
-use IEEE.STD_LOGIC_TEXTIO.all;
-
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity TDC is
- generic (
- CHANNEL_NUMBER : integer range 0 to 64 := 8);
- port (
- RESET : in std_logic;
- CLK_TDC : in std_logic;
- CLK_READOUT : in std_logic;
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- TRIGGER_IN : in std_logic;
- TRIGGER_WIN_IN : in std_logic_vector(31 downto 0);
- DATA_OUT : out std_logic_vector(31 downto 0);
- TRB_WR_CLK_OUT : out std_logic;
- DATA_VALID_OUT : out std_logic;
- DATA_FINISHED_OUT : out std_logic;
- READY_OUT : out std_logic;
- TDC_DEBUG_00 : out std_logic_vector(31 downto 0)
- );
-end TDC;
-
-architecture TDC of TDC is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Channel
- generic (
- CHANNEL_ID : integer range 0 to 15);
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(15 downto 0)
- );
- end component;
---
- component ROM_FIFO
- port (
- Address : in std_logic_vector(7 downto 0);
- OutClock : in std_logic;
- OutClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(3 downto 0));
- end component;
---
- component up_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
- end component;
---
- component edge_to_pulse_fast
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- SIGNAL_IN : in std_logic;
- PULSE_OUT : out std_logic);
- end component;
---
- component bit_sync
- generic (
- DEPTH : integer);
- port (
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic;
- D_OUT : out std_logic);
- end component;
---
- component ddr_off
- port (
- Clk : in std_logic;
- Data : in std_logic_vector(1 downto 0);
- Q : out std_logic_vector(0 downto 0));
- end component;
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
--- Input Output signals
- signal clk_i : std_logic;
- signal clk_100_i : std_logic;
- signal lock_100_i : std_logic;
- signal reset_i : std_logic;
- signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal trigger_in_i : std_logic;
- signal trig_pulse_i : std_logic;
- signal trig_sync_i : std_logic;
- signal data_out_i : std_logic_vector(31 downto 0);
- signal data_valid_i : std_logic;
- signal data_finished_i : std_logic;
-
--- Other signals
- type FSM is (IDLE, WR_HEADER, WR_ERROR, WR_TRAILOR, WAIT_FOR_FIFO_NR,
- APPLY_MASK, RD_CHANNEL_1, RD_CHANNEL_2, RD_CHANNEL_3,
- RD_CHANNEL_4, RD_CHANNEL_5, RD_CHANNEL_6, RD_CHANNEL, FINISH);
- signal FSM_CURRENT, FSM_NEXT : FSM;
---
- signal clk_to_TRB_i : std_logic_vector(0 downto 0);
- signal start_rdout_i : std_logic;
- signal rdout_busy_fsm : std_logic;
- signal rdout_busy_i : std_logic;
- signal send_finished_fsm : std_logic;
- signal send_finished_i : std_logic;
- signal wr_header_fsm : std_logic;
- signal wr_header_i : std_logic;
- signal wr_ch_data_fsm : std_logic;
- signal wr_ch_data_i : std_logic;
- signal wr_error_fsm : std_logic;
- signal wr_error_i : std_logic;
- signal wr_trailor_fsm : std_logic;
- signal wr_trailor_i : std_logic;
- signal fsm_debug_fsm : std_logic_vector(3 downto 0);
- signal fsm_debug_i : std_logic_vector(3 downto 0);
- signal mask_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal updt_mask_i : std_logic;
- signal updt_mask_fsm : std_logic;
- signal fifo_nr_int : integer range 0 to 16 := 0;
- signal fifo_nr : integer range 0 to 15 := 0;
- signal updt_index_i : std_logic;
- signal updt_index_fsm : std_logic;
- signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal trig_time_i : std_logic_vector(15 downto 0);
- signal TW_pre : std_logic_vector(15 downto 0);
- signal TW_post : std_logic_vector(15 downto 0);
- signal channel_hit_time : std_logic_vector(15 downto 0);
- signal trig_win_l : std_logic;
- signal trig_win_r : std_logic;
- signal ctwe_cntr_i : std_logic_vector(15 downto 0);
- signal ctwe_up_i : std_logic;
- signal ctwe_reset_i : std_logic;
- signal trig_win_end_i : std_logic;
---
- type Std_Logic_8_array is array (0 to 1) of std_logic_vector(3 downto 0);
- signal fifo_nr_hex : Std_Logic_8_array;
---
- signal coarse_counter_i : std_logic_vector(15 downto 0);
- signal trig_win_pre : std_logic_vector(15 downto 0);
- signal trig_win_post : std_logic_vector(15 downto 0);
- signal channel_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_3reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_4reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal LE_cntr_up : std_logic;
- signal LE_cntr_i : std_logic_vector(15 downto 0);
---
- type channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0);
- signal channel_data_i : channel_data_array;
- signal channel_data_reg : channel_data_array;
- signal channel_data_2reg : channel_data_array;
- signal channel_data_3reg : channel_data_array;
- signal channel_data_4reg : channel_data_array;
-
--------------------------------------------------------------------------------
--- test signals
--------------------------------------------------------------------------------
- signal tdc_debug_i : std_logic_vector(31 downto 0);
- signal tdc_debug_out_i : std_logic_vector(31 downto 0);
-
--------------------------------------------------------------------------------
-
-begin
-
- reset_i <= RESET;
- clk_i <= CLK_TDC;
- clk_100_i <= CLK_READOUT;
- trigger_in_i <= TRIGGER_IN;
- hit_in_i <= HIT_IN;
- trig_win_pre <= TRIGGER_WIN_IN(15 downto 0);
- trig_win_post <= TRIGGER_WIN_IN(31 downto 16);
-
--------------------------------------------------------------------------------
--- COMPONENT INSTANTINIATIONS
--------------------------------------------------------------------------------
--- Channels
- GEN_Channels : for i in 0 to CHANNEL_NUMBER - 1 generate
- Channels : Channel
- generic map (
- CHANNEL_ID => i)
- port map (
- RESET => reset_i,
- CLK => clk_i,
- HIT_IN => hit_in_i(i),
- READ_EN_IN => rd_en_i(i),
- FIFO_DATA_OUT => channel_data_i(i),
- FIFO_EMPTY_OUT => channel_empty_i(i),
- FIFO_FULL_OUT => channel_full_i(i),
- COARSE_COUNTER_IN => coarse_counter_i
- );
- end generate GEN_Channels;
- channel_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF";
-
--- Common Coarse counter
- COARSE_COUNTER : up_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => clk_i,
- RESET => reset_i,
- COUNT_OUT => coarse_counter_i,
- UP_IN => '1');
-
--------------------------------------------------------------------------------
--- CLOCK SETTINGS
--------------------------------------------------------------------------------
-
- --purpose: ddr flip-flop generation for the clock output to the TRB board
- DDR_FF_for_TRB_CLK : ddr_off
- port map (
- Clk => clk_100_i,
- Data => "01",
- Q => clk_to_TRB_i);
- TRB_WR_CLK_OUT <= clk_to_TRB_i(0);
-
--------------------------------------------------------------------------------
--- READOUT
--------------------------------------------------------------------------------
--- Trigger Setup, Synchronisation, Accept, Timing and Local Event Counter
-
- -- purpose: synchronises the trigger signal to 200 MHz clock domain
- TRIGGER_SYNC : bit_sync
- generic map (
- DEPTH => 3)
- port map (
- RESET => '0',
- CLK0 => clk_100_i,
- CLK1 => clk_100_i,
- D_IN => trigger_in_i,
- D_OUT => trig_sync_i);
-
- -- purpose: Generates pulse from the trigger signals
- Trigger_Pulse : edge_to_pulse_fast
- port map (
- RESET => reset_i,
- CLK => clk_100_i,
- SIGNAL_IN => trig_sync_i,
- PULSE_OUT => trig_pulse_i);
-
- -- purpose: Accepts the trigger according to the readout process situation
- TRIGGER_ACCEPT : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- start_rdout_i <= '0';
- elsif rdout_busy_i = '0' and trig_pulse_i = '1' then
- start_rdout_i <= '1';
- else
- start_rdout_i <= '0';
- end if;
- end if;
- end process TRIGGER_ACCEPT;
-
- -- purpose: Counts hardware triggers
- LOCAL_EVENT_COUNTER : up_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => clk_100_i,
- RESET => reset_i,
- COUNT_OUT => LE_cntr_i,
- UP_IN => LE_cntr_up);
- LE_cntr_up <= start_rdout_i;
-
- -- purpose: Defines the trigger time with respect to the coarse counter
- Define_Trigger_Time : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- trig_time_i <= (others => '0');
- elsif start_rdout_i = '1' then
- trig_time_i <= coarse_counter_i - 6;
- end if;
- end if;
- end process Define_Trigger_Time;
--------------------------------------------------------------------------------
--- Trigger Window
-
- --purpose: Controls the trigger window end
- Check_Trig_Win_End_Conrollers : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- ctwe_up_i <= '0';
- ctwe_reset_i <= '1';
- trig_win_end_i <= '0';
- elsif start_rdout_i = '1' then
- ctwe_up_i <= '1';
- ctwe_reset_i <= '0';
- trig_win_end_i <= '0';
- elsif ctwe_cntr_i = (trig_win_post)then
- ctwe_up_i <= '0';
- ctwe_reset_i <= '1';
- trig_win_end_i <= '1';
- else
- ctwe_up_i <= ctwe_up_i;
- ctwe_reset_i <= ctwe_reset_i;
- trig_win_end_i <= '0';
- end if;
- end if;
- end process Check_Trig_Win_End_Conrollers;
-
- --purpose: Trigger Window Counter
- Check_Trig_Win_End : up_counter
- generic map (
- NUMBER_OF_BITS => 16)
- port map (
- CLK => clk_100_i,
- RESET => ctwe_reset_i,
- COUNT_OUT => ctwe_cntr_i,
- UP_IN => ctwe_up_i);
-
- --purpose: Calculates the position of the trigger window edges
- Trig_Win_Calculation : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- TW_pre <= (others => '0');
- TW_post <= (others => '0');
- channel_hit_time <= (others => '0');
- else
- TW_pre <= trig_time_i - trig_win_pre;
- TW_post <= trig_time_i + trig_win_post;
- channel_hit_time <= channel_data_2reg(fifo_nr)(25 downto 10);
- end if;
- end if;
- end process Trig_Win_Calculation;
-
- --purpose: Controls if the data coming from the channel is greater than the
- --trigger window pre-edge
- Check_Trig_Win_Left : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- trig_win_l <= '0';
- elsif TW_pre <= channel_hit_time then
- trig_win_l <= '1';
- else
- trig_win_l <= '0';
- end if;
- end if;
- end process Check_Trig_Win_Left;
-
- --purpose: Controls if the data coming from the channel is smaller than the
- --trigger window post-edge
- Check_Trig_Win_Right : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- trig_win_r <= '0';
- elsif channel_hit_time <= TW_post then
- trig_win_r <= '1';
- else
- trig_win_r <= '0';
- end if;
- end if;
- end process Check_Trig_Win_Right;
--------------------------------------------------------------------------------
--- Creating mask and Generating the fifo nr to be read
-
- -- purpose: Creats and updates the mask to determine the non-empty FIFOs
- CREAT_MASK : process (clk_100_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- mask_i <= (others => '1');
- elsif trig_win_end_i = '1' then
- mask_i <= channel_empty_i;
- elsif updt_mask_i = '1' then
- mask_i(fifo_nr) <= '1';
- else
- mask_i <= mask_i;
- end if;
- end if;
- end process CREAT_MASK;
-
- ROM0 : ROM_FIFO
- port map (
- Address => mask_i(7 downto 0),
- OutClock => clk_100_i,
- OutClockEn => '1',
- Reset => reset_i,
- Q => fifo_nr_hex(0));
--- ROM1 : ROM_FIFO
--- port map (
--- Address => mask_i(15 downto 8),
--- OutClock => clk_100_i,
--- OutClockEn => '1',
--- Reset => reset_i,
--- Q => fifo_nr_hex(1));
-
- -- purpose: Generates number of the FIFO, to be read, in integer
- CON_FIFO_NR_HEX_TO_INT : process (clk_100_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- fifo_nr_int <= CHANNEL_NUMBER;
- elsif fifo_nr_hex(0)(3) /= '1' then
- fifo_nr_int <= conv_integer("00000" & fifo_nr_hex(0)(2 downto 0));
--- elsif fifo_nr_hex(1)(3) /= '1' then
--- fifo_nr_int <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0));
- else
- fifo_nr_int <= CHANNEL_NUMBER;
- end if;
- end if;
- end process CON_FIFO_NR_HEX_TO_INT;
-
- --purpose: Updates the index number for the array signals
- UPDATE_INDEX_NR : process (clk_100_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- fifo_nr <= CHANNEL_NUMBER;
- elsif updt_index_i = '1' then
- fifo_nr <= fifo_nr_int;
- else
- fifo_nr <= fifo_nr;
- end if;
- end if;
- end process UPDATE_INDEX_NR;
--------------------------------------------------------------------------------
--- Data Out, Data Valid and Data Finished assigning according to the control
--- signals from the readout final-state-machine.
-
- Data_Out_MUX : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- data_out_i <= (others => '1');
- data_valid_i <= '0';
- else
- if wr_header_i = '1' then
- data_out_i <= x"aa00" & LE_cntr_i;
- data_valid_i <= '1';
- elsif wr_ch_data_i = '1' then
- if (TW_pre(15) = '1' and trig_time_i(15) = '0') or (TW_post(15) = '0' and trig_time_i(15) = '1') then
- if (trig_win_l = '0' and trig_win_r = '1') or (trig_win_l = '1' and trig_win_r = '0') then
- --data_out_i <= channel_data_3reg(fifo_nr);
- data_out_i <= channel_data_4reg(fifo_nr);
- data_valid_i <= '1';
- else
- data_out_i <= (others => '1');
- data_valid_i <= '0';
- end if;
- else
- if (trig_win_l = '1' and trig_win_r = '1') then
- --data_out_i <= channel_data_3reg(fifo_nr);
- data_out_i <= channel_data_4reg(fifo_nr);
- data_valid_i <= '1';
- else
- data_out_i <= (others => '1');
- data_valid_i <= '0';
- end if;
- end if;
- elsif wr_error_i = '1' then
- data_out_i <= x"ee000000";
- data_valid_i <= '1';
- elsif wr_trailor_i = '1' then
- data_out_i <= x"bb00" & LE_cntr_i;
- data_valid_i <= '1';
- else
- data_out_i <= (others => '1');
- data_valid_i <= '0';
- end if;
- end if;
- end if;
- end process Data_Out_MUX;
-
- DATA_OUT <= data_out_i;
- DATA_VALID_OUT <= data_valid_i;
-
- Send_Finished : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- data_finished_i <= '0';
- elsif send_finished_i = '1' then
- data_finished_i <= '1';
- else
- data_finished_i <= '0';
- end if;
- end if;
- end process Send_Finished;
-
- DATA_FINISHED_OUT <= data_finished_i;
- READY_OUT <= data_finished_i;
------------------------------------------------------------------------------
--- Data delay
-
- Delay_Channel_Data : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- channel_data_reg <= (others => x"00000000");
- channel_data_2reg <= (others => x"00000000");
- channel_data_3reg <= (others => x"00000000");
- channel_data_4reg <= (others => x"00000000");
- channel_empty_reg <= (others => '0');
- channel_empty_2reg <= (others => '0');
- channel_empty_3reg <= (others => '0');
- channel_empty_4reg <= (others => '0');
- else
- channel_data_reg <= channel_data_i;
- channel_data_2reg <= channel_data_reg;
- channel_data_3reg <= channel_data_2reg;
- channel_data_4reg <= channel_data_3reg;
- channel_empty_reg <= channel_empty_i;
- channel_empty_2reg <= channel_empty_reg;
- channel_empty_3reg <= channel_empty_2reg;
- channel_empty_4reg <= channel_empty_3reg;
- end if;
- end if;
- end process Delay_Channel_Data;
-
------------------------------------------------------------------------------
--- Readout Final-State-Machine
-
- --purpose: FSM for writing data
- FSM_CLK : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- FSM_CURRENT <= IDLE;
- rdout_busy_i <= '0';
- updt_index_i <= '0';
- updt_mask_i <= '0';
- wr_header_i <= '0';
- wr_ch_data_i <= '0';
- wr_error_i <= '0';
- wr_trailor_i <= '0';
- rd_en_i <= (others => '0');
- send_finished_i <= '0';
- fsm_debug_i <= x"0";
- else
- FSM_CURRENT <= FSM_NEXT;
- rdout_busy_i <= rdout_busy_fsm;
- updt_index_i <= updt_index_fsm;
- updt_mask_i <= updt_mask_fsm;
- wr_header_i <= wr_header_fsm;
- wr_ch_data_i <= wr_ch_data_fsm;
- wr_error_i <= wr_error_fsm;
- wr_trailor_i <= wr_trailor_fsm;
- rd_en_i <= rd_en_fsm;
- send_finished_i <= send_finished_fsm;
- fsm_debug_i <= fsm_debug_fsm;
- end if;
- end if;
- end process FSM_CLK;
-
- FSM_PROC : process (FSM_CURRENT, trig_win_end_i, fifo_nr_int, fifo_nr,
- channel_empty_4reg)
- begin
-
- rdout_busy_fsm <= '1';
- updt_index_fsm <= '0';
- updt_mask_fsm <= '0';
- wr_header_fsm <= '0';
- wr_ch_data_fsm <= '0';
- wr_error_fsm <= '0';
- wr_trailor_fsm <= '0';
- rd_en_fsm <= (others => '0');
- send_finished_fsm <= '0';
-
- case (FSM_CURRENT) is
- when IDLE =>
- if trig_win_end_i = '1' then
- rdout_busy_fsm <= '1';
- FSM_NEXT <= WR_HEADER;
- fsm_debug_fsm <= x"1";
- else
- rdout_busy_fsm <= '0';
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"2";
- end if;
---
- when WR_HEADER =>
- FSM_NEXT <= WAIT_FOR_FIFO_NR;
- wr_header_fsm <= '1';
- fsm_debug_fsm <= x"3";
---
- when WAIT_FOR_FIFO_NR =>
- FSM_NEXT <= APPLY_MASK;
- updt_index_fsm <= '1';
- fsm_debug_fsm <= x"4";
---
- when APPLY_MASK =>
- if fifo_nr_int = 8 then
- FSM_NEXT <= WR_ERROR;
- fsm_debug_fsm <= x"5";
- else
- FSM_NEXT <= RD_CHANNEL_1;
- rd_en_fsm(fifo_nr_int) <= '1';
- fsm_debug_fsm <= x"6";
- end if;
---
- when RD_CHANNEL_1 =>
- FSM_NEXT <= RD_CHANNEL_2;
- rd_en_fsm(fifo_nr_int) <= '1';
- updt_mask_fsm <= '1';
- fsm_debug_fsm <= x"7";
---
- when RD_CHANNEL_2 =>
- FSM_NEXT <= RD_CHANNEL_3;
- rd_en_fsm(fifo_nr_int) <= '1';
- fsm_debug_fsm <= x"7";
---
- when RD_CHANNEL_3 =>
- FSM_NEXT <= RD_CHANNEL_4;
- rd_en_fsm(fifo_nr_int) <= '1';
- fsm_debug_fsm <= x"7";
---
- when RD_CHANNEL_4 =>
- FSM_NEXT <= RD_CHANNEL_5;
- rd_en_fsm(fifo_nr_int) <= '1';
- fsm_debug_fsm <= x"7";
---
- when RD_CHANNEL_5 =>
- FSM_NEXT <= RD_CHANNEL;
- rd_en_fsm(fifo_nr) <= '1';
- fsm_debug_fsm <= x"7";
---
- when RD_CHANNEL =>
--- if channel_empty_3reg(fifo_nr) = '1' then
- if channel_empty_4reg(fifo_nr) = '1' then
- wr_ch_data_fsm <= '0';
- updt_index_fsm <= '1';
- FSM_NEXT <= APPLY_MASK;
- fsm_debug_fsm <= x"8";
- else
- wr_ch_data_fsm <= '1';
- rd_en_fsm(fifo_nr) <= '1';
- FSM_NEXT <= RD_CHANNEL;
- fsm_debug_fsm <= x"9";
- end if;
---
- when WR_ERROR =>
- wr_error_fsm <= '1';
- FSM_NEXT <= WR_TRAILOR;
- fsm_debug_fsm <= x"A";
---
- when WR_TRAILOR =>
- wr_trailor_fsm <= '1';
- FSM_NEXT <= FINISH;
- fsm_debug_fsm <= x"B";
---
- when FINISH =>
- send_finished_fsm <= '1';
- rdout_busy_fsm <= '0';
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"C";
---
- when others =>
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"D";
- end case;
- end process FSM_PROC;
-
--------------------------------------------------------------------------------
-
-
-
-
-
-
-
-
-
-
-
--------------------------------------------------------------------------------
--- Logic Analyser and Test Signals
-
--- tdc_debug_out_i(0) <= start_rdout_i;
--- tdc_debug_out_i(4 downto 1) <= fsm_debug_i;
--- tdc_debug_out_i(5) <= buf1_start_i;
--- tdc_debug_out_i(9 downto 6) <= buf1_fsm_debug_i;
--- tdc_debug_out_i(11 downto 10) <= data_finished_i; --2
--- tdc_debug_out_i(15 downto 12) <= data_len_0_i(5 downto 2); --12
--- tdc_debug_out_i(19 downto 16) <= data_len_1_i(5 downto 2); --12
--- tdc_debug_out_i(25 downto 24) <= clear_in_i;
--- tdc_debug_out_i(26) <=
--- tdc_debug_out_i(27) <= wr_ch_data_i;
--- tdc_debug_out_i(28) <= buf1_wr_ch_data_i;
--- tdc_debug_out_i(29) <= HIT_IN(0);
--- tdc_debug_out_i(31 downto 30) <= trigger_in_i;
-
- REG_OUTPUTS : process (clk_100_i, reset_i)
- begin
- if rising_edge(clk_100_i) then
- if reset_i = '1' then
- tdc_debug_i <= (others => '0');
- else
- tdc_debug_i <= tdc_debug_out_i;
- end if;
- end if;
- end process REG_OUTPUTS;
- TDC_DEBUG_00 <= tdc_debug_i;
-
-end TDC;
jspc29 / trb3.git / commitdiff