\r
THE_TESTBENCH: process\r
begin\r
+ -----------------------------------------------------------\r
-- Setup signals\r
+ -----------------------------------------------------------\r
reset <= '0';\r
lvl1_timing_trg_in <= '0'; -- real timing trigger\r
lvl1_pseudo_tmg_trg_in <= '0'; -- one clock pulse form TRB \r
trg_enable_in <= '0';\r
trg_invert_in <= '0';\r
\r
+ -----------------------------------------------------------\r
-- Reset the whole stuff\r
+ -----------------------------------------------------------\r
wait until rising_edge(clock);\r
reset <= '1';\r
wait until rising_edge(clock);\r
reset <= '0';\r
wait for 100 ns;\r
\r
+ -----------------------------------------------------------\r
-- Tests may start now\r
+ -----------------------------------------------------------\r
+\r
-- enable trigger\r
wait until rising_edge(clock);\r
trg_enable_in <= '1';\r
wait for 100 ns;\r
- \r
- -- receive one TRB fake trigger\r
+\r
+ -----------------------------------------------------------\r
+\r
+ -- ONE TRIGGER (timing)\r
+\r
+ -- receive one normal timing trigger\r
+ wait for 3 ns;\r
+ lvl1_timing_trg_in <= '1';\r
+ wait for 111 ns;\r
+ lvl1_timing_trg_in <= '0'; \r
+ wait for 1000 ns;\r
+\r
+ -- LVL1 packet is there\r
wait until rising_edge(clock);\r
- lvl1_pseudo_tmg_trg_in <= '1';\r
+ lvl1_trg_type_in <= x"1";\r
+ lvl1_trg_number_in <= x"0000";\r
+ lvl1_trg_code_in <= x"ab";\r
+ lvl1_trg_information_in <= x"000000";\r
wait until rising_edge(clock);\r
- lvl1_pseudo_tmg_trg_in <= '0';\r
- wait for 300 ns;\r
- \r
+ lvl1_trg_received_in <= '1';\r
+\r
+ wait for 211 ns; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '1'; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '0'; \r
+\r
+ wait until falling_edge(lvl1_trg_release_out);\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '0';\r
+ lvl1_trg_type_in <= x"0";\r
+ lvl1_trg_number_in <= x"0000";\r
+ lvl1_trg_code_in <= x"00";\r
+ lvl1_trg_information_in <= x"000000";\r
+\r
+ wait for 555 ns;\r
\r
- wait;\r
-----------------------------------------------------------\r
+\r
+ -- ONE TRIGGER (timing)\r
+\r
+ -- receive one normal timing trigger\r
+ wait for 3 ns;\r
+ lvl1_timing_trg_in <= '1';\r
+ wait for 111 ns;\r
+ lvl1_timing_trg_in <= '0'; \r
+ wait for 1000 ns;\r
+\r
+ -- LVL1 packet is there\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_type_in <= x"1";\r
+ lvl1_trg_number_in <= x"0001";\r
+ lvl1_trg_code_in <= x"71";\r
+ lvl1_trg_information_in <= x"000000";\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '1';\r
+\r
+ wait for 211 ns; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '1'; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '0'; \r
+\r
+ wait until falling_edge(lvl1_trg_release_out);\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '0';\r
+ lvl1_trg_type_in <= x"0";\r
+ lvl1_trg_number_in <= x"0000";\r
+ lvl1_trg_code_in <= x"00";\r
+ lvl1_trg_information_in <= x"000000";\r
+\r
+ wait for 555 ns;\r
+\r
-----------------------------------------------------------\r
- \r
+ -- ONE TRIGGER (timing, wrong counter on LVL1)\r
+\r
-- receive one normal timing trigger\r
wait for 3 ns;\r
lvl1_timing_trg_in <= '1';\r
wait for 111 ns;\r
lvl1_timing_trg_in <= '0'; \r
+ wait for 1000 ns;\r
+\r
+ -- LVL1 packet is there\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_type_in <= x"1";\r
+ lvl1_trg_number_in <= x"dead";\r
+ lvl1_trg_code_in <= x"cc";\r
+ lvl1_trg_information_in <= x"000000";\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '1';\r
+\r
+ wait for 211 ns; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '1'; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '0'; \r
+\r
+ wait until falling_edge(lvl1_trg_release_out);\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '0';\r
+ lvl1_trg_type_in <= x"0";\r
+ lvl1_trg_number_in <= x"0000";\r
+ lvl1_trg_code_in <= x"00";\r
+ lvl1_trg_information_in <= x"000000";\r
+\r
+ wait for 555 ns;\r
+\r
+ -----------------------------------------------------------\r
+ -- ONE TRIGGER (timing, missing LVL1)\r
+\r
+ -- receive one normal timing trigger\r
+ wait for 3 ns;\r
+ lvl1_timing_trg_in <= '1';\r
+ wait for 111 ns;\r
+ lvl1_timing_trg_in <= '0'; \r
+ wait for 1000 ns;\r
+\r
+ wait for 6 us;\r
+\r
+ -----------------------------------------------------------\r
+\r
+ -- ONE TRIGGER (timingtriggerless)\r
+ \r
+ -- LVL1 packet is there\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_type_in <= x"9";\r
+ lvl1_trg_number_in <= x"0002";\r
+ lvl1_trg_code_in <= x"f0";\r
+ lvl1_trg_information_in <= x"000080";\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '1';\r
+\r
+ wait for 211 ns; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '1'; \r
+ wait until rising_edge(clock);\r
+ lvl1_trg_release_in <= '0'; \r
+\r
+ wait until falling_edge(lvl1_trg_release_out);\r
+ wait until rising_edge(clock);\r
+ lvl1_trg_received_in <= '0';\r
+ lvl1_trg_type_in <= x"0";\r
+ lvl1_trg_number_in <= x"0000";\r
+ lvl1_trg_code_in <= x"00";\r
+ lvl1_trg_information_in <= x"000000";\r
+\r
+ wait for 555 ns;\r
+\r
+ -----------------------------------------------------------\r
+\r
+ wait;\r
+ \r
+ -----------------------------------------------------------\r
+ \r
+ -- receive one TRB fake trigger\r
+ wait until rising_edge(clock);\r
+ lvl1_pseudo_tmg_trg_in <= '1';\r
+ wait until rising_edge(clock);\r
+ lvl1_pseudo_tmg_trg_in <= '0';\r
wait for 300 ns;\r
\r
-- receive one spike\r