update Baseline calculation, invert input delay reset bit

diff --git a/adc/source/adc_18bit_input.vhd b/adc/source/adc_18bit_input.vhd
index 256771033802329bcf91dffdae55da95f2901335..0e7041d2e39f96ad14b89b8e8200e9ae6f8a61b3 100644 (file)
--- a/adc/source/adc_18bit_input.vhd
+++ b/adc/source/adc_18bit_input.vhd
@@ -46,9 +46,7 @@ signal data_reg_save  : std_logic_vector(27 downto 0);
 signal clock_reg      : std_logic_vector(27 downto 0);
 signal clock_reg_save : std_logic_vector(27 downto 0);
 
-constant TESTPATTERN  : std_logic_vector(17 downto 0) := 18x"281FC";
-
-signal start_timer    : unsigned(23 downto 0) := (others => '0');
+constant TESTPATTERN : std_logic_vector(17 downto 0) := 18x"281FC";
 
 begin
 
@@ -73,38 +71,30 @@ THE_CLOCK_OUT : entity work.adc_1ch_clk
     dout(0)  => ADC_CLK_OUT
     );
 
-
-PROC_START : process begin
-  wait until rising_edge(CLK_ADCRAW);
-  if RESET_ADC = '1' then
-    start_timer <= (others => '0');
-  elsif start_timer(start_timer'left) = '0' then
-    start_timer <= start_timer + 1;
-  end if;  
-end process;
+    
 
 PROC_CONTROL : process begin
   wait until rising_edge(CLK_ADCRAW);
 
-  if start_timer(start_timer'left) = '1' then
-    if cycle_counter = 30 then
-      cycle_counter <= 0;
-    else
-      cycle_counter <= cycle_counter + 1;
-    end if;
 
-    if     cycle_counter = 10 then
-      clock_enable <= '1';
-    elsif  cycle_counter = 19 then
-      clock_enable <= '0';
-    end if;
+  if cycle_counter = 30 then
+    cycle_counter <= 0;
+  else
+    cycle_counter <= cycle_counter + 1;
+  end if;
 
-    if cycle_counter = 0 or cycle_counter = 1 then
-      ADC_CNV_OUT <= '1';
-    else
-      ADC_CNV_OUT <= '0';
-    end if;
+  if cycle_counter <= 8 then
+    clock_enable <= '1';
+  else
+    clock_enable <= '0';
   end if;
+
+  if cycle_counter = 13 or cycle_counter = 14 then
+    ADC_CNV_OUT <= '1';
+  else
+    ADC_CNV_OUT <= '0';
+  end if;
+  
 end process;
     
 PROC_INPUT : process begin
@@ -122,18 +112,18 @@ PROC_INPUT : process begin
   
   if CONF_ALIGN_EN = '1' and data_reg(17 downto 0) = TESTPATTERN then
     cycle_input  <= 1;
-    data_shifted <= CONF_data_shifted;
+    data_shifted <= '0';
   elsif CONF_ALIGN_EN = '1' and data_reg(18 downto 1) = TESTPATTERN then
     cycle_input  <= 1;
-    data_shifted <= not CONF_data_shifted;
+    data_shifted <= '1';
   end if;
 
-  if data_in(3 downto 2) = "00" and cycle_input = 0 then
+  if data_in(3 downto 2) = "00" then
     cycle_input <= 0;
   end if;
   
   
-  if cycle_input = 10 then
+  if cycle_input = 9 then
     data_reg_save  <= data_reg;
     clock_reg_save <= clock_reg;
 

diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd
index 9acd0298244cb3ed8aab698a877e210d23ac83e4..9d95724e7631e505006ca1d1e0a9477c78ec1117 100644 (file)
--- a/adc/source/adc_addon.vhd
+++ b/adc/source/adc_addon.vhd
@@ -65,11 +65,11 @@ architecture arch of adc_addon is
   alias STROBE_shift_align_b   : std_logic is basic_control_strobes(9);
   alias STROBE_del_move_b      : std_logic is basic_control_strobes(11);
   
-  signal basic_control         : std_logic_vector(31 downto 0);
+  signal basic_control         : std_logic_vector(31 downto 0) := (others => '0');
   alias CONF_adc_stop           : std_logic is basic_control(0);
   -- alias CONF_baseline_always_on : std_logic is basic_control(1);
   alias CONF_del_direction      : std_logic is basic_control(2);
-  alias CONF_del_loadn          : std_logic is basic_control(3);
+  alias CONF_del_load           : std_logic is basic_control(3);
   alias CONF_alignen_b          : std_logic is basic_control(16);
   alias CONF_testpat_b          : std_logic is basic_control(17);
   alias CONF_data_shifted_b     : std_logic is basic_control(18);
@@ -117,7 +117,7 @@ THE_INPUT_A : entity work.adc_input
     
     DEL_CFLAG      => open,
     DEL_DIRECTION  => CONF_del_direction,
-    DEL_LOADN      => CONF_del_loadn,
+    DEL_LOADN      => not CONF_del_load,
     DEL_MOVE       => STROBE_del_move,
         
     DATA_OUT       => data_in_a,
@@ -138,7 +138,7 @@ THE_INPUT_B : entity work.adc_18bit_input
     CONF_DATA_SHIFTED => CONF_data_shifted_b,
     DEL_CFLAG      => open,
     DEL_DIRECTION  => CONF_del_direction,
-    DEL_LOADN      => CONF_del_loadn,
+    DEL_LOADN      => not CONF_del_load,
     DEL_MOVE       => STROBE_del_move_b,
     
     

diff --git a/adc/source/adc_input.vhd b/adc/source/adc_input.vhd
index 5360c57aad0d308bd6ea12b092a5a49e9d9db75b..f041fff340035a43a690d25695802ca3c6666075 100644 (file)
--- a/adc/source/adc_input.vhd
+++ b/adc/source/adc_input.vhd
@@ -63,10 +63,10 @@ THE_INPUT : entity work.input_4ch
     alignwd   => SHIFT_ALIGN_IN,
     clkin     => CLK_ADCRAW, 
     sclk      => clk_data,
-    data_cflag      => del_cflag,
-    data_direction  => del_direction,
-    data_loadn      => del_loadn,
-    data_move       => del_move,
+    data_cflag      => DEL_CFLAG,
+    data_direction  => DEL_DIRECTION,
+    data_loadn      => DEL_LOADN,
+    data_move       => DEL_MOVE,
     
     datain    => ADC_DATA, 
     q         => data_in

diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd
index 8e9aa538827c2233db819f11dbe760127e36e4a6..45aa85558c36c93f2a2b6274e3301f9a580c7c62 100644 (file)
--- a/adc/source/adc_processor.vhd
+++ b/adc/source/adc_processor.vhd
@@ -334,13 +334,17 @@ end process;
 -------------------------------------------------------------------------------  
   proc_baseline_calc : process begin  
     wait until rising_edge(CLK);
-    if CONTROL_baseline_reset = '1' or reg_CONFIG.baseline_fix = '1' then
-      baseline_averages <= x"000" & reg_CONFIG.baseline_fix_value;
+    if reg_CONFIG.baseline_fix = '1' then
+      baseline_averages <= (others => '0');
+      baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_CONFIG.baseline_fix_value;
+    elsif CONTROL_baseline_reset = '1'  then
+      baseline_averages <= (others => '0');
+      baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_CONFIG.baseline_fix_value;
       last_CONTROL_baseline_reset <= CONTROL_baseline_reset;
     elsif last_CONTROL_baseline_reset = '1' and reg2_ram_remove = '1' then
       last_CONTROL_baseline_reset <= '0';
       baseline_averages <= (others => '0');
-      baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= resize(reg_ram_data_out(19 downto 0),20);  
+      baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_ram_data_out(19 downto 0);  
     elsif reg2_ram_remove = '1' and (reg_ram_data_out(23) = '0' or reg_CONFIG.baseline_always_on = '1') then
       baseline_averages <= baseline_averages 
                               + resize(reg_ram_data_out(19 downto 0),32)