signal int2med : int2med_array_t(0 to INTERFACE_NUM); -- 1 more due to uplink
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdccal_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx, bus_mbs_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdccal_tx, buscts_tx, bus_mbs_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX;
signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
signal cts_ipu_code : std_logic_vector(7 downto 0);
signal cts_ipu_status_bits : std_logic_vector(31 downto 0);
signal cts_ipu_busy : std_logic;
+
+ signal async_ext_trig : std_logic;
+ signal mbs_trigger : std_logic;
+
+ signal mbs_local_trigger_num_in : std_logic_vector(15 downto 0);
+ signal mbs_local_trigger_in : std_logic;
-- new
signal io_dataready_out : std_logic_vector(7 downto 0);
signal reset_via_cri : std_logic := '0';
signal last_cri_resetPulse : std_logic;
+ attribute syn_keep of bus_mbs_rx : signal is true;
+ attribute syn_preserve of bus_mbs_rx : signal is true;
+
-- component trb_net16_cri_interface is
-- generic(
-- INCLUDE_READOUT : std_logic := '0';
gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate
- cts_rdo_additional_data(31 + i*32 downto 32*i) <= x"00000000";--cts_rdo_additional(i).data;
- cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= x"00000000";--cts_rdo_additional(i).statusbits;
+ cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data;
+ cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits;
- cts_rdo_additional_write(i) <= '0';--cts_rdo_additional(i).data_write;
- cts_rdo_additional_finished(i) <= '1';--cts_rdo_additional(i).data_finished;
+ cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write;
+ cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished;
end generate;
gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
FEE_DATA_FINISHED_OUT => cts_rdo_finished
);
- cts_addon_triggers_in(1 downto 0) <= trig_gen_out_i when rising_edge(clk_sys);
+ cts_addon_triggers_in(1 downto 0) <= '0' & mbs_trigger when rising_edge(clk_sys);
buscts_tx.nack <= '0';
buscts_tx.ack <= '0';
+
+---------------------------------------------------------------------------
+-- MBS
+---------------------------------------------------------------------------
+ THE_LOCAL_MBS_CREATE : process
+ variable cnt : unsigned(16 downto 0) := (others => '0');
+ begin
+ wait until rising_edge(clk_sys);
+ mbs_local_trigger_in <= '0';
+ if (reset_i = '1') then
+ cnt := 0;
+ mbs_local_trigger_num_in <= (others => '0');
+ else
+ cnt := cnt + 1;
+ if (cnt = 100000) then
+ mbs_local_trigger_in <= '1';
+ mbs_local_trigger_num_in <= std_logic_vector(unsigned(mbs_local_trigger_num_in) + 1);
+ cnt := 0;
+ end if;
+ end if;
+ end process;
+
+
+ THE_MBS_MASTER : entity work.mbs_master
+ port map (
+ CLK => clk_sys,
+ RESET_IN => reset_i,
+
+ MBS_CLOCK_OUT => open,
+ MBS_DATA_OUT => mbs_trigger,
+
+ --data output for read-out
+ TRIGGER_IN => mbs_local_trigger_in,
+ TRIGGER_NUMBER_IN => mbs_local_trigger_num_in,
+ DATA_OUT => open,
+ WRITE_OUT => open,
+ FINISHED_OUT => open,
+ STATUSBIT_OUT => open
+ );
+
+
+ THE_MBS_REC : entity work.mbs_recv
+ port map (
+ CLK => clk_sys,
+ RESET_IN => reset_i,
+
+ MBS_IN => mbs_trigger,
+ CLK_200 => clk_full_osc,
+
+ TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1),
+ TRG_SYNC_OUT => cts_ext_trigger,
+
+ TRIGGER_IN => cts_rdo_rx.data_valid,
+ TRG_NUMBER_IN => cts_trg_number,
+ TRG_CODE_IN => cts_trg_code,
+ TIMING_TRG_IN => cts_trigger_out,
+
+ DATA_OUT => cts_rdo_additional(0).data,
+ WRITE_OUT => cts_rdo_additional(0).data_write,
+ FINISHED_OUT => cts_rdo_additional(0).data_finished,
+ STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
+
+ REGIO_IN => bus_mbs_rx,
+ REGIO_OUT => bus_mbs_tx,
+
+ CONTROL_REG_IN => cts_ext_control,
+ STATUS_REG_OUT => cts_ext_status,
+ HEADER_REG_OUT => cts_ext_header,
+
+ DEBUG => cts_ext_debug
+ );
+
+
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 11,
+ PORT_NUMBER => 12,
PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"e000",
- 7 => x"ef00", 8 => x"a000", 9 => x"8300", 10 => x"e100", others => x"0000"),
+ 7 => x"ef00", 8 => x"a000", 9 => x"8300", 10 => x"e100", 11 => x"e400", others => x"0000"),
PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 4,
- 7 => 8 , 8 => 11, 9 => 8, 10 => 8, others => 0),
+ 7 => 8 , 8 => 11, 9 => 8, 10 => 8, 11 => 2, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(8) => buscts_rx,
BUS_RX(9) => buscrireg_rx,
BUS_RX(10)=> busCriDatadbgReg_rx,
+ BUS_RX(11)=> bus_mbs_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bustc_tx,
BUS_TX(2) => bussci_tx(0),
BUS_TX(8) => buscts_tx,
BUS_TX(9) => buscrireg_tx,
BUS_TX(10)=> busCriDatadbgReg_tx,
+ BUS_TX(11)=> bus_mbs_tx,
STAT_DEBUG => open
);
--TRIGGER_TO_CTS <= trig_gen_out_i(1);
--RJ45_SIG_4 <= trig_gen_out_i(0);
--TRIGGER_OUT <= RJ45_SIG_1;
- cts_ext_trigger <= TRIGGER_IN; --
+ --cts_ext_trigger <= TRIGGER_IN; --
TRIGGER_OUT <= cts_trigger_out; -- trigger from internal CTS to DiRICH/Power
monitor_inputs_i(11 downto 0) <= BACK_TRIG1;
constant ADDON_LINE_COUNT : integer := 2;--44;
constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
+ -- constant FPGA_SIZE : string := "149KUM";
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
constant INCLUDE_TDC : integer := c_NO;
constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
- constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO;
+ constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
constant ETM_ID : std_logic_vector(7 downto 0);
- constant cts_rdo_additional_ports : integer := 2;-- INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC
+ constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC
--constant CFG_MODE : integer := c_NO;--*2 + USE_BACKPLANE;
begin
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+ t(3 downto 0) := std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4));
+ --t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ --t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC
-- t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
jspc29 / dirich.git / commitdiff