--- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
-- Module Version: 4.8
---X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 19 -depth 16 -no_enable -pe 0 -pf 0 -fill -e
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16 -width 19 -depth 16 -no_enable -pe -1 -pf 0 -fill -e
--- Fri Jun 18 11:50:14 2010
+-- Mon Jun 21 13:20:26 2010
library IEEE;
use IEEE.std_logic_1164.all;
WrEn: in std_logic;
RdEn: in std_logic;
Reset: in std_logic;
- AmEmptyThresh: in std_logic_vector(3 downto 0);
AmFullThresh: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(18 downto 0);
WCNT: out std_logic_vector(4 downto 0);
Empty: out std_logic;
Full: out std_logic;
- AlmostEmpty: out std_logic;
AlmostFull: out std_logic);
end fifo_19x16_obuf;
signal rden_i_inv: std_logic;
signal invout_0: std_logic;
signal r_nw: std_logic;
- signal rcnt_reg_3_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal full_i: std_logic;
signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
signal wptr_4: std_logic;
signal rptr_4: std_logic;
- signal rcnt_reg_4: std_logic;
signal ifcount_0: std_logic;
signal ifcount_1: std_logic;
signal bdcnt_bctr_ci: std_logic;
signal co2: std_logic;
signal co1: std_logic;
signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
signal co0_1: std_logic;
signal co1_1: std_logic;
signal cmp_le_1: std_logic;
signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
signal r_ctr_ci: std_logic;
signal ircount_2: std_logic;
signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
signal co0_4: std_logic;
signal ircount_4: std_logic;
signal co2_2: std_logic;
signal rcount_4: std_logic;
signal co1_4: std_logic;
- signal rcnt_sub_0: std_logic;
- signal r_nw_inv_inv: std_logic;
- signal rcount_0: std_logic;
- signal r_nw_inv: std_logic;
- signal rcnt_sub_1: std_logic;
- signal rcnt_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rcount_1: std_logic;
- signal rcount_2: std_logic;
- signal rcnt_sub_3: std_logic;
- signal rcnt_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rcount_3: std_logic;
- signal rcnt_sub_msb: std_logic;
- signal co2_3d: std_logic;
- signal co2_3: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal rcnt_reg_0: std_logic;
- signal rcnt_reg_1: std_logic;
- signal co0_6: std_logic;
- signal rcnt_reg_2: std_logic;
- signal rcnt_reg_3: std_logic;
- signal co1_6: std_logic;
- signal ae_set_clrsig: std_logic;
- signal ae_set_setsig: std_logic;
- signal ae_set_d: std_logic;
- signal ae_set_d_c: std_logic;
signal wcnt_sub_0: std_logic;
signal cnt_con_inv: std_logic;
+ signal rptr_0: std_logic;
signal cnt_con: std_logic;
signal wcount_0: std_logic;
signal wcnt_sub_1: std_logic;
signal wcnt_sub_2: std_logic;
- signal co0_7: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
signal wcount_1: std_logic;
signal wcount_2: std_logic;
signal wcnt_sub_3: std_logic;
signal wcnt_sub_4: std_logic;
- signal co1_7: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_3: std_logic;
signal wcount_3: std_logic;
signal wcnt_sub_msb: std_logic;
- signal co2_4d: std_logic;
- signal co2_4: std_logic;
+ signal co2_3d: std_logic;
+ signal co2_3: std_logic;
signal wren_i: std_logic;
- signal cmp_ci_3: std_logic;
+ signal cmp_ci_2: std_logic;
signal wcnt_reg_0: std_logic;
signal wcnt_reg_1: std_logic;
- signal co0_8: std_logic;
+ signal co0_6: std_logic;
signal wcnt_reg_2: std_logic;
signal wcnt_reg_3: std_logic;
- signal co1_8: std_logic;
+ signal co1_6: std_logic;
signal wcnt_reg_4: std_logic;
signal af_set: std_logic;
signal af_set_c: std_logic;
- signal rdataout18: std_logic;
- signal rdataout17: std_logic;
- signal rdataout16: std_logic;
signal scuba_vlo: std_logic;
- signal rdataout15: std_logic;
- signal rdataout14: std_logic;
- signal rdataout13: std_logic;
- signal rdataout12: std_logic;
- signal rdataout11: std_logic;
- signal rdataout10: std_logic;
- signal rdataout9: std_logic;
- signal rdataout8: std_logic;
- signal rdataout7: std_logic;
- signal rdataout6: std_logic;
- signal rdataout5: std_logic;
- signal rdataout4: std_logic;
- signal rdataout3: std_logic;
- signal rdataout2: std_logic;
- signal rdataout1: std_logic;
- signal rdataout0: std_logic;
- signal rptr_3: std_logic;
- signal rptr_2: std_logic;
- signal rptr_1: std_logic;
- signal rptr_0: std_logic;
- signal dec0_wre3: std_logic;
- signal wptr_3: std_logic;
- signal wptr_2: std_logic;
- signal wptr_1: std_logic;
- signal wptr_0: std_logic;
-- local component declarations
component AGEB2
port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
- component DPR16X4A
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
- RAD0: in std_logic; RAD1: in std_logic;
- RAD2: in std_logic; RAD3: in std_logic;
- WAD0: in std_logic; WAD1: in std_logic;
- WAD2: in std_logic; WAD3: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic);
- end component;
component VHI
port (Z: out std_logic);
end component;
component XOR2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
attribute GSR : string;
- attribute initval of LUT4_2 : label is "0x3232";
attribute initval of LUT4_1 : label is "0x3232";
- attribute initval of LUT4_0 : label is "0x8000";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_19x16_obuf.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
attribute GSR of FF_32 : label is "ENABLED";
attribute GSR of FF_31 : label is "ENABLED";
attribute GSR of FF_30 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t8: AND2
+ AND2_t5: AND2
port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_8: INV
+ INV_5: INV
port map (A=>full_i, Z=>invout_2);
- AND2_t7: AND2
+ AND2_t4: AND2
port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_7: INV
+ INV_4: INV
port map (A=>empty_i, Z=>invout_1);
- AND2_t6: AND2
+ AND2_t3: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t5: XOR2
+ XOR2_t2: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_6: INV
+ INV_3: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_5: INV
+ INV_2: INV
port map (A=>wren_i, Z=>wren_i_inv);
- LUT4_2: ROM16X1
+ LUT4_1: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
AD0=>empty_i, DO0=>empty_d);
- LUT4_1: ROM16X1
+ LUT4_0: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_wre3);
-
- AND2_t4: AND2
+ AND2_t1: AND2
port map (A=>rden_i, B=>invout_0, Z=>r_nw);
- INV_4: INV
- port map (A=>wren_i, Z=>invout_0);
-
- INV_3: INV
- port map (A=>r_nw, Z=>r_nw_inv);
-
- XOR2_t3: XOR2
- port map (A=>wcount_4, B=>rcount_4, Z=>rcnt_sub_msb);
-
- INV_2: INV
- port map (A=>r_nw_inv, Z=>r_nw_inv_inv);
-
INV_1: INV
- port map (A=>rcnt_reg_3, Z=>rcnt_reg_3_inv);
-
- AND2_t2: AND2
- port map (A=>rcnt_reg_4, B=>rcnt_reg_3_inv, Z=>ae_set_clrsig);
-
- AND2_t1: AND2
- port map (A=>rcnt_reg_4, B=>rcnt_reg_3, Z=>ae_set_setsig);
+ port map (A=>wren_i, Z=>invout_0);
XOR2_t0: XOR2
port map (A=>wcount_4, B=>rptr_4, Z=>wcnt_sub_msb);
INV_0: INV
port map (A=>cnt_con, Z=>cnt_con_inv);
- FF_57: FD1P3DX
+ pdp_ram_0_0_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
+ ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
+ ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
+ BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
+ CLKW=>Clock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
+ ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_56: FD1P3DX
+ FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_55: FD1P3DX
+ FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_54: FD1P3DX
+ FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_53: FD1P3DX
+ FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_52: FD1S3BX
+ FF_27: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_51: FD1S3DX
+ FF_26: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_50: FD1P3BX
+ FF_25: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
- FF_49: FD1P3DX
+ FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_48: FD1P3DX
+ FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_47: FD1P3DX
+ FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_46: FD1P3DX
+ FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_45: FD1P3BX
+ FF_20: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
- FF_44: FD1P3DX
+ FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_43: FD1P3DX
+ FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_42: FD1P3DX
+ FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_41: FD1P3DX
+ FF_16: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_40: FD1P3DX
+ FF_15: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
- FF_39: FD1P3DX
+ FF_14: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
- FF_38: FD1P3DX
+ FF_13: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
- FF_37: FD1P3DX
+ FF_12: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
- FF_36: FD1P3DX
+ FF_11: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
- FF_35: FD1P3DX
+ FF_10: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
- FF_34: FD1P3DX
+ FF_9: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
- FF_33: FD1P3DX
+ FF_8: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
- FF_32: FD1P3DX
+ FF_7: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
- FF_31: FD1P3DX
+ FF_6: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
- FF_30: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(0));
-
- FF_29: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(1));
-
- FF_28: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(2));
-
- FF_27: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(3));
-
- FF_26: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(4));
-
- FF_25: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(5));
-
- FF_24: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(6));
-
- FF_23: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(7));
-
- FF_22: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(8));
-
- FF_21: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(9));
-
- FF_20: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(10));
-
- FF_19: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(11));
-
- FF_18: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(12));
-
- FF_17: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(13));
-
- FF_16: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(14));
-
- FF_15: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(15));
-
- FF_14: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(16));
-
- FF_13: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(17));
-
- FF_12: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>Q(18));
-
- FF_11: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0);
-
- FF_10: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1);
-
- FF_9: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2);
-
- FF_8: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3);
-
- FF_7: FD1S3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4);
-
- FF_6: FD1S3BX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
-
FF_5: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2,
NC0=>ircount_4, NC1=>open);
- rcnt_0: FSUB2B
- port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
- S1=>rcnt_sub_0);
-
- rcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2,
- BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2);
-
- rcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>rcnt_sub_msb, B0=>rcount_3,
- B1=>scuba_vlo, BI=>co1_5, BOUT=>co2_3, S0=>rcnt_sub_3,
- S1=>rcnt_sub_4);
-
- rcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_3, COUT=>open, S0=>co2_3d, S1=>open);
-
- ae_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- ae_set_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
- B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6);
-
- ae_set_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
- B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6);
-
- ae_set_cmp_2: AGEB2
- port map (A0=>ae_set_setsig, A1=>scuba_vlo, B0=>ae_set_clrsig,
- B1=>scuba_vlo, CI=>co1_6, GE=>ae_set_d_c);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
- S1=>open);
-
wcnt_0: FSUB2B
port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
- BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0);
+ BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
wcnt_1: FSUB2B
port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
+ BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
wcnt_2: FSUB2B
port map (A0=>wcount_3, A1=>wcnt_sub_msb, B0=>rptr_3,
- B1=>scuba_vlo, BI=>co1_7, BOUT=>co2_4, S0=>wcnt_sub_3,
+ B1=>scuba_vlo, BI=>co1_5, BOUT=>co2_3, S0=>wcnt_sub_3,
S1=>wcnt_sub_4);
wcntd: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_4, COUT=>open, S0=>co2_4d, S1=>open);
+ B1=>scuba_vlo, CI=>co2_3, COUT=>open, S0=>co2_3d, S1=>open);
af_set_cmp_ci_a: FADD2B
port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
af_set_cmp_0: AGEB2
port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8);
+ B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
af_set_cmp_1: AGEB2
port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8);
+ B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
af_set_cmp_2: AGEB2
port map (A0=>wcnt_reg_4, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co1_8, GE=>af_set_c);
-
- a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
- S1=>open);
+ B1=>scuba_vlo, CI=>co1_6, GE=>af_set_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
- fifo_pfu_0_0: DPR16X4A
- port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
- DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16,
- DO1=>rdataout17, DO2=>rdataout18, DO3=>open);
-
- fifo_pfu_0_1: DPR16X4A
- port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
- DI3=>Data(15), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12,
- DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15);
-
- fifo_pfu_0_2: DPR16X4A
- port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
- DI3=>Data(11), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8,
- DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11);
-
- fifo_pfu_0_3: DPR16X4A
- port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
- WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
- RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
- WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5,
- DO2=>rdataout6, DO3=>rdataout7);
-
- fifo_pfu_0_4: DPR16X4A
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
- RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
- WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1,
- DO2=>rdataout2, DO3=>rdataout3);
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ S1=>open);
WCNT(0) <= fcount_0;
WCNT(1) <= fcount_1;
for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
for all:INV use entity ecp2m.INV(V); end for;
for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
for all:VHI use entity ecp2m.VHI(V); end for;
for all:VLO use entity ecp2m.VLO(V); end for;
for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
end for;
end Structure_CON;
jspc29 / trbnet.git / commitdiff