*** empty log message ***

diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj
index 7787c50aed299d25aa53c4ac57fc766c735c64b4..1001520e7b3264831cdfa75d3df5b9dbcf944a1d 100644 (file)
--- a/tdc_test/trb3_periph.prj
+++ b/tdc_test/trb3_periph.prj
@@ -138,14 +138,15 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "./trb3_periph.vhd"
 
-add_file -vhdl -lib "work" "source/Adder_320.vhd"
+add_file -vhdl -lib "work" "source/Adder_304.vhd"
 add_file -vhdl -lib "work" "source/bit_sync.vhd"
-add_file -vhdl -lib "work" "source/Channel_320.vhd"
-add_file -vhdl -lib "work" "source/Encoder_320_Bit.vhd"
+add_file -vhdl -lib "work" "source/Channel.vhd"
+add_file -vhdl -lib "work" "source/Encoder_304_Bit.vhd"
 add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd"
 add_file -vhdl -lib "work" "source/Reference_channel.vhd"
 add_file -vhdl -lib "work" "source/reset_generator.vhd"
+add_file -vhdl -lib "work" "source/ROM_Encoder.vhd"
 add_file -vhdl -lib "work" "source/ROM_FIFO.vhd"
 add_file -vhdl -lib "work" "source/TDC.vhd"
 add_file -vhdl -lib "work" "source/up_counter.vhd"
-add_file -vhdl -lib "work" "source/ROM_Encoder.vhd"
+

diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd
index 208bc9e9333e1c0ff161a6e54d70351136149962..e6399c3a8315dc3668b00a20ef61378078bc5640 100644 (file)
--- a/tdc_test/trb3_periph.vhd
+++ b/tdc_test/trb3_periph.vhd
@@ -592,7 +592,7 @@ begin
 
   THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER        => 16,       -- Number of TDC channels
+      CHANNEL_NUMBER        => 8,       -- Number of TDC channels
       TRG_WIN_PRE           => "00001100100",  -- Pre-Trigger window width
       TRG_WIN_POST          => "00001100100")  -- Post-Trigger window width
     port map (
@@ -600,7 +600,7 @@ begin
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      HIT_IN                => DQLL(14 downto 0),  -- Channel start signals
+      HIT_IN                => DQLL(6 downto 0),  -- Channel start signals
 --
       -- Trigger signals from handler
       TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet